CN109188243A - A kind of PCB interconnection method for testing reliability - Google Patents
A kind of PCB interconnection method for testing reliability Download PDFInfo
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- CN109188243A CN109188243A CN201811002911.2A CN201811002911A CN109188243A CN 109188243 A CN109188243 A CN 109188243A CN 201811002911 A CN201811002911 A CN 201811002911A CN 109188243 A CN109188243 A CN 109188243A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
A kind of PCB interconnection method for testing reliability, the method uses the pore chain of special designing, the type of pore chain mesoporous is through-hole, buried via hole, Microvia or Microvia, the layer that hole is crossed over is identical as the layer that homogeneous hole in PCB product figure is crossed over, top layer and the lowest level that hole crosses over all layers is arranged in connection line between pore chain mesoporous and hole, and the both ends of pore chain are provided with testing weld pad；The method uses DC current regulator power supply and resistance measuring instrument, the resistance of pore chain is first measured at room temperature, then test voltage value and test current value are set on DC current regulator power supply, output electric current is applied on the pore chain of design, pore chain temperature is set to reach the set temperature range within 150-350 DEG C in 5-100 seconds, then stop applying test electric current, pore chain is cooled to room temperature, measure the resistance of pore chain, if during testing electric current application, under the voltage of setting, current threshold of the actual loading electric current lower than setting in circuit, or it is more than the threshold values set that test electric current, which applies the pore chain resistance variations of front and back, then pore chain, which is considered as, does not pass through test.Test method test speed of the invention is fast, and at low cost, convenient test, sampling proportion is big, can detect the interconnection defect for slight through-hole, buried via hole, blind hole or the Microvia that PCB electrical testing cannot detect.
Description
Technical field
The present invention relates to a kind of PCB interconnection method for testing reliability and resolution chart more particularly to PCB aperture to interconnect reliability
Test method, the method can detect slight PCB aperture interconnection defect.
Background technique
The circuit network of multi-layer PCB is and the various holes composition of each layer of connection by the metallic circuit of each layer, pad,
Hole in PCB includes through-hole, buried via hole, blind hole and Microvia, and wherein through-hole penetrates through all layers of PCB, it may be connected to random layer,
Buried via hole generally runs through any 2 layers or multilayer in addition to PCB two outside layers, it may be connected to arbitrarily in addition to PCB two outside layers
Internal layer, blind hole then generally connection include an outer layer 2 layers or multilayer, Microvia then generally connects adjacent 2 layers, therefore
It includes through-hole, buried via hole, blind hole and Microvia to realize that the interconnection of PCB, which is by the hole in PCB,.
The interconnection reliability of PCB mostlys come from the interconnection reliability of electroplating ventilating hole, buried via hole, blind hole and Microvia, packet
It includes:
1) the conducting reliability of the intercommunicating pores itself such as through-hole, buried via hole, blind hole and Microvia；
Due to the difference of baseplate material and intercommunicating pore coating the physical property variation after heated, when heated, the side Z of dielectric substrate material
To thermal expansion so that intercommunicating pore coating is also forced and is deformed, to generate stress on intercommunicating pore, intercommunicating pore thickness of coating
It is the master for leading to hole own reliability that partially thin, coating, which contains the plating defects such as bubble, thickness of coating are uneven, hole wall and coating are coarse,
Want reason；
2) connection reliability of the intercommunicating pores such as through-hole, buried via hole, blind hole and Microvia and inside and outside sandwich circuit；
When brill is dirty, resist remains and is precipitated and other foreign matters are remained on the interconnection face of intercommunicating pore and inside and outside sandwich circuit, or
When defect occurs in chemical layers of copper on person interconnection face, under the stress for generation of expanding with heat and contract with cold, hole coating is separated with inside and outside sandwich circuit,
To lead to the problem of interconnection reliability.
Common electrical testing cannot sort out above hole plating defect and interconnection defect, because of the hole of this kind of defect
Itself and be still connected with inside and outside sandwich circuit with hole, even if under relatively serious situation, hole occur slight fracture or
Hole coating is separated with inside and outside sandwich circuit, but when carrying out electrical testing, since electrical testing machine clamp acts on, on the pad of hole by
Pressure it is larger, these, which break or separate, to pass through electrical testing together by " pressing ".
If the PCB with these light defects is sent to client, become PCBA by assembling, or becomes final products friendship
Pay into user's hand after, by the circulation change of environment temperature, these light defects can become to deteriorate, eventually lead to open circuit and
Product failure, such PCB manufacturer may face customer complaint and huge reparation.
PCB interconnects method for testing reliability.At present PCB interconnect method for testing reliability include:
1. gas phase high/low temperature recycles, gas phase high/low temperature loop test is that test sample is alternately placed in high temperature and cryogenic gas ring
Border regular hour and circulation, and detect the situation of change of the various electrical properties of test sample；
2. liquid phase high/low temperature recycles, liquid phase high/low temperature loop test is that test sample is alternately placed in high temperature and cryogenic liquid ring
Border regular hour and circulation, and detect the situation of change of the various electrical properties of test sample；
3. multi-reflow, multi-reflow test is by test sample by repeatedly simulation solder reflow process, and detects test specimens
The situation of change of the various electrical properties of product reflux front and back.
The shortcomings that these tests is that the time of test is long, and testing cost is high, and test belongs to destructive testing, test samples
Ratio is not high.Due to needing attached gas to heat and refrigerating plant, equipment very bulky complex required for testing, and due to
The transmitting of heat is carried out using gas or liquid, therefore the time for carrying out alternate cycles needs is long, common one cycle
The time needed was at 30 minutes to one hour or so.
Summary of the invention
The purpose of the present invention is to provide a kind of PCB interconnection method for testing reliability can quickly be examined by the method
Slight PCB aperture interconnects defect out.
In order to achieve the above objectives, the technical scheme is that
Pore chain is designed, the type in the hole of pore chain is through-hole, buried via hole, blind hole or Microvia.The quantity of pore chain mesoporous is 10-500,
The line number of pore chain mesoporous is 1-10 row, and the columns of pore chain mesoporous is 10-50 column, and the bore dia of pore chain is same in PCB product figure
The 50-200% of the minimum diameter in the hole of type, the layer that hole is crossed over is identical as the layer that homogeneous hole in PCB product figure is crossed over,
Connection line between pore chain mesoporous and hole is arranged in top layer and the lowest level that hole crosses over all layers, pore chain mesoporous and hole it
Between connection line line width be hole perimeter 50%-200%.The both ends of pore chain are provided with testing weld pad, and pad is rectangular or circle
Shape, the pad diameter in the hole in pore chain are the 50-200% of the minimum pad diameter in the hole of same type in PCB product figure, pore chain
In adjacent hole pad edge distance be 0.05-2mm.
Sampling determines test used test current value, and steps are as follows:
1) testing time and Range of measuring temp are first set；
2) then apply the testing time set in step 1 on the pore chain of sampling using different DC currents, if sampling
Pore chain temperature reach the Range of measuring temp of setting when completing the testing time of the setting, then select the current value to be used as this
The test current value of this kind of pore chain of model, if the temperature of the pore chain of sampling is not up to when completing the testing time of the setting
The Range of measuring temp of setting then adjusts the pore chain that electric current retests sampling, until the temperature of all sampling pore chains is at certain
Under electric current, the Range of measuring temp of setting is reached when completing the testing time of the setting, selects the current value as the model
This kind of pore chain test current value.
Test, steps are as follows:
1) resistance of pore chain is measured at room temperature；
2) test voltage value and test current value are set on DC current regulator power supply, and output test electric current is applied to pore chain
On, so that the temperature of pore chain is reached the Range of measuring temp of setting within the testing time of setting, then stop applying test electric current,
Pore chain is cooled to room temperature；
3) resistance of pore chain is measured at room temperature；
4) judge whether pore chain passes through test.
The standard for judging whether pore chain passes through test includes following two:
1) judged according to actual loading curent change, if within the testing time that test electric current applies, under the voltage of setting,
Actual loading electric current is not less than the threshold values of setting in circuit, then pore chain is considered as through test, if the survey applied in test electric current
It tries in the time, under the voltage of setting, for actual loading electric current lower than the threshold values of setting, then pore chain, which is considered as, does not pass through survey in circuit
Examination；
2) judged according to resistance variations, if the resistance variations of pore chain are no more than the valve of setting at room temperature before and after applying test electric current
Value, then pore chain is considered as through test, if the resistance variations of pore chain are more than the threshold values of setting at room temperature before and after applying test electric current,
Then pore chain hole is not pass through test.If judging whether pore chain fails according to resistance variations, testing procedure can be without
And the 3) step 1).
The method test speed is fast, at low cost, and convenient test, sampling proportion is big, can detect that PCB electrical testing cannot
The slight PCB aperture interconnection defect detected.
Beneficial effects of the present invention:
Compared with interconnecting method for testing reliability with traditional PCB, the advantages of test method of the invention, is:
1) test speed is fast.It, can be by a piece of PCB in making sheet since the electric current that the test of same pore chain uses is identical
Same pore chain is together in series while being tested using the route on fixture or pcb board；
2) pore chain flexible layout is tested.Test pore chain can be set on the nonfunctional frame of the repetitive unit in PCB in making sheet,
Also the edge in PCB in making sheet can be set, do not destroy original PCB product figure and design, be not take up useful region, do not increase
Add PCB material cost；
3) testing cost is low, convenient test, and test equipment is simple.Test equipment is mainly DC current regulator power supply, and test can
To use or be not suitable for fixture；
4) test result is simple and clear.It is only necessary to observe the curent change of power supply output to can determine whether to test whether to pass through；
5) test process does not damage product, therefore sampling proportion is big.A piece of PCB can be required in making sheet according to user, design
The test pore chain of different number, therefore all PCB can accomplish absolutely all tests in making sheet.
Detailed description of the invention
Fig. 1 is layout of the pore chain in PCB in making sheet in the embodiment of the present invention.
Fig. 2 is the sectional view in various holes in the embodiment of the present invention.
Fig. 3 is the top view of single order Microvia pore chain in the embodiment of the present invention.
Fig. 4 is the sectional view of single order Microvia pore chain in the embodiment of the present invention.
Fig. 5 is the top view of second order Microvia pore chain in the embodiment of the present invention.
Fig. 6 is the sectional view of second order Microvia pore chain in the embodiment of the present invention.
Fig. 7 is the top view of through-hole pore chain in the embodiment of the present invention.
Fig. 8 is the sectional view of through-hole pore chain in the embodiment of the present invention.
Fig. 9 is the top view of buried via hole pore chain in the embodiment of the present invention.
Figure 10 is the sectional view of buried via hole pore chain in the embodiment of the present invention.
Specific embodiment
A 6 layers of second order HDI printed circuit board, making sheet 101 layout as shown in Figure 1, it is a piece of making sheet include 9 lists
Member 102, it is Elementary Function graphics field that each unit 102, which has non-functional element sides 103,104, and 105 be edges of boards nonfunctional
Region.It is laid out pore chain in the element sides nonfunctional region 103 of each unit 102, including the single order Microvia pore chain across 2 layers
106, across 3 layers of superposition Microvia pore chain 107, across 6 layers of through-hole pore chain 108, across 4 layers of buried via hole pore chain 109, totally 4
Kind pore chain.
The hole that making sheet 101 includes the schematic diagram of the section structure as shown in Fig. 2, including: cross over 2 layers, from first layer
The 205 single order Microvia 201' to the single order Microvia 201 of the second layer 206 or from layer 5 209 to layer 6 210；Across 3
Layer, from first layer 205 to 207 second order Microvia 202 of third layer or from the 4th layer 208 to the second order Microvia of layer 6 210
202'；Across 6 layers, from first layer 205 to the through-hole 203 of layer 6 210；Across 4 layers, from the second layer 206 to layer 5 209
Buried via hole 204.Amount to 4 kinds of holes.205 be first layer in figure, and 206 be the second layer, and 207 be third layer, and 208 be the 4th layer, and 209 be the
Five layers, 210 be layer 6.
Pore chain design is as follows.
All 4 kinds of pore chains include 1 row 12 column hole, and the hole count of every pore chain is 12.
Across 2 layers of single order Microvia 201 pore chain 106 top view as shown in figure 3, sectional view is as shown in Figure 4.301
It is the pad of single order Microvia, diameter and the same type in Elementary Function graphics field of pad 303 for testing weld pad, 303
The diameter of minimum single order Microvia pad is identical, the route of the top layer of 302 layers crossed over by single order Microvia 201, route
Width is identical as the perimeter of single order Microvia 201, the 304 undermost routes crossed over by single order Microvia 201, line width
It is identical as the perimeter of single order Microvia 201.Same type in the aperture of single order Microvia 201 and Elementary Function graphics field is most
The aperture of small single order Microvia is identical.
Across 3 layers of second order Microvia 202 pore chain 107 top view as shown in figure 5, sectional view is as shown in Figure 6.501
It is the pad of second order Microvia, diameter and the same type in Elementary Function graphics field of pad 503 for testing weld pad, 503
The diameter of minimum second order Microvia pad is identical, the route of the top layer of 502 layers crossed over by second order Microvia 202, route
Width is identical as the perimeter of second order Microvia 202, the 504 undermost routes crossed over by second order Microvia 202, line width
It is identical as the perimeter of second order Microvia 202.Same type in the aperture of second order Microvia 202 and Elementary Function graphics field is most
The aperture of small second order Microvia is identical.
Across the pore chain 108 of 6 layers of through-hole 203 top view as shown in fig. 7, sectional view as shown in 6 Fig. 8.701 be test
Pad, 703 be the pad of through-hole, the diameter of pad 703 and the minimum vias pad of the same type in Elementary Function graphics field
Diameter it is identical, the route of the top layer of 702 layers crossed over by through-hole 203, line width is identical as the perimeter of through-hole 203,
The 704 undermost routes crossed over by through-hole 203, line width are identical as the perimeter of through-hole 203.The aperture of through-hole 203 with
The aperture of the minimum vias of same type in Elementary Function graphics field is identical.
Across 4 layers of buried via hole 204 pore chain 109 top view as shown in figure 9, sectional view is as shown in Figure 10.901 be test
Pad, 903 be the pad of buried via hole, the diameter of pad 903 and the minimum buried via hole pad of the same type in Elementary Function graphics field
Diameter it is identical, the route of the top layer of 902 layers crossed over by buried via hole 204, line width is identical as the perimeter of buried via hole 204,
The 904 undermost routes crossed over by buried via hole 204, line width are identical as the perimeter of buried via hole 204.The aperture of buried via hole 204 with
The aperture of the minimum buried via hole of same type in Elementary Function graphics field is identical.
Sample testing determines the test current value of various pore chains.The testing time is set as 10 seconds, pore chain temperature setting is
It 200-220 DEG C, extracts at making sheet 5, every every kind of pore chain extraction one in making sheet is applied to hole with different DC currents
On chain, the temperature of pore chain when testing 10 seconds.Electric current is 2.3 ampere-hours, and pore chain temperature is equal at 10 seconds of 5 single order Microvia pore chains
In 200-220 DEG C, the test electric current of single order Microvia pore chain is 2.3 amperes；Electric current is 2.8 ampere-hours, 5 second order Microvias
For pore chain temperature in 200-220 DEG C, the test electric current of second order Microvia pore chain is 2.8 amperes at 10 seconds of pore chain；Electric current is
3.8 ampere-hours, for pore chain temperature in 200-220 DEG C, the test electric current of through-hole pore chain is 3.8 at 10 seconds of 5 through-hole pore chains
Ampere；Electric current is 3.5 ampere-hours, and pore chain temperature is in 200-220 DEG C at 10 seconds of 5 buried via hole pore chains, the survey of buried via hole pore chain
Trying electric current is 3.5 amperes.
Batch testing, sets whether pore chain passes through the standard of test to judge according to actual loading curent change, if
Electric current is tested to apply in the testing time, under the voltage of setting, 95% of DC current lower than setting DC current in circuit, then
Pore chain, which is considered as, does not pass through test.
DC current regulator power supply output test voltage value is set as 36 volts, test current value is 2.3 amperes, is applied to
It is all 10 seconds on the single order Microvia pore chain of making sheet, judged whether to pass through test according to actual loading curent change.
DC current regulator power supply output test voltage value is set as 36 volts, test current value is 2.8 amperes, is applied to
It is all 10 seconds on the second order Microvia pore chain of making sheet, judged whether to pass through test according to actual loading curent change.
DC current regulator power supply output test voltage value is set as 36 volts, test current value is 3.8 amperes, is applied to
It is all 10 seconds on the through-hole pore chain of making sheet, judged whether to pass through test according to actual loading curent change.
DC current regulator power supply output test voltage value is set as 36 volts, test current value is 3.5 amperes, is applied to
It is all 10 seconds on the buried via hole pore chain of making sheet, judged whether to pass through test according to actual loading curent change.
Claims (9)
1. a kind of PCB interconnects method for testing reliability comprising following steps:
1) resistance of pore chain is measured at room temperature；
2) test voltage value and test current value are set on DC current regulator power supply, and output test electric current is applied to pore chain
On, so that the temperature of pore chain is reached the Range of measuring temp of setting within the testing time of setting, then stop applying test electric current,
Pore chain is cooled to room temperature；
3) resistance of pore chain is measured at room temperature；
4) judge whether pore chain passes through test.
2. method as claimed in claim 1, which is characterized in that step 4) judges whether pore chain passes through the standard of test and include
Following two:
1) judged according to actual loading curent change, if within the testing time that test electric current applies, under the voltage of setting,
Actual loading electric current is not less than the threshold values of setting in circuit, then pore chain is considered as through test, if the survey applied in test electric current
It tries in the time, under the voltage of setting, for actual loading electric current lower than the threshold values of setting, then pore chain, which is considered as, does not pass through survey in circuit
Examination, current threshold is set as applying 50%-99%, the further preferred 80%-95% of test electric current, if according to actual loading electric current
Variation judge whether pore chain fails, then can without the 1) with the 3) step；
2) judged according to resistance variations, if the resistance variations of pore chain are no more than the valve of setting at room temperature before and after applying test electric current
Value, then pore chain is considered as through test, if the resistance variations of pore chain are more than the threshold values of setting at room temperature before and after applying test electric current,
Then pore chain is considered as not by test, and resistance variations threshold value setting is 5%-200%, further preferred 10%-50%.
3. method as claimed in claim 1, which is characterized in that test voltage value is 5-50 volts, further preferred 10-36
Volt, test current value is 0.2-20 amperes, 1-10 amperes further preferred.
4. the test electric current on pore chain is applied to when test as claimed in claim 1, which is characterized in that be directed to a certain model
The a certain pore chain of PCB, the set test current value of test are measured by the test method sampled, and extract interconnection pore chain
Number is 3-20, further preferred 3-10.
5. sample testing method as claimed in claim 4 comprising following steps:
1) testing time and Range of measuring temp are first set；
2) then apply the testing time set in step 1 on the pore chain of sampling using different DC currents, if sampling
Pore chain temperature reach the Range of measuring temp of setting when completing the testing time of the setting, then select the current value to be used as this
The test current value of this kind of pore chain of model, if the temperature of the pore chain of sampling is not up to when completing the testing time of the setting
The Range of measuring temp of setting then adjusts the pore chain that electric current retests sampling, until the temperature of all sampling pore chains is at certain
Under electric current, the Range of measuring temp of setting is reached when completing the testing time of the setting, selects the current value as the model
This kind of pore chain test current value.
6. method as claimed in claim 1, which is characterized in that the testing time set as 5-100 seconds, further preferably
10-60 seconds, the Range of measuring temp that pore chain reaches when test was chosen from 150-350 DEG C, further preferably from 150-250 DEG C
It chooses.
7. pore chain as claimed in claim 1, which is characterized in that the type in hole is through-hole, buried via hole, blind hole or Microvia, hole
The quantity of chain mesoporous is 10-500, preferably 20-100, further preferred 30-100；The line number of pore chain mesoporous is 1-10
Row, preferably 1-5 row, further preferred 1-3 row；The columns of pore chain mesoporous is 10-50 column, preferably 10-15 column, bore dia PCB
The 50-200% of the minimum diameter in the hole of same type, preferably 70-150% in product figure, the layer and PCB product figure that hole is crossed over
The layer that middle homogeneous hole is crossed over is identical.
8. pore chain as claimed in claim 1, which is characterized in that the connection line between pore chain mesoporous and hole is arranged in hole institute
Top layer and lowest level across all layers；The line width of connection line between pore chain mesoporous and hole is the 50%- of hole perimeter
200%, the both ends of pore chain are provided with testing weld pad, and pad is rectangular or round；The pad diameter in the hole in pore chain is PCB product
The 50-200% of the minimum pad diameter in the hole of same type, preferably 70-150% in figure；The pad side in the adjacent hole in pore chain
Edge distance is 0.05-2mm, preferably 0.1-1mm.
9. pore chain as claimed in claim 1, which is characterized in that when each unit in making sheet has non-functional unit
Side, and when nonfunctional element sides space is enough, by pore chain layout in non-functional element sides, when each unit in making sheet
There are a non-functional element sides, but when nonfunctional element sides insufficient space is enough or each unit is without non-functional element sides,
Pore chain is laid out in the edges of boards nonfunctional region in making sheet.
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| CN110146804A (en) * | 2019-06-08 | 2019-08-20 | 四会富仕电子科技股份有限公司 | A kind of PCB dynamic conducting method for testing reliability |
| CN110398680A (en) * | 2019-08-14 | 2019-11-01 | 华芯电子(天津)有限责任公司 | A kind of PCB method for testing reliability |
| CN111142010A (en) * | 2020-01-24 | 2020-05-12 | 上海炜绫测试技术有限公司 | PCB interconnection reliability testing method and device |
| CN111142009A (en) * | 2020-01-24 | 2020-05-12 | 上海炜绫测试技术有限公司 | PCB interconnection reliability testing method and device |
| CN111707928A (en) * | 2020-06-29 | 2020-09-25 | 广东浪潮大数据研究有限公司 | Method and device for testing PCB wiring processing capacity |
| CN113064058A (en) * | 2021-04-12 | 2021-07-02 | 万安裕维电子有限公司 | PCB interconnection reliability test method and system |
| CN113109696A (en) * | 2021-04-12 | 2021-07-13 | 万安裕维电子有限公司 | Method for testing performance of PCB conductive hole |
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