CN105629124A - PCB network poor conduction analysis method - Google Patents
PCB network poor conduction analysis method Download PDFInfo
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- CN105629124A CN105629124A CN201610009240.7A CN201610009240A CN105629124A CN 105629124 A CN105629124 A CN 105629124A CN 201610009240 A CN201610009240 A CN 201610009240A CN 105629124 A CN105629124 A CN 105629124A
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- network
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- Analysing Materials By The Use Of Radiation (AREA)
Abstract
The invention discloses a PCB network poor conduction analysis method, comprising steps of inquiring network nodes of a PCB network line, performing network node segmentation to form a segmented network, measuring the resistance of each the segmented network, if the resistance value is greater than the 5M Omega, determining the segmented network as an open circuit, if the range of the resistance value of the resistor is 10 Omega-5M Omega, determining the segmented network as a micro open circuit, if the open circuit is determined, the fault analysis is performed on the through hole or the blind hole or the circuit on the adverse position, if the segmented network is determined as the micro open circuit, performing heating on the corresponding segmented network by letting DC current to go through, and using the infrared thermal imaging instrument to observe the temperature highest point, wherein the temperature highest point is the adverse position, and performing the fault analysis on the adverse position. The invention can fast and accurately find the adverse position in the network circuit and performs analysis.
Description
Technical field
The present invention relates to a kind of analysis method of PCB network poor flow.
Background technology
At present, during the substandard products of PCB (printed circuit board) are analyzed, the network line of PCB often causes because of open circuit losing efficacy. But, for solving Problem of Failure, need to causing that the reason that network line is opened a way is analyzed, way conventional at present is all adopt test device to different contact electrode measurements, owing to the electrode of network line is quite a lot of, the mode efficiency tested one by one of this routine is low, and, the particular problem of the information also more difficult accurate judgement inefficacies such as the electric current of test device feedback, resistance.
Summary of the invention
In order to overcome the deficiencies in the prior art, it is an object of the invention to provide a kind of analysis method of PCB network poor flow, bad position can be found out quickly and accurately in network line and analyzed.
The purpose of the present invention realizes by the following technical solutions:
A kind of analysis method of PCB network poor flow, comprises the following steps:
S1, inquiry PCB network line nexus, and carry out nexus segmentation formed segmented network;
S2, each segmented network is measured resistance respectively, if resistance value is more than 5M ��, then judge that this segmented network is as open circuit, if the Standard resistance range of resistance value is 10 ��-5M ��, then judges that this segmented network is crack;
S3, a. are for being judged as the in the case of of opening a way: the through hole of bad position or blind hole or circuit are carried out defect analysis; When being b. judged as crack for segmented network: corresponding segmented network being passed into DC current and is heated, then observe thermal self-restraint stress with thermal infrared imager, this thermal self-restraint stress is bad position, finally this bad position is carried out defect analysis.
Preferably for the situation that bad position is through hole or blind hole, micro-Sectioning is used to see whether there is porous dehiscence.
It is the situation of circuit preferably for bad position, uses X-ray instrument to observe whether circuit exists crackle, crack.
Preferably, for being observed the bad position drawn by thermal infrared imager, if this bad position is circuit, then X-ray instrument is used to observe whether bad circuit exists breach, micro-crack, if this bad position is through hole or blind hole, then see whether there is micro-crack by slice analysis.
Compared to existing technology, the beneficial effects of the present invention is:
The present invention is by carrying out segmentation to network line, then segmented network is measured respectively, substantially increase the efficiency measuring resistance, also improve accuracy simultaneously, and, by the judgement segmented network of resistance being belonged to open circuit or crack, carry out the poor flow defect analysis method that corresponding enforcement is different, in hgher efficiency.
Accompanying drawing explanation
Fig. 1 is the flow chart of the analysis method of PCB network poor flow of the present invention.
Detailed description of the invention
Below, in conjunction with accompanying drawing and detailed description of the invention, the present invention is described further:
The analysis method of a kind of PCB network poor flow as shown in Figure 1, comprises the following steps:
S1, inquiry PCB network line nexus, and carry out nexus segmentation formed segmented network;
S2, each segmented network is measured resistance respectively, if resistance value is more than 5M ��, then judge that this segmented network is as open circuit, if the Standard resistance range of resistance value is 10 ��-5M ��, then judges that this segmented network is crack;
S3, a. are for being judged as the in the case of of opening a way: the through hole of bad position or blind hole or circuit are carried out defect analysis; When being b. judged as crack for segmented network: corresponding segmented network being passed into DC current and is heated, then observe thermal self-restraint stress with thermal infrared imager, this thermal self-restraint stress is bad position, finally this bad position is carried out defect analysis.
By network line is carried out segmentation, then segmented network is measured respectively, substantially increase the efficiency measuring resistance, also improve accuracy simultaneously, and, by the judgement segmented network of resistance being belonged to open circuit or crack, carry out the defect analysis method that corresponding enforcement is different, in hgher efficiency. Wherein, for open circuit and crack situation, and for blind hole, through hole, circuit different defective locations, implement different analysis methods so that analyzing more specific aim, accuracy is also higher. Particularly, adopt thermal infrared imager to observe the mode of thermal self-restraint stress, quickly will can obtain the accurate location of bad position.
Exemplarily, for through hole or blind hole, just can obtain the actual defects of through hole or blind hole owing to needing to analyze its section, therefore, in this example, when being through hole or blind hole for bad position, use micro-Sectioning to see whether there is porous dehiscence.
Exemplarily, owing to the defect of circuit is difficult to be obtained by profile analysis, therefore, when this example is circuit for bad position, X-ray instrument is used to observe whether circuit exists crackle, crack. By X-ray instrument (X ray detector), the exception of circuit just can be checked.
Exemplarily, for being observed the bad position drawn by thermal infrared imager, if this bad position is circuit, then X-ray instrument is used to observe whether bad circuit exists breach, micro-crack, if this bad position is through hole or blind hole, then see whether there is micro-crack by slice analysis.
It will be apparent to those skilled in the art that can technical scheme as described above and design, make other various corresponding changes and deformation, and all these change and deformation all should belong within the protection domain of the claims in the present invention.
Claims (4)
1. the analysis method of a PCB network poor flow, it is characterised in that comprise the following steps:
S1, inquiry PCB network line nexus, and carry out nexus segmentation formed segmented network;
S2, each segmented network is measured resistance respectively, if resistance value is more than 5M ��, then judges that this segmented network is as open circuit, if resistance value resistance range for 10 ��-5M ��, then judge that this segmented network is crack;
S3, a. are for being judged as the in the case of of opening a way: the through hole of bad position or blind hole or circuit are carried out defect analysis; When being b. judged as crack for segmented network: corresponding segmented network being passed into DC current and is heated, then observe thermal self-restraint stress with thermal infrared imager, this thermal self-restraint stress is bad position, finally this bad position is carried out defect analysis.
2. the analysis method of PCB network poor flow according to claim 1, it is characterised in that when being through hole or blind hole for bad position, uses micro-Sectioning to see whether there is porous dehiscence.
3. the analysis method of PCB network poor flow according to claim 1, it is characterised in that when being circuit for bad position, uses X-ray instrument to observe whether circuit exists crackle, crack.
4. the analysis method of PCB network poor flow according to claim 1, it is characterized in that, for being observed the bad position drawn by thermal infrared imager, if this bad position is circuit, X-ray instrument is then used to observe whether bad circuit exists breach, micro-crack, if this bad position is through hole or blind hole, then see whether there is micro-crack by slice analysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610009240.7A CN105629124A (en) | 2016-01-01 | 2016-01-01 | PCB network poor conduction analysis method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610009240.7A CN105629124A (en) | 2016-01-01 | 2016-01-01 | PCB network poor conduction analysis method |
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| CN105629124A true CN105629124A (en) | 2016-06-01 |
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| CN201610009240.7A Pending CN105629124A (en) | 2016-01-01 | 2016-01-01 | PCB network poor conduction analysis method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108181572A (en) * | 2017-12-29 | 2018-06-19 | 大族激光科技产业集团股份有限公司 | Flying probe tester test method, device, computer equipment and storage medium |
| CN109188243A (en) * | 2018-08-30 | 2019-01-11 | 上海炜绫测试技术有限公司 | A kind of PCB interconnection method for testing reliability |
| CN110146804A (en) * | 2019-06-08 | 2019-08-20 | 四会富仕电子科技股份有限公司 | A kind of PCB dynamic conducting method for testing reliability |
| CN112731111A (en) * | 2020-12-30 | 2021-04-30 | 苏州谨测检测技术服务有限公司 | Novel PCBA device failure short circuit test method |
| CN113567828A (en) * | 2021-06-15 | 2021-10-29 | 中国电子科技集团公司第十三研究所 | Nondestructive failure detection method for multilayer low-temperature co-fired ceramic substrate |
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| CN108181572A (en) * | 2017-12-29 | 2018-06-19 | 大族激光科技产业集团股份有限公司 | Flying probe tester test method, device, computer equipment and storage medium |
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| CN113567828A (en) * | 2021-06-15 | 2021-10-29 | 中国电子科技集团公司第十三研究所 | Nondestructive failure detection method for multilayer low-temperature co-fired ceramic substrate |
| CN113567828B (en) * | 2021-06-15 | 2024-06-21 | 中国电子科技集团公司第十三研究所 | Nondestructive failure detection method for multilayer low-temperature co-fired ceramic substrate |
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