CN109166797A - TiN薄膜刻蚀方法 - Google Patents

TiN薄膜刻蚀方法 Download PDF

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Publication number
CN109166797A
CN109166797A CN201810757205.2A CN201810757205A CN109166797A CN 109166797 A CN109166797 A CN 109166797A CN 201810757205 A CN201810757205 A CN 201810757205A CN 109166797 A CN109166797 A CN 109166797A
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Prior art keywords
thin film
tialn thin
silicon wafer
etching
tialn
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刘善善
朱黎敏
朱兴旺
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Micromachines (AREA)

Abstract

本发明公开了一种TiN薄膜刻蚀方法，包括如下步骤：步骤1、对表面覆盖TiN薄膜的硅片进行NH3处理；步骤2、对经过NH3处理后的硅片涂胶加显影处理；步骤3、对硅片刻蚀成型。本发明既能有效的刻蚀掉TiN薄膜，又不影响下层薄膜的特性。

Description

TiN薄膜刻蚀方法
技术领域
本发明涉及半导体集成电路领域，特别是涉及一种TiN(氮化钛)薄膜刻蚀方法。
背景技术
TiN薄膜作为相对高电阻薄膜经常应用到MEMS(微机电系统)器件中作为电极，由于TiN薄膜本身特殊的结构，使得其在受到含氧离子轰击过程中，会有部分TiN中的N(氮)原子被替换，形成一种带氧的特殊薄膜覆盖在TiN表面，在后续的刻蚀工艺过程中，会严重阻碍TiN薄膜的刻蚀。
发明内容
本发明要解决的技术问题是提供一种TiN薄膜刻蚀方法，既能有效的刻蚀掉TiN薄膜，又不影响下层薄膜的特性。
为解决上述技术问题，本发明的TiN薄膜刻蚀方法是采用如下技术方案实现的：
步骤1、准备一表面覆盖TiN薄膜的硅片；
步骤2、对表面覆盖TiN薄膜的硅片进行NH3(氨气)处理；
步骤3、对经过NH3处理后的硅片涂胶加显影处理；
步骤4、对硅片刻蚀成型。
采用本发明的TiN薄膜的刻蚀工艺方法，可以有效的应用于TiN薄膜刻蚀，尤其是在单独TiN薄膜刻蚀工艺，既能有效的刻蚀掉TiN薄膜，又不影响下层薄膜的特性。
本发明的方法适用于MEMS电极的刻蚀，适用于MEMS产品。
附图说明
下面的结合附图与具体实施方式对本发明作进一步详细的说明：
图1是所述TiN薄膜刻蚀方法流程示意图。
具体实施方式
结合图1所示，所述TiN薄膜刻蚀方法在下面的实施例中，具体实施过程如下：
步骤1、准备一表面覆盖TiN薄膜的硅衬底，即表面覆盖TiN薄膜的硅片。TiN薄膜的厚度为10～30nm。TiN薄膜的成膜方法不限于物理沉积(PVD)以及化学气相沉积(CVD)等成膜方法中的一种及混合工艺方法。
步骤2、对表面覆盖TiN薄膜的硅片进行NH3处理。对表面覆盖TiN薄膜的硅片进行NH3处理的设备为CVD设备工艺腔或者PVD设备工艺腔，处理工艺温度为250～400℃，真空压力为3～10torr，NH3流量为30～100sccm，N2流量3～10k sccm，处理时间为10～30s。
步骤3、对经过NH3处理后的硅片涂胶加显影处理。
步骤4、对硅片刻蚀成型。对经过涂胶显影后的硅片进行刻蚀工艺处理的方法，包括但不限于干法刻蚀，湿法刻蚀，以及混合等刻蚀TiN薄膜的方法。
以上通过具体实施方式对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (4)

1.一种TiN薄膜刻蚀方法，其特征在于，包括如下步骤：
步骤1、准备一表面覆盖TiN薄膜的硅片；
步骤2、对表面覆盖TiN薄膜的硅片进行NH3处理；
步骤3、对经过NH3处理后的硅片涂胶加显影处理；
步骤4、对硅片刻蚀成型。
2.如权利要求1所述的方法，其特征在于：步骤1所述TiN薄膜的厚度为10～30nm。
3.如权利要求1所述的方法，其特征在于：实施步骤2时，对表面覆盖TiN薄膜的硅片进行NH3处理的设备为CVD设备工艺腔或者PVD设备工艺腔，处理工艺温度为250～400℃，真空压力为3～10torr，NH3流量为30～100sccm，N2流量3～10k sccm，处理时间为10～30s。
4.如权利要求1所述的方法，其特征在于：实施步骤4时，对经过涂胶显影后的硅片进行刻蚀的方法，包括干法刻蚀，湿法刻蚀，以及混合刻蚀。
CN201810757205.2A 2018-07-11 2018-07-11 TiN薄膜刻蚀方法 Pending CN109166797A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110459468A (zh) * 2019-08-29 2019-11-15 上海华力集成电路制造有限公司 TiN薄膜的刻蚀方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004218053A (ja) * 2003-01-17 2004-08-05 Tokyo Electron Ltd 薄膜の形成方法及び薄膜の形成装置
CN1641843A (zh) * 2004-01-14 2005-07-20 株式会社瑞萨科技 半导体器件及其制造方法
KR100596791B1 (ko) * 2004-07-21 2006-07-04 주식회사 하이닉스반도체 반도체 소자의 ＴｉＮ막 형성방법
CN103377910A (zh) * 2012-04-23 2013-10-30 中芯国际集成电路制造(上海)有限公司 半导体器件的刻蚀方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004218053A (ja) * 2003-01-17 2004-08-05 Tokyo Electron Ltd 薄膜の形成方法及び薄膜の形成装置
CN1641843A (zh) * 2004-01-14 2005-07-20 株式会社瑞萨科技 半导体器件及其制造方法
KR100596791B1 (ko) * 2004-07-21 2006-07-04 주식회사 하이닉스반도체 반도체 소자의 ＴｉＮ막 형성방법
CN103377910A (zh) * 2012-04-23 2013-10-30 中芯国际集成电路制造(上海)有限公司 半导体器件的刻蚀方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110459468A (zh) * 2019-08-29 2019-11-15 上海华力集成电路制造有限公司 TiN薄膜的刻蚀方法

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