CN109152526A - 具有8个通道的数字生物电势获取系统 - Google Patents

具有8个通道的数字生物电势获取系统 Download PDF

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CN109152526A
CN109152526A CN201780012702.3A CN201780012702A CN109152526A CN 109152526 A CN109152526 A CN 109152526A CN 201780012702 A CN201780012702 A CN 201780012702A CN 109152526 A CN109152526 A CN 109152526A
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马蒂亚斯·库尔
伊奥诺斯·马诺利
丹尼斯·普拉查
托马斯·斯蒂格利茨
奥斯卡·科塔
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Luo Lobp Co New York
Neuroloop GmbH
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    • HELECTRICITY
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Abstract

本发明涉及一种具有用于从生物的神经系统获取电子信息的许多输入通道的生物相容的记录系统,所述生物相容的记录系统包括前置放大器级和另外的放大器级,其中第二放大器级的输入耦合到所述前置放大器的输出;以及具有电容倍增器的低通滤波器,所述低通滤波器连接到所述第二级的所述放大器。所述记录系统的所述前置放大器使用P‑MOS技术设计。

Description

具有8个通道的数字生物电势获取系统
技术领域
本发明涉及用于记录生物的神经信号的生物相容的神经植入体。具体地,本发明公开用于植入生物中的芯片内神经信号的获取系统。
背景技术
生物电势是在活细胞、组织和有机组织中的点之间测量的电势并且结合所有生物化学过程发生。还描述信息在细胞之间和在细胞内的传递。电量(电压、电流或场强度)由带电荷离子的化学反应引起。此术语进一步在描述信息在细胞之间和细胞内的传递中(例如,在信号传输中)使用。
神经植入体可电刺激、捕获并且阻挡(或甚至同时捕获和刺激)来自生物中单个神经元或神经元群组(生物神经网络)的信号。
本发明公开集成CMOS生物电势获取芯片的设计和测试,所述集成CMOS生物电势获取芯片具有8个通道并且由低噪声放大器(LNA)、第二级、复用器和两个模数转换器(ADC)组成。
由于其可变的功率消耗,第一级的集成噪声可从1.94μVRMS减少至0.693μVRMS(Iss=250μA)。装置具有可变的下拐角频率和上拐角频率并且在1Mb/s下输出两个16位数字数据流。
芯片以X-Fab 0.35μm CMOS技术制造并且具有10mm2的面积。
神经植入体是支持疾病(诸如帕金森氏疾病、听觉损伤和心脏病)的治疗的装置。
这类装置通过电刺激连接神经系统以诱导身体反应。例如,耳蜗植入体刺激听神经来创建听觉的感知印象,起搏器刺激心脏的内壁来触发心脏肌肉收缩,并且深脑刺激器生成防止由帕金森氏疾病引起的不想要的肌肉颤搐的信号。
医学研究的目的在于理解神经植入体应如何影响神经系统。正常地,大型记录系统在对人和动物的实验中使用,使得可能可视化并且处理来自脑或神经的信号。当前实验显示明显倾向于使用可植入的获取系统,因为它们是更靠近于医学植入体的现实的一个步骤。
取决于应用的类型,生物电信号覆盖宽范围的幅值、噪声电平和频率带。出于这个原因,可使其性质适于相应的应用的记录系统是极其令人希望的。
Ghovanloo[6]展示了具有极其低的功率消耗的系统,所述系统可检测脑信号并且包括可变的带宽和无线电传输。Harrison等人展示了多功能获取放大器,所述多功能获取放大器在脑动作电势、脑电图(EEG)、心电图(ECG)和肌电图(EMG)的情况下已经得以证明其自身。
这些获取系统的优点是它们各自具有4μVRMs和2μVRMS的噪声电平,这在具有EEG和神经电图(ENG)的应用中相对较高。
放大器还生成噪声,所述噪声被分成热噪声和闪烁噪声。
热噪声密度相对于频率恒定并且与晶体管的等效电阻成正比例。
另一方面,闪烁噪声密度取决于具有1/f因子的频率并且与晶体管表面成反比例。
已经作出一些努力来克服噪声限制。显著的工作由用于ENG的BJT输入跨导运算放大器(OTA)表示,由R.Rieger和N.Donaldson提出。
由于BJT晶体管并不生成闪烁噪声,因而300nVRMS的所得的输入相关的噪声显著地低于先前的放大器的输入相关的噪声。然而,此架构具有两个严重的缺点:
1.它具有来自电极组织界面的20nA的剩余DC电流,这长期可在触点处导致腐蚀,以及
2.技术是“开环”,这致使增益是随机变量,这对于用于袖套电极记录的“真三向发声布置”是一个问题。
此外,斩波结构被提出使信号偏移至闪烁噪声可忽略不计的频率。信号然后在不具有闪烁噪声的情况下解调。遗憾的是,斩波放大器需要至少十倍多的带宽以确保信号足够远。
这种要求增加了放大器的功率消耗。本发明示出多功能的低噪声放大器以实现子μVRMS的输入噪声电平。应用到噪声减少的方法在于适当的晶体管大小和功率以及使用具有低闪烁噪声常数的PMOS输入晶体管。图1中示出的本系统在具有10位ADC的情况下具有8个双极性输入通道和两个独立的串行数字输出。
发明内容
LNA前置放大器
已知第一级(前置放大器)在放大器链中是最重要的级,因为它是最易受噪声影响的部件。出于这个原因,已经使用全差分伸缩架构。
图2中示出的架构提供单一级中高的增益和带宽,以及理论上无限共模抑制比(CMRR)和无限噪声抑制(PSRR)。
放大器通道的方程式是已知的,并且被改述用于gm/ID设计方法,所述噪音模型如下:
并且传递函数:
以及
图注:
Kn 闪光噪声常数NMOS 120×10-24V2F
Kp 闪光噪声常数PMOS 20×10-24V2F
k 玻尔兹曼常数 1,3806×10-23m2kg/s2K
(1)
V2 n,in 总输入噪声 VRMS
k 玻尔兹曼常数 1
T 温度 K
gm 跨导 A/V
ID 漏极端子处的电流电平 A
(2)
CIN 输入容量 F
CF 反馈容量 F
fcL 下拐角频率 Hz
fcU 上拐角频率 Hz
(3)
RF 反馈电阻 Ω
β MOSFET晶体管电流放大 A/V2
ISS 用于FD伸缩放大器的极化电流 A
使用图3中标记的PMOS晶体管和最佳点,下列表中显示的变量被确定:PMOS FD伸缩放大器的变量
第二级
图4中示出的第二级负责FD(全差分)到单端转换,其中6μVRMS量的输入噪音用于148μW的功率消耗(在LP模式中11μVRMS和46μW)。由于反馈,它递送0dB或20dB的增益。OTA由单端2级密勒放大器组成。
在电子器件的场中,由于电容在输入端子和输出端子之间的效应的放大,密勒效应是反相电压放大器的等效输入电容的增加。由于密勒效应明显地增加的输入容量产生如下结果:
CM=C(1+Av)
其中-Av是增益并且C是反馈电容。
尽管术语密勒效应通常是指电容,但是连接在输入接点和另一个接点之间的示出增益的任何阻抗可利用这一效应修改放大器输入阻抗。
具有电容倍增器的低通滤波器
由于不同的应用需要不同的上拐角频率fcu,因而变量RC低通滤波器已经被集成。
在参考文献[3]中,这一变量通过调整LNA偏置电流Iss,创建噪音行为的变量来实现。为了避免这一不想要的耦合,提出电容倍增器,所述电容倍增器使用来自[4]的控制电流OTA并且连接到第二级,如[5]中所描述。电容倍增因子(从50pF到5nF)由差分输入VGC±、56μA的偏置电流和0.013mm2的面积设置。
MUX,模数转换器和串行输出
芯片使用X-Fab 0.35μm库10位SAR-ADC并且集成用户定义的基于触发器的并串转换器。16位小字节序输出如[4]中组合,其中S表示起始令牌位(H L),位C3-C0表示通道数量并且位D9-D0表示ADC样本值。
功率消耗
芯片的功率消耗概括于下表:
结果
图8中示出的芯片使用X-Fab 0.35μm技术制造。放大器I/O引脚概括于表2中。系统引脚为参数提供灵活性:
·使能函数:连续的/SS变量、第二级低功率(LP)模式、电容倍增器、20dB增益
·偏置电压:VREF_ISS、VREF_CMFB
·频率范围变量:VGCP/N、VTUNE
尽管芯片被设计用于数字输出,但是它包含测试引脚来支持其特性,诸如前置放大器的模拟输出和具有通道1和5的低通滤波器。
表2,LNA8芯片的I/O引脚。已加下划线的引脚表示输出。
ADC可用高达1MHz的两个串行数字输出定时。
频率响应
LNA8记录系统在每种情况下通过改变电势V调谐和VGC±具有可变的拐角频率fcU、fcL。
噪声行为
放大器的噪声频谱密度被测量用于不同的偏置电流和带宽设置电压。
图13中的图形表示示出相比较于示意性的仿真和模拟提取的仿真的测量的曲线。图14示出用于不同放大器配置的总集成输入噪声。曲线示出针对Iss=250μA的*(仿真值)0.6VRMS的最小噪声。
活体内记录
获取系统已经被测试具有生物电活体内信号,如图15所示。生物电信号使用SPI解码从串行数字输出直接地提取。SPI总线(串行外围接口)是用于短程通信的同步串行通信接口规格。SPI装置可在全双工操作中使用主从架构与单一主机通信。主装置生成框架以用于读取和写入。大量的从装置通过选择单个从选择线(SS)来支持。
图15中的上部在上文示出示例性二头肌EMG检测的三个连续的收缩。图15中的下部示出ECG检测。
总结
本文示出具有8个通道的生物电势获取系统的实现。表3示出与类似页的比较。
尽管最好的噪声效率因子由使用BJT晶体管(BJT晶体管-->Mahdi参考!)的设计实现,但是这具有如下缺点:20nA的剩余DC电流保留,这从长远看来可导致电极腐蚀。
电容倍增器实现其提供宽范围的上截止频率的功能。
然而,由于电容倍增器的尺寸被设计成具有最小面积和功率消耗,因而噪声行为在不具有电容倍增器的情况下可能无法保持低于1μVRMS;噪声行为可通过软件滤波维持。
表3显示示出的低噪声放大器(LNA)与其他系统的比较
与[3]以前的作品相比较,本设计集成希望的系统的其他区块。
放大器面积已经减少了四倍并且由模拟输出减少。
结果
本发明示出具有8个通道的多功能生物电信号获取芯片的成功的实现方式和测试。放大的通道从两个模拟多路复用器选择并且由两个SPI相容的16位数据流输出。总集成输入噪声可针对介于1Hz和10kHz之间的带宽减少至*(仿真值)0.6μVRMS。获取系统已经被测试用于ECG和EMG应用。
参考文献
[1]B.Razavi,Design of analog CMOS integrated circuits:Tata McGraw-Hill Education,2002.
[2]P.Harpe,H.Gao,R.van Dommele,E.Cantatore,and A.van Roermund,“21.2A3nW signal-acquisition IC integrating an amplifier with 2.1NEF and a 1.5fJ/conv-step ADC,”in Solid-State Circuits Conference-(ISSCC),2015IEEEInternational,2015,S.1–3.
[3]O.F.Cota,D.Plachta,T.Stieglitz,Y.Manoli,and M.Kuhl,“In-vivocharacterization of a 0.8‐3\muV RMS input-noise versatile CMOS pre-amplifier,”in Neural Engineering(NER),2015 7th International IEEE/EMBSConference on,2015,S.458–461.
[4]J.S.R.Garimella,A.J.andR.G.Carvajal,“Gain programmable current mirrors based on current steering,”Electronics Letters,vol.42,no.10,S.559–560,2006.
[5]J.A.Ruiz,A.Lopez-Martin,and J.Ramirez-Angulo,“Three novel improvedCMOS capacitance scaling schemes,”in Circuits and Systems(ISCAS),Proceedingsof 2010IEEE International Symposium on,2010,S.1304–1307.
[6]M.Yin and M.Ghovanloo,“A low-noise clockless simultaneous 32-channel wireless neural recording system with adjustable resolution,”AnalogIntegrated Circuits and Signal Processing,vol.66,no.3,S.417–431,ISI:000287319400010,2011.
[7]J.Taylor and R.Rieger,“A low-noise front-end for multiplexed ENGrecording using CMOS technology,”Analog Integrated Circuits and SignalProcessing,vol.68,no.2,S.163–174,ISI:000292649900004,2011.
[8]F.Zhang,J.Holleman,and B.P.Otis,“Design of ultra-low powerbiopotential amplifiers for biosignal acquisition applications,”IeeeTransactions on Biomedical Circuits and Systems,vol.6,no.4,S.344–355,2012.。

Claims (6)

1.一种用于从生物的神经系统获取电子信息的生物相容的记录系统,其包括:
-前置放大器,
-第二放大器级,其中所述第二级的所述放大器的输入耦合到所述前置放大器的输出,
-具有电容倍增器的低通滤波器,所述低通滤波器连接到所述第二级的所述放大器。
2.如权利要求1所述的记录系统,其特征在于所述前置放大器在所述第一放大器级中使用P-MOS输入晶体管。
3.如权利要求1所述的记录系统,其特征在于所述记录系统可在至少两个记录通道的帮助下获取彼此独立的至少两个信号。
4.如权利要求1所述的记录系统,其中所述系统通过预定信号的变化具有可变的下拐角频率(fcL)和上拐角频率(fcU)。
5.如权利要求2所述的记录系统,其中所述前置放大器的所述第一放大器级由完全差分伸缩架构组成。
6.如权利要求1所述的记录系统,其中基于触发器的并串转换器被集成。
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