CN109150168B - All-digital phase-locked loop of pipeline circuit structure and phase-locked control method - Google Patents

Abstract

An all-digital phase-locked loop with a pipeline circuit structure and a phase-locked control method, wherein the all-digital phase-locked loop includes a digital phase detector module, a pipeline variable mode controller module, a pipeline digital filter module, a buckle pulse control circuit module and Pipeline divider block. Use electronic design automation technology to complete the design of each module circuit. By adopting pipeline technology to optimize the circuit structure of the phase-locked loop, the operating speed of the phase-locked system is improved, and the power consumption of the system is reduced. Speed, but also enhance the stability of the system. The all-digital phase-locked loop with pipeline circuit structure has the advantages of fast phase-locking speed, low power consumption, and high system stability, and can reduce the cost of practical application in system chip applications, and has huge market potential.

Description

All-Digital Phase-Locked Loop with Pipeline Circuit Structure and Phase-Locked Control Method

technical field

The invention relates to the technical field of electronic information, in particular to an all-digital phase-locked loop and a phase-locked control method applied to a pipeline circuit structure of an on-chip system.

Background technique

Phase-locked loops have been widely used in the fields of communication, radio electronics, automatic control and power system automation. With the rapid development of semiconductor technology and the emergence of system chips, phase-locked loops have become an important function in SoCs. module. The existing all-digital phase-locked loop has the defect of high power consumption due to unreasonable circuit structure. For chips used in system-on-chip applications in various fields, reducing power consumption, shortening response time, and increasing system operating speed will greatly improve system performance. Therefore, in order to reduce the overall power consumption of system-on-chip, especially reduce Such as the power consumption of mobile devices, it is necessary to reduce the power consumption of each functional module in the system chip.

In addition, the anti-interference performance of the all-digital phase-locked loop is closely related to the phase-locked speed, capture range and loop bandwidth, and they are contradictory. Therefore, a compromise method is usually used in the design to obtain better anti-interference performance and improve system stability. However, it is bound to have an adverse effect on the quality of the system when making a compromise. The limitation of the circuit structure of the existing all-digital phase-locked loop and the fixed system parameters make it impossible to realize the high performance and high stability of the chip-on-chip applied in the all-digital phase-locked loop at the same time.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a full-digital phase-locked loop and a phase-locked control method with a pipeline circuit structure, use pipeline technology to optimize the circuit structure of the phase-locked loop, and improve the operation of the phase-locked system speed and reduce system power consumption. At the same time, the dynamic control of the working process of the all-digital phase-locked loop is realized by dynamically adjusting the parameters of the pipeline digital filter, which not only improves the phase-locking speed, but also enhances the stability of the system.

The technical solution of the present invention is: an all-digital phase-locked loop with a pipeline circuit structure, including a digital phase detector module, a pipeline variable mode controller module, a pipeline digital filter module, a buckle pulse control circuit module and a pipeline frequency divider Modules, using electronic design automation technology to complete the design of each module circuit.

The digital phase detector module is realized by double D flip-flops. The digital phase detector module has two signal input terminals and three signal output terminals. The two signal input terminals are respectively the fin signal input terminal and the fout signal input terminal. The signal output terminals are ua signal output terminal, ah signal output terminal and be signal output terminal respectively. The digital phase detector module judges the phase error and polarity by detecting the rising edge of the input signal fin and the output signal fout of the full digital phase locked loop. , and generate a phase error signal ua that reflects the input and output signals, and a polarity signal, that is, the leading signal ah and the lagging signal be.

The pipeline variable mode controller module includes a time-to-digital conversion module TDC and a variable mode controller. The pipeline variable mode controller module provides adjustable dynamic parameters for the pipeline digital filter, receives the phase error signal ua output by the digital phase detector module, and According to the size of the phase error signal ua, the modulus km output by the pipeline variable mode controller module is adjusted. The specific adjustment method is: when the phase error is large, a smaller modulus km is output in order to speed up the phase locking speed; When the phase error is small, a larger modulus km is output to reduce the phase jitter after the loop is locked.

The time-to-digital conversion module TDC includes a 20-bit counter, and the 20-bit counter adopts a five-stage pipeline design. Each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value. The first stage of the counter The digits of the counter are 0-3 digits, the digits of the second-stage counter are 4-7 digits, the digits of the third-stage counter are 8-11 digits, the digits of the fourth-stage counter are 12-15 digits, and the fifth-stage counters are 12-15 digits. The number of counters is 16-19 bits, and the design of the time-to-digital conversion module TDC is completed by using the ultra-high-speed integrated circuit hardware description language, and then connected with the variable-mode controller to obtain the pipeline automatic variable-mode controller module; according to the digital phase detector module The output phase error signal ua provides the output signal km with variable modulus value for the reversible counter in the pipeline digital filter module.

The pipeline digital filter module consists of an 8-bit reversible counter, which adopts a two-stage pipeline design, and each stage of counter M includes a register J, an adder and a latch S for temporarily storing the count value. Among them, the number of digits of the first stage counter is 0-3 digits, the number of digits of the second stage counter is 4-7 digits, and the modulus value of the reversible counter is automatically generated by the pipeline variable modulus controller module according to the preset control algorithm; The pipeline digital filter module receives the leading signal ah and the lagging signal be obtained from the digital phase detector module according to the comparison between the input signal fin and the output feedback signal fout, and counts up or down according to the leading signal ah or the lagging signal be, when the count value When the received modulus value of the counter is reached, a carry signal inc or a borrow signal dec is generated, and sent to the plus and minus pulse control circuit module respectively.

The plus and minus pulse control circuit module receives the carry signal inc or the borrow signal dec sent by the pipeline digital filter module, performs pulse plus and minus processing on the output digital sequence signal, and sends the processed digital sequence signal to the pipeline for frequency division device module; the specific implementation method is: when the carry signal inc at the input terminal of the buckling pulse control circuit module is high level, a pulse is inserted in the digital sequence signal output by it; When the bit signal dec is at a high level, a pulse is subtracted from the output digital sequence signal, and the digital sequence signal processed by adding the pulse is sent to the pipeline frequency divider module for further adjustment.

The pipeline frequency divider module is composed of a 24-bit counter, and its frequency division factor N is adjustable; the 24-bit counter adopts a three-stage pipeline design, and each stage of the counter M includes a register J, an adder and a lock for temporarily storing the count value Register S; each level is an 8-bit counter, in which the number of bits of the first level counter is 0-7 bits, the number of bits of the second level counter is 8-15 bits, and the number of bits of the third level counter is 16-23 bit; whenever the 8-bit counter of the lower level generates a carry signal, the 8-bit counter of the higher level is triggered to start counting, so as to perform cumulative counting; the frequency division coefficient N is set from the external input port, that is, according to the phase-locked loop Depending on the frequency of the input signal, the specific parameters of the frequency division coefficient can be flexibly set; the setting of this parameter is selected according to the ratio of the system clock signal frequency to the system input signal frequency satisfying 2 ^N.

The output terminal of the phase error signal ua of the digital phase detector module is connected with the input terminal of the pipeline variable mode controller module, and the output terminals of the leading signal ah and the lag signal be are respectively connected with the first signal input terminal and the second signal terminal of the pipeline digital filter module. The signal input terminals are connected, the modulus signal km output terminal of the pipeline variable mode controller module is connected with the third input signal input terminal of the pipeline digital filter module, the carry signal inc output terminal of the pipeline digital filter module and the borrow signal The dec output ends are respectively connected with the two signal input ends of the buckle pulse control circuit module, the signal output end of the buckle pulse control circuit module is connected with the first signal input end of the pipeline frequency divider module, according to the clock signal frequency and The frequency division factor N set by the external input port of the system input signal frequency is connected with the second input terminal of the pipeline frequency divider module, and the output signal fout of the pipeline frequency divider module is a phase-locked loop output signal, and it is fed back to The digital phase detector module serves as one of the inputs of the digital phase detector module.

According to the system structure diagram of the full digital phase-locked loop of the assembly line circuit structure, the present invention adopts a top-down design method, based on electronic design automation technology, uses VHDL language to program each module, and completes the full digital phase locking of the assembly line circuit structure Ring top circuit design.

In the top-level circuit of the all-digital phase-locked loop of the pipeline circuit structure, the system clock signal clk is connected to the input terminal clk of the pipeline variable mode controller module, the pipeline digital filter module and the buckle pulse control circuit module respectively.

The system reset signal reset is respectively connected to the input terminal reset of the pipeline variable mode controller module, the pipeline digital filter module, the buckling pulse control circuit module and the pipeline frequency divider module.

The enable signal en is connected to the input terminal en of the pipeline digital filter module.

The system input signal fin is connected to the input terminal fin of the digital phase detector module.

There are three output signals of the digital phase detector module, namely ah, be and ua, where ah and be are respectively connected to the input terminals ah and be of the pipeline digital filter module, and ua is connected to the input terminal of the pipeline variable mode controller module Ua is connected.

The output terminal km of the pipeline variable mode controller module is connected with the input terminal km of the pipeline digital filter module.

The two output terminals of the pipeline digital filter module, the output terminal of the carry signal inc and the output terminal of the borrow signal dec, are respectively connected to the input terminals inc and dec of the buckling pulse control circuit module.

The output terminal idout of the buckling pulse control circuit module is connected with the input terminal idout of the pipeline frequency divider module.

Calculate the ratio relationship between the clock signal frequency of the system and the system input signal frequency, set the frequency division coefficient N, and use it as the input terminal of the frequency division coefficient N of the pipeline frequency divider module, and the output terminal fout of the pipeline frequency divider module is the output of the system The signal terminal is also fed back to the input port of the system as the input terminal of the digital phase detector module.

The specific phase-locked control process of the all-digital phase-locked loop of pipeline circuit structure provided by the present invention is as follows:

The digital phase detector module outputs the corresponding phase leading signal ah or lagging signal be and phase error signal ua by detecting the rising edge of the phase locked loop input signal fin and output signal fout.

The pipeline variable mode controller module digitizes and compares the phase error signal. When the phase error is large, the modulus km sent to the pipeline digital filter module is reduced; when the phase error is small, the digital value sent to the pipeline is increased. The modulus km of the filter block.

At the same time, judge the level of the phase lead signal ah and the phase lag signal be output by the digital phase detector module. When the phase lead signal ah output by the digital phase detector module is at a high level, the pipeline variable mode controller module performs counting up. When the counting value After reaching the modulus km of the pipeline variable mode controller module, the pipeline digital filter module outputs the carry signal inc; when the phase lag signal be output by the digital phase detector module is at a high level, the pipeline variable mode controller module counts down. After the count value reaches the modulus km, the pipeline digital filter module outputs the borrow signal dec.

The buckling pulse control circuit module adjusts the phase of the output signal idout of the buckling pulse control circuit module by adding or subtracting a system clock cycle time according to the carry signal inc and the borrow signal dec output by the pipeline digital filter module.

The pipeline frequency divider module outputs the output signal fout of the pipeline frequency divider module according to the digital signal sequence output by the buckle pulse control circuit module and the frequency division coefficient N determined according to the ratio of the system clock signal frequency to the system input signal frequency. into the digital phase detector module, together with the input signal fin of the next period as the input of the digital phase detector module, to generate the corresponding phase leading signal ah or lagging signal be and phase error signal ua, and control accordingly to gradually reduce the phase error, and finally realize the locking of the phase-locked loop.

In the full digital phase-locked loop with pipeline circuit structure, the circuit structure of pipeline variable mode controller module, pipeline digital filter module and pipeline frequency divider module is designed through multi-stage pipeline technology, which reduces the system delay and improves the system performance. operating speed, and reduces the overall power consumption of the system.

The modulus value of the reversible counter in the pipeline variable mode controller module changes with the phase error, which can speed up its locking speed, and in the phase locking interval, it will automatically select the maximum modulus value set by the system, thereby greatly reducing the loop The jitter of the phase of the output signal of the road improves the stability of the system; by setting the frequency division coefficient N of the pipeline frequency divider module from the external input port, it is satisfied that the ratio of the system clock signal frequency to the system input signal frequency satisfies 2 ^N. selection, so that when the frequency of the system input signal jumps, the phase-locked loop can quickly adjust the phase error, and automatically select the maximum modulus after locking, that is, dynamically adjust the system parameters according to its different working processes. Thereby solving the contradiction between improving the locking speed and stability, and improving the overall performance of the system.

Compared with the prior art, the present invention has the following characteristics:

The all-digital phase-locked loop of the multi-stage assembly line circuit structure proposed by the present invention adopts electronic design automation technology to complete the system design, and its performance characteristics are:

1. The pipeline variable mode controller module, pipeline digital filter module, and pipeline frequency divider module are set through pipeline technology, and the circuit structure of the phase-locked loop is optimized, which improves the operating speed of the phase-locked system and reduces the system power. consumption.

2. Through the dynamic adjustment of the pipeline digital filter parameters, the dynamic control of the phase-locked loop working process is realized, which can not only improve the phase-locking speed, but also enhance the stability of the system.

3. The phase-locked loop has the advantages of fast phase-locking speed, low power consumption, and high system stability. When it is applied to a system chip, it can reduce the cost of practical application and has huge market potential.

The detailed structure of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Description of drawings

Accompanying drawing 1 is the system structural block diagram of the all-digital phase-locked loop of pipeline circuit structure;

Accompanying drawing 2 is the counter circuit structural diagram that adopts multistage pipeline technology;

Accompanying drawing 3 is the circuit structural diagram of pipeline variable mode controller module;

Accompanying drawing 4 is the top-level circuit diagram of the all-digital phase-locked loop of pipeline circuit structure;

Accompanying drawing 5 is the waveform simulation diagram when fin=50MHz;

Accompanying drawing 6 is the simulation diagram of the waveform when fin=50MHz jumps to fin=25MHz.

Detailed ways

An all-digital phase-locked loop with a pipeline circuit structure, including a digital phase detector module 1, a pipeline variable mode controller module 5, a pipeline digital filter module 2, a buckling pulse control circuit module 3 and a pipeline frequency divider module 4. Use electronic design automation technology to complete the design of each module circuit.

The digital phase detector module 1 is realized by double D flip-flops. The digital phase detector module has two signal input terminals and three signal output terminals. The two signal input terminals are respectively the fin signal input terminal and the fout signal input terminal. The two signal output terminals are the ua signal output terminal, the ah signal output terminal and the be signal output terminal respectively. The digital phase detector module 1 judges the phase error and Polarity, and generate a phase error signal ua that reflects the input and output signals, and a polarity signal, that is, the leading signal ah and the lagging signal be.

The pipeline variable mode controller module 5 includes a time-to-digital conversion module TDC5-1 and a variable mode controller 5-2, the pipeline variable mode controller module 5 provides adjustable dynamic parameters for the pipeline digital filter 2, and receives the digital phase detector module 1 output phase error signal ua, and adjust the modulus km output by the pipeline variable mode controller module 5 according to the size of the phase error signal ua, the specific adjustment method is: when the phase error is large, output a smaller modulus The value km is used to speed up the phase locking speed; when the phase error is small, a larger modulus value km is output to reduce the phase jitter after the loop is locked.

The time-to-digital conversion module TDC5-1 includes a 20-bit counter, and the 20-bit counter adopts a five-stage pipeline design, and each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value. Among them, the digits of the first stage counter are 0-3 digits, the digits of the second stage counter are 4-7 digits, the digits of the third stage counter are 8-11 digits, and the digits of the fourth stage counter are 12-15 digits. Bit, the number of digits of the fifth-stage counter is 16-19, as shown in Figure 2, where I is the input signal of the counter, and O is the output signal of the counter. The design of the time-to-digital conversion module TDC5-1 is completed by using the ultra-high-speed integrated circuit hardware description language, and then connected with the variable-mode controller 5-2 to obtain the pipeline automatic variable-mode controller module 5. According to the phase error signal ua output by the digital phase detector module 1, the reversible counter in the pipeline digital filter module 2 is provided with an output signal km of variable modulus.

The pipeline digital filter module 2 is composed of an 8-bit reversible counter. The reversible counter adopts a two-stage pipeline design. Each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value. Wherein the number of digits of the first stage counter is 0-3 digits, the number of digits of the second stage counter is 4-7 digits, and the modulus value of the reversible counter is automatically generated by the pipeline variable modulus controller module 5 according to the preset control algorithm. The pipeline digital filter module 2 receives the leading signal ah and the lagging signal be obtained from the digital phase detector module 1 according to the comparison between the input signal fin and the output feedback signal fout, and counts up or down according to the leading signal ah or the lagging signal be, When the count value reaches the modulus value of the received counter, a carry signal inc or a borrow signal dec is generated, and sent to the add pulse control circuit module 3 respectively.

Addition pulse control circuit module 3 receives the carry signal inc or borrow signal dec sent by the pipeline digital filter module 2, performs pulse addition processing on the digital sequence signal output by it, and sends the processed digital sequence signal to the pipeline Divider module 4. The specific implementation method is: when the carry signal inc of the input terminal of the buckle pulse control circuit module 3 is high level, a pulse is inserted in the digital sequence signal output by it; When the signal dec is at a high level, a pulse is subtracted from the output digital sequence signal, and the digital sequence signal processed by adding the pulse is sent to the pipeline frequency divider module 4 for further adjustment.

The pipeline frequency divider module 4 is composed of a 24-bit counter, and its frequency division factor N is adjustable. The 24-bit counter adopts a three-stage pipeline design, and each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value. Each level is an 8-bit counter, wherein the number of bits of the first level counter is 0-7 bits, the number of bits of the second level counter is 8-15 bits, and the number of bits of the third level counter is 16-23 bits. Whenever the low-level 8-bit counter generates a carry signal, the high-level 8-bit counter is triggered to start counting, so as to perform cumulative counting; the frequency division coefficient N is set from the external input port, that is, according to the phase-locked loop input signal Depending on the frequency, the specific parameters of the frequency division coefficient can be flexibly set. The setting of this parameter is selected according to the ratio of the system clock signal frequency to the system input signal frequency satisfying 2 ^N.

The output terminal of the phase error signal ua of the digital phase detector module 1 is connected to the input terminal of the pipeline variable mode controller module 5, and the output terminals of the leading signal ah and the lagging signal be are respectively connected to the first signal input terminal of the pipeline digital filter module 2 and the second signal input terminal are connected, the modulus signal km output terminal of the pipeline variable mode controller module 5 is connected with the third input signal input terminal of the pipeline digital filter module 2, and the carry signal inc of the pipeline digital filter module 2 The output end and the borrow signal dec output end are respectively connected with the two signal input ends of the buckle pulse control circuit module 3, and the signal output end of the buckle pulse control circuit module 3 is connected with the first signal input of the pipeline frequency divider module 4 The ends are connected, and the frequency division coefficient N set according to the external input port determined by the clock signal frequency and the system input signal frequency is connected with the second input end of the pipeline frequency divider module 4, and the output signal fout of the pipeline frequency divider module 4 is The phase locked loop outputs a signal and feeds it back to the digital phase detector module 1 as one of the inputs of the digital phase detector module 1 .

According to the system structure diagram of the full digital phase-locked loop of the assembly line circuit structure, the present invention adopts a top-down design method, based on electronic design automation technology, uses VHDL language to program each module, and completes the full digital phase locking of the assembly line circuit structure Ring top circuit design.

In the top-level circuit of the all-digital phase-locked loop of the pipeline circuit structure, the system clock signal clk is connected to the input terminal clk of the pipeline variable mode controller module 5, the pipeline digital filter module 2 and the buckling pulse control circuit module 3 respectively.

The system reset signal reset is respectively connected to the input end reset of the pipeline variable mode controller module 5 , the pipeline digital filter module 2 , the buckling pulse control circuit module 3 and the pipeline frequency divider module 4 .

The enable signal en is connected to the input end en of the pipeline digital filter module 2 .

The system input signal fin is connected to the input terminal fin of the digital phase detector module 1 .

There are three output signals of the digital phase detector module, namely ah, be and ua, wherein ah and be are respectively connected to the input terminals ah and be of the pipeline digital filter module 2, and ua is connected to the pipeline digital filter module 5's The input terminal ua is connected.

The output terminal km of the pipeline variable mode controller module 5 is connected to the input terminal km of the pipeline digital filter module 2 .

The two output terminals of the pipeline digital filter module 2, the output terminal of the carry signal inc and the output terminal of the borrow signal dec, are respectively connected to the input terminals inc and dec of the buckling pulse control circuit module 3 .

The output terminal idout of the buckling pulse control circuit module 3 is connected to the input terminal idout of the pipeline frequency divider module 4 .

Calculate the ratio relationship between the clock signal frequency of the system and the system input signal frequency, set the frequency division coefficient N, and use it as the input terminal of the frequency division coefficient N of the pipeline frequency divider module 4, and the output terminal fout of the pipeline frequency divider module 4 is the system The output signal end of the system is fed back to the input port of the system as the input end of the digital phase detector module 1 at the same time.

The specific phase-locked control process of the all-digital phase-locked loop of pipeline circuit structure provided by the present invention is as follows:

The digital phase detector module 1 outputs the corresponding phase leading signal ah or lagging signal be and phase error signal ua by detecting the rising edge of the phase locked loop input signal fin and output signal fout.

The pipeline variable modulus controller module 5 digitizes and compares the phase error signal, and when the phase error is large, reduces the modulus km sent to the pipeline digital filter module 2; when the phase error is small, increases the input The modulus km of the pipeline digital filter block 2.

Simultaneously, judge the level of the phase lead signal ah and the phase lag signal be that the digital phase detector module 1 outputs, when the phase lead signal ah of its output is high level, the pipeline modulus controller module 5 carries out counting up, when adding After the count value reaches the modulus value km of the pipeline variable mode controller module 5, the pipeline digital filter module 2 outputs the carry signal inc; when the phase lag signal be output by the digital phase detector module 1 is at a high level, the pipeline variable mode controller module 5 Perform down-counting, and when the down-counting value reaches the modulus km, the pipeline digital filtering module 2 outputs a borrow signal dec.

The buckle pulse control circuit module 3 adjusts the output signal idout of the buckle pulse control circuit module 3 by adding or subtracting the time of one system clock cycle according to the carry signal inc and the borrow signal dec output by the pipeline digital filter module 2 phase.

The pipeline frequency divider module 4 outputs the output signal of the pipeline frequency divider module 4 according to the digital signal sequence output by the buckle pulse control circuit module, and the frequency division coefficient N determined according to the ratio of the clock signal frequency of the system to the system input signal frequency fout is sent to the digital phase detector module 1, and together with the input signal fin of the next period as the input of the digital phase detector module 1, the corresponding phase leading signal ah or lagging signal be and phase error signal ua are generated, and the control is carried out accordingly. Gradually reduce the phase error, and finally achieve the locking of the phase-locked loop.

Carry out system simulation on the full digital phase-locked loop circuit with pipeline circuit structure, the simulation results are shown in Figure 5-6, where Figure 5 is the simulation waveform diagram when the frequency is 50MHz, and Figure 6 is the input signal frequency jump from 50MHz to 25MHz simulation waveform diagram, in the figure en is the system enable signal, reset is the system reset signal, clk is the system clock signal, fin is the system input signal, and fout is the system output signal.

From the simulation of the phase-locked loop, it can be seen from Figure 5 that in the phase adjustment interval, the modulus km of the reversible counter in the phase-locked loop varies with the phase error, which can speed up its locking speed; in the phase lock interval, It will automatically select the maximum modulus km set by the system, so it can greatly reduce the jitter of the loop output signal phase and improve the stability of the system.

It can be seen from Figure 6 that when the input frequency jumps, the phase-locked loop can quickly lock the frequency of the signal in the first period after the frequency jump of the input signal, and quickly adjust the phase error. After about 2.5 It can be locked within μs, and the maximum km value is also automatically selected after locking. The phase-locked loop can dynamically adjust system parameters according to its different working processes, fundamentally solves the contradiction between improving the locking speed and stability, and improves the overall performance of the phase-locked system.

When the clock signal frequency of the system is 200MHZ, and the input signal frequency of the system is 50MHZ, the system simulation is carried out on the traditional phase-locked loop and the pipeline phase-locked loop respectively, and the timing analysis and power consumption analysis are carried out on the simulation results. The specific result analysis is shown in Table 1:

Table 1 clk=200 MHZ, fin=50 MHZ result comparison

Delay/(ns) Power consumption/(μW) Traditional ADPLL 3.424 117390 Pipelined ADPLL 2.146 116760

It can be seen from Table 1 that, first of all, compared with the traditional PLL, the system delay of the PLL with pipeline circuit structure is reduced by 1.278ns. Secondly, when the clock frequency is 200MHZ, the total power consumption of the system is reduced by 630μW compared with the traditional PLL. It can be seen that the all-digital phase-locked loop with pipeline circuit structure can reduce the system delay, improve the working speed of the system, and reduce the total power consumption of the system.

Claims (1)

1. the phase-locked control method of the all-digital phase-locked loop of pipeline circuit structure, it is characterized in that: The all-digital phase-locked loop of the pipeline circuit structure includes a digital phase detector module, a pipeline variable mode controller module, a pipeline digital filter module, a buckling pulse control circuit module and a pipeline frequency divider module, and is completed by electronic design automation technology Design of each module circuit; The digital phase detector module is realized by double D flip-flops. The digital phase detector module has two signal input terminals and three signal output terminals. The two signal input terminals are respectively the fin signal input terminal and the fout signal input terminal. The signal output terminals are ua signal output terminal, ah signal output terminal and be signal output terminal respectively. The digital phase detector module judges the phase error and polarity by detecting the rising edge of the input signal fin and the output signal fout of the full digital phase locked loop. , and generate a signal ua reflecting the phase error between the input and output signals, and a polarity signal, that is, the leading signal ah and the lagging signal be; The pipeline variable mode controller module includes a time-to-digital conversion module TDC and a variable mode controller. The pipeline variable mode controller module provides adjustable dynamic parameters for the pipeline digital filter, receives the phase error signal ua output by the digital phase detector module, and According to the size of the phase error signal ua, the modulus km output by the pipeline variable mode controller module is adjusted. The specific adjustment method is: when the phase error is large, a smaller modulus km is output in order to speed up the phase locking speed; When the phase error is small, a larger modulus km is output to reduce the phase jitter after the loop is locked; The time-to-digital conversion module TDC includes a 20-bit counter, and the 20-bit counter adopts a five-stage pipeline design. Each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value. The first stage of the counter The digits of the counter are 0-3 digits, the digits of the second-stage counter are 4-7 digits, the digits of the third-stage counter are 8-11 digits, the digits of the fourth-stage counter are 12-15 digits, and the fifth-stage counters are 12-15 digits. The number of counters is 16-19 bits, and the design of the time-to-digital conversion module TDC is completed by using the ultra-high-speed integrated circuit hardware description language, and then connected with the variable-mode controller to obtain the pipeline automatic variable-mode controller module; according to the digital phase detector module The output phase error signal ua provides the output signal km of variable modulus for the reversible counter in the pipeline digital filter module; The pipeline digital filter module is composed of an 8-bit reversible counter. The reversible counter adopts a two-stage pipeline design. Each stage of the counter M includes a register J, an adder and a latch S for temporarily storing the count value; the first stage The number of digits of the counter is 0-3 digits, the number of digits of the second stage counter is 4-7 digits, the modulus value of the reversible counter is automatically generated by the pipeline variable mode controller module according to the preset control algorithm; the pipeline digital filter The module receives the leading signal ah and the lagging signal be obtained from the digital phase detector module according to the comparison between the input signal fin and the output feedback signal fout, and counts up or down according to the leading signal ah or the lagging signal be. When the count value reaches the received When the modulus value of the counter is generated, a carry signal inc or a borrow signal dec is generated and sent to the plus and minus pulse control circuit module respectively; The plus and minus pulse control circuit module receives the carry signal inc or the borrow signal dec sent by the pipeline digital filter module, performs pulse plus and minus processing on the output digital sequence signal, and sends the processed digital sequence signal to the pipeline for frequency division device module; the specific implementation method is: when the carry signal inc at the input terminal of the buckling pulse control circuit module is high level, a pulse is inserted in the digital sequence signal output by it; When the bit signal dec is at a high level, a pulse is subtracted from the output digital sequence signal, and the digital sequence signal processed by adding the pulse is sent to the pipeline frequency divider module for further adjustment; The pipeline frequency divider module is composed of a 24-bit counter, and its frequency division factor N is adjustable; the 24-bit counter adopts a three-stage pipeline design, and each stage of the counter M includes a register J, an adder and a lock for temporarily storing the count value Register S; each level is an 8-bit counter, in which the number of bits of the first level counter is 0-7 bits, the number of bits of the second level counter is 8-15 bits, and the number of bits of the third level counter is 16-23 bit; whenever the 8-bit counter of the lower level generates a carry signal, the 8-bit counter of the higher level is triggered to start counting, so as to perform cumulative counting; the frequency division coefficient N is set from the external input port, that is, according to the phase-locked loop The frequency of the input signal is different, and the specific parameters of the frequency division coefficient can be flexibly set; the setting of this parameter is selected according to the ratio of the system clock signal frequency to the system input signal frequency satisfying 2 ^N ; The output terminal of the phase error signal ua of the digital phase detector module is connected with the input terminal of the pipeline variable mode controller module, and the output terminals of the leading signal ah and the lag signal be are respectively connected with the first signal input terminal and the second signal terminal of the pipeline digital filter module. The signal input terminals are connected, the modulus signal km output terminal of the pipeline variable mode controller module is connected with the third input signal input terminal of the pipeline digital filter module, the carry signal inc output terminal of the pipeline digital filter module and the borrow signal The dec output ends are respectively connected with the two signal input ends of the buckle pulse control circuit module, the signal output end of the buckle pulse control circuit module is connected with the first signal input end of the pipeline frequency divider module, according to the clock signal frequency and The frequency division factor N set by the external input port of the system input signal frequency is connected with the second input terminal of the pipeline frequency divider module, and the output signal fout of the pipeline frequency divider module is a phase-locked loop output signal, and it is fed back to The digital phase detector module is used as one of the inputs of the digital phase detector module; The full digital phase-locked loop of the pipeline circuit structure adopts a top-down design method, based on electronic design automation technology, uses VHDL language to program each module, and completes the top-level circuit design of the full digital phase-locked loop of the pipeline circuit structure; In the top-level circuit of the all-digital phase-locked loop of the pipeline circuit structure, the system clock signal clk is connected to the input terminal clk of the pipeline variable mode controller module, the pipeline digital filter module and the buckle pulse control circuit module respectively; The system reset signal reset is respectively connected with the input terminal reset of the pipeline variable mode controller module, the pipeline digital filter module, the buckle pulse control circuit module and the pipeline frequency divider module; The enable signal en is connected to the input terminal en of the pipeline digital filter module; The system input signal fin is connected to the input terminal fin of the digital phase detector module; There are three output signals of the digital phase detector module, namely ah, be and ua, where ah and be are respectively connected to the input terminals ah and be of the pipeline digital filter module, and ua is connected to the input terminal of the pipeline variable mode controller module ua connected; The output terminal km of the pipeline variable mode controller module is connected with the input terminal km of the pipeline digital filter module; The two output terminals of the pipeline digital filter module, the carry signal inc output terminal and the borrow signal dec, are respectively connected to the input terminals inc and dec of the buckle pulse control circuit module; The output terminal idout of the buckle pulse control circuit module is connected with the input terminal idout of the pipeline frequency divider module; Calculate the ratio relationship between the clock signal frequency of the system and the system input signal frequency, set the frequency division coefficient N, and use it as the input terminal of the frequency division coefficient N of the pipeline frequency divider module, and the output terminal fout of the pipeline frequency divider module is the output of the system The signal terminal is also fed back to the input port of the system as the input terminal of the digital phase detector module; The digital phase detector module outputs the corresponding phase leading signal ah or lagging signal be and phase error signal ua by detecting the rising edge of the phase locked loop input signal fin and output signal fout; The pipeline variable mode controller module digitizes and compares the phase error signal. When the phase error is large, the modulus km sent to the pipeline digital filter module is reduced; when the phase error is small, the digital value sent to the pipeline is increased. The modulus km of the filter module; At the same time, judge the level of the phase lead signal ah and the phase lag signal be output by the digital phase detector module. When the phase lead signal ah output by the digital phase detector module is at a high level, the pipeline variable mode controller module performs counting up. When the counting value After reaching the modulus km of the pipeline variable mode controller module, the pipeline digital filter module outputs the carry signal inc; when the phase lag signal be output by the digital phase detector module is at a high level, the pipeline variable mode controller module counts down. After the count value reaches the modulus km, the pipeline digital filter module outputs the borrow signal dec; The buckle pulse control circuit module adjusts the phase of the output signal idout of the buckle pulse control circuit module by adding or subtracting the time of one system clock cycle according to the carry signal inc and the borrow signal dec output by the pipeline digital filter module; The pipeline frequency divider module outputs the output signal fout of the pipeline frequency divider module according to the digital signal sequence output by the buckle pulse control circuit module and the frequency division coefficient N determined according to the ratio of the system clock signal frequency to the system input signal frequency. into the digital phase detector module, together with the input signal fin of the next period as the input of the digital phase detector module, to generate the corresponding phase leading signal ah or lagging signal be and phase error signal ua, and control accordingly to gradually reduce the phase error, and finally realize the locking of the phase-locked loop.