CN109150168B - All-digital phase-locked loop of pipeline circuit structure and phase-locked control method - Google Patents

All-digital phase-locked loop of pipeline circuit structure and phase-locked control method Download PDF

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CN109150168B
CN109150168B CN201811181639.9A CN201811181639A CN109150168B CN 109150168 B CN109150168 B CN 109150168B CN 201811181639 A CN201811181639 A CN 201811181639A CN 109150168 B CN109150168 B CN 109150168B
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module
signal
pipeline
phase
digital
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CN109150168A (en
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单长虹
田帆
王丽君
赵宇红
邓贤君
杨檬玮
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University of South China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • G06F15/7878—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS for pipeline reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The all-digital phase-locked loop comprises a digital phase discriminator module, a pipeline variable-mode controller module, a pipeline digital filter module, a buckling pulse control circuit module and a pipeline frequency divider module. And the design of each module circuit is completed by utilizing an electronic design automation technology. The circuit structure of the phase-locked loop is optimized by adopting the assembly line technology, so that the running speed of the phase-locked loop is improved, the system power consumption is reduced, the dynamic control on the working process of the phase-locked loop is realized by dynamically adjusting the system parameters, the phase-locked speed can be improved, and the stability of the system can be enhanced. The all-digital phase-locked loop of the pipeline circuit structure has the advantages of high phase locking speed, low power consumption, high system stability and the like, can reduce the cost of practical application in the application of a system chip, and has huge market potential.

Description

All-digital phase-locked loop of pipeline circuit structure and phase-locked control method
Technical Field
The invention relates to the technical field of electronic information, in particular to an all-digital phase-locked loop and a phase-locked control method applied to a pipeline circuit structure of a system on a chip.
Background
Phase-locked loops are widely applied in the fields of communication, radio electronics, automatic control, power system automation and the like, and with the rapid development of semiconductor technology and the appearance of system chips, the phase-locked loops become an important functional module in a system on a chip. The existing all-digital phase-locked loop has the defect of high power consumption due to unreasonable circuit structure. For chips used in the on-chip system in various fields, the power consumption is reduced, the response time is shortened, and the running speed of the system is improved greatly to the system performance, so that in order to reduce the overall power consumption of the on-chip system, especially the power consumption of a mobile device, the power consumption of each functional module in the system chip needs to be reduced.
In addition, the anti-interference performance of the all-digital phase-locked loop is closely related to the phase-locked speed, the capture range and the loop bandwidth and is contradictory, so that the system stability is improved by adopting a compromise mode in common design, but the quality of the system is adversely affected in the process of compromise selection. The limitation of the circuit structure of the existing all-digital phase-locked loop and the fixed system parameters ensure that the high performance and the high stability of the chip on the chip applied to the all-digital phase-locked loop cannot be realized at the same time.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an all-digital phase-locked loop with a pipeline circuit structure and a phase-locked control method, which optimize the circuit structure of the phase-locked loop by using a pipeline technology, improve the running speed of a phase-locked system and reduce the power consumption of the system. Meanwhile, the dynamic control of the working process of the all-digital phase-locked loop is realized through the dynamic adjustment of the parameters of the pipeline digital filter, so that the phase-locking speed is improved, and the stability of the system is enhanced.
The technical scheme of the invention is as follows: the full digital phase-locked loop comprises a digital phase discriminator module, a pipeline variable mode controller module, a pipeline digital filter module, a buckling pulse control circuit module and a pipeline frequency divider module, and the design of each module circuit is completed by utilizing an electronic design automation technology.
The digital phase detector module is realized by a double-D trigger, and is provided with two signal input ends and three signal output ends, wherein the two signal input ends are a fin signal input end and a fout signal input end respectively, the three signal output ends are a ua signal output end, an ah signal output end and a be signal output end respectively, and the digital phase detector module judges the phase error and the polarity of the input signal fin and the output signal fout by detecting the rising edges of the input signal fin and the output signal fout of the all-digital phase-locked loop and generates a phase error signal ua and a polarity signal, namely an advance signal ah and a lag signal be, which reflect the input signal and the output signal.
The assembly line variable mode controller module comprises a time digital conversion module TDC and a variable mode controller, the assembly line variable mode controller module provides adjustable dynamic parameters for the assembly line digital filter, receives a phase error signal ua output by the digital phase discriminator module, and adjusts a mode value km output by the assembly line variable mode controller module according to the magnitude of the phase error signal ua, wherein the specific adjustment mode is as follows: when the phase error is larger, outputting a smaller modulus value km so as to accelerate the phase locking speed; when the phase error is smaller, a larger modulus km is output to reduce the phase jitter after the loop is locked.
The time digital conversion module TDC comprises 20-bit counters, the 20-bit counters are designed by adopting a five-stage pipeline, each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing count values, wherein the number of bits of the first stage of counter is 0-3 bits, the number of bits of the second stage of counter is 4-7 bits, the number of bits of the third stage of counter is 8-11 bits, the number of bits of the fourth stage of counter is 12-15 bits, the number of bits of the fifth stage of counter is 16-19 bits, the design of the time digital conversion module TDC is completed by adopting an ultra-high speed integrated circuit hardware description language, and the time digital conversion module TDC is connected with a variable-mode controller to obtain an automatic variable-mode controller module of the pipeline; and providing an output signal km with a variable modulus value for a reversible counter in the pipeline digital filter module according to the phase error signal ua output by the digital phase detector module.
The pipeline digital filter module is composed of 8-bit reversible counters, the reversible counters adopt a two-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value. The first-stage counter has a bit number of 0-3, the second-stage counter has a bit number of 4-7, and the modular value of the reversible counter is automatically generated by the assembly line variable-module controller module according to a preset control algorithm; the pipeline digital filter module receives an advance signal ah and a retard signal be which are obtained by comparing an input signal fin with an output feedback signal fout from the digital phase discriminator module, counts up or down according to the advance signal ah or the retard signal be, generates a carry signal inc or a borrow signal dec when the count value reaches the received modulus value of the counter, and sends the carry signal inc or the borrow signal dec to the buckling pulse control circuit module respectively.
The deduction pulse control circuit module receives a carry signal inc or a borrow signal dec sent by the pipeline digital filter module, carries out pulse deduction processing on the digital sequence signal output by the module, and sends the processed digital sequence signal to the pipeline frequency divider module; the specific implementation mode is as follows: when the carry signal inc at the input end of the deduction pulse control circuit module is at a high level, inserting a pulse into the digital sequence signal output by the deduction pulse control circuit module; when the borrowing signal dec at the other input end of the deduction pulse control circuit module is at a high level, a pulse is deducted from the digital sequence signal output by the deduction pulse control circuit module, and the digital sequence signal after the deduction pulse processing is sent to the pipeline frequency divider module for further adjustment.
The pipeline frequency divider module consists of a 24-bit counter, and the frequency division coefficient N of the pipeline frequency divider module is adjustable; the 24-bit counter adopts a three-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value; each stage is an 8-bit counter, wherein the number of bits of the first stage counter is 0-7 bits, the number of bits of the second stage counter is 8-15 bits, and the number of bits of the third stage counter is 16-23 bits; triggering the 8-bit counter of the higher stage to start counting when the 8-bit counter of the lower stage generates a carry signal, so as to carry out accumulation counting; the frequency division coefficient N is set from an external input port, namely specific parameters of the frequency division coefficient are flexibly set according to different input signal frequencies of the phase-locked loop; the parameter is set to satisfy 2 according to the ratio of the clock signal frequency of the system to the input signal frequency of the system N To select.
The output end of the carry signal inc and the borrow signal dec of the pipeline digital filter module are respectively connected with the two signal input ends of the buckling pulse control circuit module, the signal output end of the buckling pulse control circuit module is connected with the first signal input end of the pipeline frequency divider module, the frequency division coefficient N set according to the clock signal frequency and the external input port determined by the system input signal frequency is connected with the second input end of the pipeline frequency divider module, the output signal fout of the pipeline frequency divider module is a phase-locked loop output signal, and the phase-locked loop output signal is fed back to the digital phase detector module to serve as one of the input of the digital phase detector module.
According to the system structure block diagram of the all-digital phase-locked loop of the pipeline circuit structure, the invention adopts a top-down design method, is based on an electronic design automation technology, adopts VHDL language to program each module, and completes the top-layer circuit design of the all-digital phase-locked loop of the pipeline circuit structure.
In the top-level circuit of the all-digital phase-locked loop of the pipeline circuit structure, a system clock signal clk is respectively connected with input ends clk of the pipeline variable-mode controller module, the pipeline digital filter module and the buckling pulse control circuit module.
The system reset signal reset is respectively connected with the input end reset of the pipeline variable mode controller module, the pipeline digital filter module, the buckling pulse control circuit module and the pipeline frequency divider module.
The enable signal en is coupled to the input en of the pipelined digital filter module.
The system input signal fin is connected to the digital phase detector module input fin.
The output signals of the digital phase discriminator module are three, namely ah, be and ua, wherein ah, be are respectively connected with the input ends ah, be of the pipeline digital filter module, and ua is connected with the input end ua of the pipeline variable-mode controller module.
The output km of the pipeline variable mode controller module is connected with the input km of the pipeline digital filter module.
And the two output ends of the carry signal inc output ends and the borrow signal dec of the pipeline digital filter module are respectively connected with the input ends inc and dec of the buckling pulse control circuit module.
The output end idout of the buckling pulse control circuit module is connected with the input end idout of the pipeline frequency divider module.
Calculating the ratio relation between the clock signal frequency of the system and the input signal frequency of the system, setting a frequency division coefficient N, taking the frequency division coefficient N as the input end of the frequency division coefficient N of the pipeline frequency divider module, taking the output end fout of the pipeline frequency divider module as the output signal end of the system, and feeding back the output end fout of the pipeline frequency divider module to the input port of the system as the input end of the digital phase discriminator module.
The specific phase-locking control process of the all-digital phase-locked loop with the pipeline circuit structure provided by the invention is as follows:
the digital phase detector module outputs a corresponding phase lead signal ah or lag signal be and a phase error signal ua by detecting rising edges of the phase-locked loop input signal fin and the output signal fout.
The assembly line variable mode controller module digitizes and compares the phase error signal, when the phase error is larger, reduce the module value km sent into the assembly line digital filter module; when the phase error is small, the modulus km fed into the pipeline digital filter module is increased.
Meanwhile, the levels of a phase advance signal ah and a phase retard signal be output by the digital phase discriminator module are judged, when the phase advance signal ah output by the digital phase discriminator module is at a high level, the assembly line variable mode controller module counts up, and when the counted value reaches the module value km of the assembly line variable mode controller module, the assembly line digital filter module outputs a carry signal inc; when the phase lag signal be output by the digital phase discriminator module is at a high level, the pipeline variable-mode controller module performs down counting, and when the down count value reaches a mode value km, the pipeline digital filter module outputs a borrow signal dec.
The deduction pulse control circuit module adjusts the phase of the output signal idout of the deduction pulse control circuit module by adding or subtracting one system clock period time according to the carry signal inc and the borrow signal dec output by the pipeline digital filter module.
The pipeline frequency divider module sends an output signal fout of the pipeline frequency divider module into the digital phase discriminator module to be used as the input of the digital phase discriminator module together with a next period input signal fin according to a digital signal sequence output by the buckling pulse control circuit module and a frequency division coefficient N determined according to the ratio of the clock signal frequency of the system to the input signal frequency of the system, and corresponding phase advance signals ah or delay signals be and phase error signals ua are generated, so that control is performed, phase errors are gradually reduced, and finally locking of a phase-locked loop is realized.
In the all-digital phase-locked loop with the pipeline circuit structure, the pipeline variable-mode controller module, the pipeline digital filter module and the pipeline frequency divider module are designed through a multi-stage pipeline technology, so that the delay of a system is reduced, the working speed of the system is improved, and the total power consumption of the system is reduced.
The mode value of the reversible counter in the assembly line variable mode controller module changes along with the different phase errors, so that the locking speed of the reversible counter can be increased, and the maximum mode value set by the system can be automatically selected in a phase locking interval, so that the jitter of the phase of a loop output signal is greatly reduced, and the stability of the system is improved; the frequency division coefficient N of the pipeline frequency divider module is set by an external input port, so that the ratio of the clock signal frequency according to the system to the input signal frequency of the system is 2 N The phase-locked loop can realize rapid adjustment of phase errors when the frequency of the input signal of the system jumps, and the maximum modulus value is automatically selected after locking, namely, the system parameters are dynamically adjusted according to different working processes, so that the contradiction between locking speed and stability is solved, and the overall performance of the system is improved.
Compared with the prior art, the invention has the following characteristics:
the invention provides an all-digital phase-locked loop with a multistage pipeline circuit structure, which adopts an electronic design automation technology to complete system design and has the performance characteristics that:
1. the assembly line variable mode controller module, the assembly line digital filter module and the assembly line frequency divider module are arranged through the assembly line technology, so that the circuit structure of the phase-locked loop is optimized, the running speed of the phase-locked system is improved, and the system power consumption is reduced.
2. Dynamic control on the working process of the phase-locked loop is realized through dynamic adjustment of parameters of the pipeline digital filter, so that the phase-locking speed can be improved, and the stability of the system can be enhanced.
3. The phase-locked loop has the advantages of high phase locking speed, low power consumption, high system stability and the like, can reduce the cost of practical application when being applied to a system chip, and has huge market potential.
The detailed structure of the present invention is further described below with reference to the accompanying drawings and detailed description.
Drawings
FIG. 1 is a system architecture block diagram of an all-digital phase-locked loop of a pipeline circuit architecture;
FIG. 2 is a diagram of a counter circuit architecture employing a multi-stage pipeline technique;
FIG. 3 is a circuit block diagram of a pipeline variable mode controller module;
FIG. 4 is a top level circuit diagram of an all-digital phase-locked loop of a pipeline circuit structure;
fig. 5 is a waveform simulation diagram at fin=50 MHz;
fig. 6 is a waveform simulation diagram when fin=50 MHz jumps to fin=25 MHz.
Detailed Description
The all-digital phase-locked loop of the pipeline circuit structure comprises a digital phase discriminator module 1, a pipeline variable-mode controller module 5, a pipeline digital filter module 2, a buckling pulse control circuit module 3 and a pipeline frequency divider module 4. And the design of each module circuit is completed by utilizing an electronic design automation technology.
The digital phase detector module 1 is implemented by a dual D flip-flop, and has two signal input ends, namely a fin signal input end and a fout signal input end, and three signal output ends, namely a ua signal output end, an ah signal output end and a be signal output end, respectively, and the digital phase detector module 1 determines the phase error and the polarity of the input signal fin and the output signal fout by detecting rising edges of the input signal fin and the output signal fout of the all-digital phase-locked loop, and generates a phase error signal ua reflecting the input signal and the output signal, and a polarity signal, namely an advance signal ah and a retard signal be.
The assembly line variable mode controller module 5 comprises a time digital conversion module TDC5-1 and a variable mode controller 5-2, the assembly line variable mode controller module 5 provides adjustable dynamic parameters for the assembly line digital filter 2, receives a phase error signal ua output by the digital phase detector module 1, and adjusts a mode value km output by the assembly line variable mode controller module 5 according to the magnitude of the phase error signal ua, wherein the specific adjustment mode is as follows: when the phase error is larger, outputting a smaller modulus value km so as to accelerate the phase locking speed; when the phase error is smaller, a larger modulus km is output to reduce the phase jitter after the loop is locked.
The time-digital conversion module TDC5-1 comprises a 20-bit counter, the 20-bit counter adopts a five-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value. The number of bits of the first-stage counter is 0-3 bits, the number of bits of the second-stage counter is 4-7 bits, the number of bits of the third-stage counter is 8-11 bits, the number of bits of the fourth-stage counter is 12-15 bits, and the number of bits of the fifth-stage counter is 16-19 bits, as shown in fig. 2, wherein I is an input signal of the counter, and O is an output signal of the counter. The design of the time-digital conversion module TDC5-1 is completed by adopting a hardware description language of an ultra-high speed integrated circuit, and then the design is connected with the variable-mode controller 5-2 to obtain the automatic variable-mode controller module 5 of the assembly line. The reversible counter in the pipeline digital filter module 2 is provided with an output signal km of variable modulus value based on the phase error signal ua output by the digital phase detector module 1.
The pipelined digital filter module 2 is comprised of an 8-bit reversible counter that employs a two-stage pipelined design, each stage counter M comprising a register J, a 1-up and a latch S for temporarily storing a count value. The number of bits of the first-stage counter is 0-3 bits, the number of bits of the second-stage counter is 4-7 bits, and the modulus value of the reversible counter is automatically generated by the pipeline variable modulus controller module 5 according to a preset control algorithm. The pipeline digital filter module 2 receives an advance signal ah and a retard signal be obtained by comparing an input signal fin with an output feedback signal fout from the digital phase detector module 1, counts up or down according to the advance signal ah or the retard signal be, generates a carry signal inc or a borrow signal dec when the count value reaches the received counter module value, and sends the carry signal inc or the borrow signal dec to the buckling pulse control circuit module 3 respectively.
The deduction pulse control circuit module 3 receives the carry signal inc or the borrow signal dec sent by the pipeline digital filter module 2, carries out pulse deduction processing on the digital sequence signal output by the carry signal inc or the borrow signal dec, and sends the processed digital sequence signal to the pipeline frequency divider module 4. The specific implementation mode is as follows: when the carry signal inc at the input end of the deduction pulse control circuit module 3 is at a high level, inserting a pulse into the digital sequence signal output by the deduction pulse control circuit module; when the borrowing signal dec at the other input end of the deduction pulse control circuit module 3 is at a high level, a pulse is deducted from the digital sequence signal output by the deduction pulse control circuit module, and the digital sequence signal after the deduction pulse processing is sent to the pipeline frequency divider module 4 for further adjustment.
The pipeline divider module 4 is formed by a 24-bit counter, the division factor N of which is adjustable. The 24-bit counter adopts a three-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value. Each stage is an 8-bit counter, wherein the number of bits of the first stage counter is 0-7 bits, the number of bits of the second stage counter is 8-15 bits, and the number of bits of the third stage counter is 16-23 bits. Triggering the 8-bit counter of the higher stage to start counting when the 8-bit counter of the lower stage generates a carry signal, so as to carry out accumulation counting; the frequency division coefficient N is set from an external input port, namely specific parameters of the frequency division coefficient are flexibly set according to different input signal frequencies of the phase-locked loop. The parameter is set to satisfy 2 according to the ratio of the clock signal frequency of the system to the input signal frequency of the system N To select.
The output end of a phase error signal ua of the digital phase detector module 1 is connected with the input end of the pipeline variable mode controller module 5, the output ends of a leading signal ah and a lagging signal be are respectively connected with the first signal input end and the second signal input end of the pipeline digital filter module 2, the output end of a mode value signal km of the pipeline variable mode controller module 5 is connected with the third signal input end of the pipeline digital filter module 2, the output end of a carry signal inc and the output end of a borrow signal dec of the pipeline digital filter module 2 are respectively connected with the two signal input ends of the buckling pulse control circuit module 3, the signal output end of the buckling pulse control circuit module 3 is connected with the first signal input end of the pipeline frequency divider module 4, the frequency division coefficient N set according to the external input port determined by the clock signal frequency and the system input signal frequency is connected with the second input end of the pipeline frequency divider module 4, and the output signal fout of the pipeline frequency divider module 4 is a phase-locked loop output signal and is fed back to the digital phase detector module 1 as one of the input of the digital phase detector module 1.
According to the system structure block diagram of the all-digital phase-locked loop of the pipeline circuit structure, the invention adopts a top-down design method, is based on an electronic design automation technology, adopts VHDL language to program each module, and completes the top-layer circuit design of the all-digital phase-locked loop of the pipeline circuit structure.
In the top-level circuit of the all-digital phase-locked loop of the pipeline circuit structure, a system clock signal clk is respectively connected with input ends clk of the pipeline variable mode controller module 5, the pipeline digital filter module 2 and the buckling pulse control circuit module 3.
The system reset signal reset is respectively connected with the input ends reset of the pipeline variable mode controller module 5, the pipeline digital filter module 2, the buckling pulse control circuit module 3 and the pipeline frequency divider module 4.
The enable signal en is connected to the input en of the pipeline digital filter module 2.
The system input signal fin is connected to the input fin of the digital phase detector module 1.
The output signals of the digital phase discriminator module are three, namely ah, be and ua, wherein ah, be are respectively connected with the input ends ah, be of the pipeline digital filter module 2, and ua is connected with the input end ua of the pipeline variable-mode controller module 5.
The output km of the pipeline variable mode controller module 5 is connected with the input km of the pipeline digital filter module 2.
The two output ends of the carry signal inc output ends and the borrow signal dec of the pipeline digital filter module 2 are respectively connected with the input ends inc and dec of the buckling pulse control circuit module 3.
The output end idout of the buckling pulse control circuit module 3 is connected with the input end idout of the pipeline frequency divider module 4.
Calculating the ratio relation between the clock signal frequency of the system and the input signal frequency of the system, setting a frequency division coefficient N, taking the frequency division coefficient N as the input end of the frequency division coefficient N of the pipeline frequency divider module 4, taking the output end fout of the pipeline frequency divider module 4 as the output signal end of the system, and feeding back to the input port of the system as the input end of the digital phase discriminator module 1.
The specific phase-locking control process of the all-digital phase-locked loop with the pipeline circuit structure provided by the invention is as follows:
the digital phase detector module 1 outputs a corresponding phase lead signal ah or lag signal be and a phase error signal ua by detecting rising edges of the phase locked loop input signal fin and the output signal fout.
The pipeline variable mode controller module 5 digitizes and compares the phase error signal, when the phase error is larger, the module value km sent into the pipeline digital filter module 2 is reduced; when the phase error is small, the modulus km fed into the pipeline digital filter module 2 is increased.
Meanwhile, the levels of a phase advance signal ah and a phase retard signal be output by the digital phase discriminator module 1 are judged, when the phase advance signal ah output by the digital phase discriminator module is at a high level, the pipeline variable mode controller module 5 counts up, and when the counted value reaches the module value km of the pipeline variable mode controller module 5, the pipeline digital filter module 2 outputs a carry signal inc; when the phase lag signal be output by the digital phase discriminator module 1 is at a high level, the pipeline variable mode controller module 5 performs down counting, and when the down counting value reaches a mode value km, the pipeline digital filter module 2 outputs a borrow signal dec.
The deduction pulse control circuit module 3 adjusts the phase of the output signal idout of the deduction pulse control circuit module 3 by adding or subtracting one system clock period time according to the carry signal inc and the borrow signal dec output by the pipeline digital filter module 2.
The pipeline frequency divider module 4 sends an output signal fout of the pipeline frequency divider module 4 into the digital phase discriminator module 1 according to a digital signal sequence output by the buckling pulse control circuit module and a frequency division coefficient N determined according to the ratio of the clock signal frequency of the system to the input signal frequency of the system, and the output signal fout and the next period input signal fin are used as the input of the digital phase discriminator module 1 together to generate a corresponding phase advance signal ah or a corresponding phase retard signal be and a corresponding phase error signal ua, so that the phase error is gradually reduced and finally locking of a phase-locked loop is realized.
The system simulation is carried out on the all-digital phase-locked loop circuit of the pipeline circuit structure, and the simulation result is shown in fig. 5-6, wherein fig. 5 is a simulation waveform diagram when the frequency is 50MHz, fig. 6 is a simulation waveform diagram when the frequency of an input signal jumps from 50MHz to 25MHz, en is a system enabling signal, reset is a system reset signal, clk is a system clock signal, fin is a system input signal, and fout is a system output signal.
As can be seen from the phase-locked loop simulation, as shown in fig. 5, in the phase adjustment interval, the modulus km of the reversible counter in the phase-locked loop changes with different phase errors, so that the locking speed can be increased; in the phase locking interval, the maximum modulus km set by the system can be automatically selected, so that the jitter of the phase of the loop output signal can be greatly reduced, and the stability of the system is improved.
As can be seen from fig. 6, when the input frequency hops, the phase-locked loop can quickly lock the frequency of the signal in the first period after the frequency hops, and quickly adjust the phase error, and lock the signal after about 2.5 μs, and also automatically select the maximum km value after locking. The phase-locked loop can dynamically adjust system parameters according to different working processes, thereby fundamentally solving the contradiction between the improvement of locking speed and stability and improving the overall performance of the phase-locked system.
Taking the clock signal frequency of the system as 200MHz, and when the input signal frequency of the system is 50MHz, respectively carrying out system simulation on the traditional phase-locked loop and the assembly line phase-locked loop, and carrying out time sequence analysis and power consumption analysis on simulation results. The specific results are analyzed as shown in table 1:
table 1 clk=200 MHZ, fin=50 MHZ results comparison
Delay/(ns) Power consumption/(uW)
Conventional ADPLL 3.424 117390
Pipelined ADPLL 2.146 116760
As can be seen from table 1, first, the system delay of the phase-locked loop is reduced by 1.278ns compared to the conventional phase-locked loop. Second, at a clock frequency of 200MHZ, the total power consumption of the system is reduced by 630 μw compared with a conventional phase-locked loop. Therefore, the all-digital phase-locked loop with the pipeline circuit structure can reduce the system delay, improve the working speed of the system and reduce the total power consumption of the system.

Claims (1)

1. The phase-locking control method of the all-digital phase-locked loop of the pipeline circuit structure is characterized by comprising the following steps of:
the full digital phase-locked loop of the pipeline circuit structure comprises a digital phase discriminator module, a pipeline variable mode controller module, a pipeline digital filter module, a buckling pulse control circuit module and a pipeline frequency divider module, and the design of each module circuit is completed by utilizing an electronic design automation technology;
the digital phase detector module is realized by a double-D trigger, and is provided with two signal input ends and three signal output ends, wherein the two signal input ends are a fin signal input end and a fout signal input end respectively, the three signal output ends are a ua signal output end, an ah signal output end and a be signal output end respectively, and the digital phase detector module judges the phase error and the polarity of the input signal fin and the output signal fout by detecting the rising edges of the input signal fin and the output signal fout of an all-digital phase-locked loop and generates a phase error signal ua and a polarity signal, namely an advance signal ah and a retard signal be, which reflect the input signal and the output signal;
the assembly line variable mode controller module comprises a time digital conversion module TDC and a variable mode controller, the assembly line variable mode controller module provides adjustable dynamic parameters for the assembly line digital filter, receives a phase error signal ua output by the digital phase discriminator module, and adjusts a mode value km output by the assembly line variable mode controller module according to the magnitude of the phase error signal ua, wherein the specific adjustment mode is as follows: when the phase error is larger, outputting a smaller modulus value km so as to accelerate the phase locking speed; when the phase error is smaller, outputting a larger modulus km to reduce the phase jitter after the loop is locked;
the time digital conversion module TDC comprises 20-bit counters, the 20-bit counters are designed by adopting a five-stage pipeline, each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing count values, wherein the number of bits of the first stage of counter is 0-3 bits, the number of bits of the second stage of counter is 4-7 bits, the number of bits of the third stage of counter is 8-11 bits, the number of bits of the fourth stage of counter is 12-15 bits, the number of bits of the fifth stage of counter is 16-19 bits, the design of the time digital conversion module TDC is completed by adopting an ultra-high speed integrated circuit hardware description language, and the time digital conversion module TDC is connected with a variable-mode controller to obtain an automatic variable-mode controller module of the pipeline; providing an output signal km with a variable modulus for a reversible counter in a pipeline digital filter module according to a phase error signal ua output by a digital phase detector module;
the pipeline digital filter module consists of 8-bit reversible counters, the reversible counters adopt a two-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value; the first-stage counter has a bit number of 0-3, the second-stage counter has a bit number of 4-7, and the modular value of the reversible counter is automatically generated by the assembly line variable-module controller module according to a preset control algorithm; the pipeline digital filter module receives an advance signal ah and a retard signal be which are obtained by comparing an input signal fin with an output feedback signal fout from the digital phase discriminator module, counts up or down according to the advance signal ah or the retard signal be, generates a carry signal inc or a borrow signal dec when the count value reaches the received modulus value of the counter, and sends the carry signal inc or the borrow signal dec to the buckling pulse control circuit module respectively;
the deduction pulse control circuit module receives a carry signal inc or a borrow signal dec sent by the pipeline digital filter module, carries out pulse deduction processing on the digital sequence signal output by the module, and sends the processed digital sequence signal to the pipeline frequency divider module; the specific implementation mode is as follows: when the carry signal inc at the input end of the deduction pulse control circuit module is at a high level, inserting a pulse into the digital sequence signal output by the deduction pulse control circuit module; when the borrowing signal dec at the other input end of the deduction pulse control circuit module is at a high level, deducting a pulse from the digital sequence signal output by the deduction pulse control circuit module, and sending the digital sequence signal subjected to deduction pulse processing to the pipeline frequency divider module for further adjustment;
the pipeline frequency divider module consists of a 24-bit counter, and the frequency division coefficient N of the pipeline frequency divider module is adjustable; the 24-bit counter adopts a three-stage pipeline design, and each stage of counter M comprises a register J, a 1 adder and a latch S for temporarily storing a count value; each stage is an 8-bit counter, wherein the number of bits of the first stage counter is 0-7 bits, the number of bits of the second stage counter is 8-15 bits, and the number of bits of the third stage counter is 16-23 bits; each time the 8-bit counter of the lower stage generates a carry signal, the 8-bit counter of the higher stage is triggeredStarting counting, and accumulating and counting according to the starting counting; the frequency division coefficient N is set from an external input port, namely specific parameters of the frequency division coefficient are flexibly set according to different input signal frequencies of the phase-locked loop; the parameter is set to satisfy 2 according to the ratio of the clock signal frequency of the system to the input signal frequency of the system N To select;
the output end of a carry signal inc and the output end of a borrow signal dec of the pipeline digital filter module are respectively connected with two signal input ends of a buckling pulse control circuit module, the signal output end of the buckling pulse control circuit module is connected with the first signal input end of a pipeline frequency divider module, a frequency division coefficient N which is set according to the clock signal frequency and an external input port which is determined by the system input signal frequency is connected with the second input end of the pipeline frequency divider module, and the output signal fout of the pipeline frequency divider module is a phase-locked loop output signal and is fed back to the digital phase detector module as one of the input of the digital phase detector module;
the full-digital phase-locked loop of the pipeline circuit structure adopts a top-down design method, and based on an electronic design automation technology, each module is programmed by adopting VHDL language, so that the top-level circuit design of the full-digital phase-locked loop of the pipeline circuit structure is completed;
in a top-level circuit of an all-digital phase-locked loop of a pipeline circuit structure, a system clock signal clk is respectively connected with input ends clk of a pipeline variable-mode controller module, a pipeline digital filter module and a buckling pulse control circuit module;
the system reset signal reset is respectively connected with the input end reset of the assembly line variable mode controller module, the assembly line digital filter module, the buckling pulse control circuit module and the assembly line frequency divider module;
the enabling signal en is connected with the input end en of the pipeline digital filter module;
the system input signal fin is connected with the digital phase discriminator module input terminal fin;
the output signals of the digital phase discriminator module are three, namely ah, be and ua, wherein ah, be are respectively connected with the input ends ah, be of the pipeline digital filter module, and ua is connected with the input end ua of the pipeline variable-mode controller module;
the output km of the pipeline variable mode controller module is connected with the input km of the pipeline digital filter module;
the two output ends of the pipeline digital filter module carry signal inc output ends and borrow signal dec are respectively connected with the input ends inc and dec of the buckling pulse control circuit module;
the output end idout of the buckling pulse control circuit module is connected with the input end idout of the pipeline frequency divider module;
calculating the ratio relation between the clock signal frequency of the system and the input signal frequency of the system, setting a frequency division coefficient N, taking the frequency division coefficient N as the input end of the frequency division coefficient N of the pipeline frequency divider module, taking the output end fout of the pipeline frequency divider module as the output signal end of the system, and feeding back the output end fout of the pipeline frequency divider module to the input port of the system as the input end of the digital phase discriminator module;
the digital phase discriminator module outputs a corresponding phase advance signal ah or a corresponding phase retard signal be and a corresponding phase error signal ua by detecting rising edges of an input signal fin and an output signal fout of the phase-locked loop;
the assembly line variable mode controller module digitizes and compares the phase error signal, when the phase error is larger, reduce the module value km sent into the assembly line digital filter module; when the phase error is smaller, increasing the modulus km sent into the pipeline digital filter module;
meanwhile, the levels of a phase advance signal ah and a phase retard signal be output by the digital phase discriminator module are judged, when the phase advance signal ah output by the digital phase discriminator module is at a high level, the assembly line variable mode controller module counts up, and when the counted value reaches the module value km of the assembly line variable mode controller module, the assembly line digital filter module outputs a carry signal inc; when the phase lag signal be output by the digital phase discriminator module is at a high level, the pipeline variable-mode controller module performs down counting, and when the down counting value reaches a mode value km, the pipeline digital filtering module outputs a borrow signal dec;
the deduction pulse control circuit module adjusts the phase of an output signal idout of the deduction pulse control circuit module by adding or subtracting one system clock period time according to a carry signal inc and a borrow signal dec output by the pipeline digital filter module;
the pipeline frequency divider module sends an output signal fout of the pipeline frequency divider module into the digital phase discriminator module to be used as the input of the digital phase discriminator module together with a next period input signal fin according to a digital signal sequence output by the buckling pulse control circuit module and a frequency division coefficient N determined according to the ratio of the clock signal frequency of the system to the input signal frequency of the system, and corresponding phase advance signals ah or delay signals be and phase error signals ua are generated, so that control is performed, phase errors are gradually reduced, and finally locking of a phase-locked loop is realized.
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