CN109148449A - The manufacturing method of semiconductor device and semiconductor device - Google Patents

The manufacturing method of semiconductor device and semiconductor device Download PDF

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Publication number
CN109148449A
CN109148449A CN201810561064.7A CN201810561064A CN109148449A CN 109148449 A CN109148449 A CN 109148449A CN 201810561064 A CN201810561064 A CN 201810561064A CN 109148449 A CN109148449 A CN 109148449A
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semiconductor region
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semiconductor
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groove
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CN109148449B (en
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豊田善昭
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L21/8232—Field-effect technology
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Present invention offer can improve the surge tolerance of circuit portion and can be reduced the semiconductor device of the conducting resistance in deferent segment portion and the manufacturing method of semiconductor device.The deferent segment portion (41) of semiconductor substrate (13) is provided with longitudinal type MOSFET (10), circuit portion (42) is provided with lateral type n-channel MOSFET (20) and by penetrating through p along depth direction‑The p of type well region (21)+The longitudinal type diode (30) that type diffusion region (31) is constituted.It is set to the n of (10) longitudinal type MOSFET+The bottom surface of the first contact trench (11a) of type source region (7) is by p++Type contact zone (8) covering.It is set to the n of lateral type n-channel MOSFET+The bottom surface of the second contact trench (27a) of type source region (22) is by p++Type contact zone (24) covering, is set to n+The entirety of the third contact trench (28a) in type drain region (23) is by n+The covering of type drain region.

Description

The manufacturing method of semiconductor device and semiconductor device
Technical field
The present invention relates to the manufacturing methods of semiconductor device and semiconductor device.
Background technique
In the past, for the raising reliability of power semiconductor, miniaturization and cost effective purpose, there is known will The control of longitudinal type power semiconductor and the longitudinal type power semiconductor, the lateral type semiconductor element for protecting circuit The power semiconductor arrangement that part is arranged on the same semiconductor substrate (semiconductor chip) is (for example, referring to following patent documents 1 ~3).
For the structure of existing semiconductor device, illustrate the longitudinal type n-channel power MOSFET of deferent segment (Metal Oxide Semiconductor Field Effect Transistor: insulated-gate type field effect transistor) and control The function on the same semiconductor substrate is arranged in the lateral type CMOS (Complementary MOS: complementary type MOS) of circuit processed Rate semiconductor device.Figure 17 is the sectional view for indicating the structure of existing semiconductor device.
Existing semiconductor device shown in Figure 17 is to set ditch for the longitudinal type n-channel power MOSFET of deferent segment Vehicle-mounted high-end (high side) type Power IC (Integrated of the longitudinal type MOSFET 110 of slot grid structure Circuit: integrated circuit) an example.Existing semiconductor device shown in Figure 17 has defeated on semiconductor substrate 113 Section portion 141 and circuit portion 142 out.Semiconductor substrate 113 is to make n-102 epitaxial growth of type semiconductor layer is in n+Type initial substrate 101 Front on made of epitaxial substrate.
In deferent segment portion 141, the longitudinal type MOSFET 110 configured with deferent segment.In deferent segment portion 141, n+Type is initial Substrate 101 and n-Type semiconductor layer 102 is functioned respectively as drain region and drift region.It is connected to the back of semiconductor substrate 113 Face (n+The back side of type initial substrate 101) drain electrode (drain terminal) 112 be the power voltage terminal for being connected with vehicle battery Sub (hereinafter referred to as Vcc terminal).
In the face side (n of semiconductor substrate 113-Type semiconductor layer 102 relative to n+101 side of type initial substrate is opposite Side), be provided with ground terminal (hereinafter referred to as GND terminal) and output terminal (hereinafter referred to as OUT terminal).In OUT terminal Son is connected with the source electrode (source terminal) 111 of longitudinal type MOSFET 110.Symbol 103~109 is longitudinal type MOSFET respectively 110 groove, gate insulating film, gate electrode, p-type base area, n+Type source region, p++Type contact zone and interlayer dielectric.
In circuit portion 142, the lateral type CMOS of control circuit etc. configured with control longitudinal type MOSFET 110.Figure 17 In illustrate only lateral type p ditch in the complementary connection for the lateral type CMOS for constituting the control circuit for being configured at circuit portion 142 Lateral type n-channel MOSFET 120 in road MOSFET and lateral type n-channel MOSFET 120.In circuit portion 142, partly leading The positive superficial layer of structure base board 113, is selectively provided with p-Type well region 121.
In p-The inside of type well region 121 is respectively selectively provided with the n of lateral type n-channel MOSFET 120+Type source region 122、n+Type drain region 123 and p++Type contact zone 124.p++Type contact zone 124 and n+Type source region 122 together with source electrode (source Extreme son) the 127 contact hole 109a exposings for forming contact (electrical contact).
In addition, in p-The inside of type well region 121, in p in a manner of being separated with lateral type n-channel MOSFET 120-Type well region 121 periphery is nearby provided with p+Type diffusion region 131.p+The depth of type diffusion region 131 can be with p-The depth phase of type well region 121 With or compare p-The depth of type well region 121 is deep.p+Type diffusion region 131 is as preventing on the front by being laminated in semiconductor substrate 113 P caused by the current potential of wiring layer-The reversion of the reversion of type well region 121 prevents layer and functions.In addition, p+Type diffusion region 131 As the aftermentioned longitudinal type diode 130 for the surge protection for being built in circuit portion 142 anode region and function.
In p+The inside of type diffusion region 131 is selectively provided with and forms the p contacted with wiring layer 133++Type contact zone 132.In the case where lateral type n-channel MOSFET 120 is shown in Figure 17 for the various inverter circuits in control circuit The source electrode 127 of one example, lateral type n-channel MOSFET 120 is electrically connected with GND terminal.P as backgate-Type well region 121 also via p++Type contact zone 124 and source electrode 127 and be electrically connected with GND terminal.
In the drain electrode 128 of lateral type n-channel MOSFET 120, it is electrically connected with the various lateral type semiconductors that diagram is omitted Element (the lateral type p-channel MOSFET of resistive element and/or the lateral type CMOS of composition control circuit).Symbol 122,123, 125,126 be lateral type n-channel MOSFET 120 n+Type source region, n+Type drain region, gate insulating film and gate electrode.Such Vehicle-mounted Power IC, it is desirable that high surge tolerance, deferent segment longitudinal type MOSFET 110 performance improve (low electric conduction It hinders, the high speed of switching speed).
In the Power IC shown in Figure 17, in order to ensure high surge tolerance between Vcc terminal and OUT terminal, need to mention The surge tolerance of the longitudinal type MOSFET 110 of high deferent segment.In the past, as improve MOSFET monomer surge tolerance and The contact structures of performance are proposed by filling out in being set to for semiconductor substrate in the inside of the groove for the part that contact hole exposes Enter electrode layer, forms the groove interface construction of electrode layer with the contact of semiconductor portion (semiconductor substrate) in the inner wall of the groove (for example, referring to following patent documents 4~7).
By making MOSFET become groove interface construction, it is able to suppress parasitic bipolar action when avalanche breakdown, and can Improve surge tolerance.In addition, by making MOSFET become groove interface construction, thus the contact between electrode layer and semiconductor portion Area increases, and thus, it is possible to reduce contact resistance.Therefore, by maintaining contact resistance to make unit cell (the composition list of element Position) miniaturization, or do not change the size of unit cell and reduce contact resistance, thus, it is possible to reduce the conducting resistance of MOSFET RonA(mΩcm2)。
On the other hand, in order to ensure high surge tolerance between Vcc terminal and GND terminal, in Vcc terminal and GND terminal Between be connected with surge current side by side and absorb with the longitudinal type diode (not shown) of (surge protection use).Two pole of longitudinal type Pipe is formed in and the longitudinal type MOSFET 110 of deferent segment and/or various lateral type circuit elements (lateral type n-channel MOSFET 120 etc.) identical semiconductor substrate 113.At this point, the increase in order to inhibit process number, the longitudinal type two of surge current absorption The p-type anode region of pole pipe prevents the p of layer with above-mentioned reversion is become+Type diffusion region 131 is formed simultaneously.
P-type anode region and p due to the longitudinal type diode of surge current absorption+Type diffusion region 131 becomes identical It constitutes, so in circuit portion 142, by p+Type diffusion region 131 and n-Type substrate regions 102a is formed and surge current absorption The longitudinal type diode 130 of the identical pn-junction structure of longitudinal type diode.This structure with it is built-in multiple small in circuit portion 142 The longitudinal type diode 130 of area is equivalent.n-Type substrate regions 102a is n-Type semiconductor layer 102 is formed without p-Type Well region 121 etc. and directly with the original remaining part of conductivity type and impurity concentration.
In this way, a part for the circuit portion 142 for occupying large area in Power IC to be used as to the longitudinal type of surge protection Diode.The longitudinal type of surge protection is independently formed with the part other than the circuit portion 142 of semiconductor substrate 113 as a result, The case where diode, is compared, and the effective pn-junction area of the longitudinal type diode of surge protection becomes larger.Surge protection is indulged To type diode surge tolerance due to becoming larger with pn-junction area in ratio, so along with the longitudinal type two of surge protection The effective pn-junction area of pole pipe becomes larger, and the surge tolerance of Power IC improves.
In addition, the pressure resistance of longitudinal type diode increases with the rising of temperature.Therefore, even if current convergence is utilizing electricity The a part in road portion 142 and the longitudinal type diode 130 of small area formed, the pressure resistance of the longitudinal type diode 130 also can be because It generates heat and increases, thus the current convergence of longitudinal type diode 130 is mitigated.Therefore, as described above, even if making to utilize electricity The a part in road portion 142 and the longitudinal type diode 130 of surge protection formed spreads presence in circuit portion 142, also not Partial breakdown easily occurs in circuit portion 142.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2000-091344 bulletin
Patent document 2: No. 5641131 bulletins of Japanese Patent No.
Patent document 3: No. 6037085 bulletins of Japanese Patent No.
Patent document 4: No. 4488660 bulletins of Japanese Patent No.
Patent document 5: No. 5578165 bulletins of Japanese Patent No.
Patent document 6: No. 5388495 bulletins of Japanese Patent No.
Patent document 7: Japanese Unexamined Patent Publication 2009-043966 bulletin
Summary of the invention
Technical problem
However, in above-mentioned existing Power IC (referring to Fig.1 7), for realizing between Vcc terminal and GND terminal High surge tolerance, new discovery there is a problem of following.By the circuit portion 142 in Power IC, as lateral type n-channel The source electrode of MOSFET 120 and the n for being formed with high impurity concentration+Type source region 122, so that being formed makes n+Type source region 122 is emitter, Make p-Type well region 121 is base stage, makes n-Type substrate regions 102a is the parasitic bipolar element 143 of the longitudinal type of collector.
The n of lateral type n-channel MOSFET 120+Type source region 122 is electrically connected with the GND terminal of low potential side.Therefore, if Increase along with the rising of surge voltage in the electric current (hereinafter referred to as avalanche current) 144 that circuit portion 142 generates, then snowslide The electric current 144a of a part of electric current (hole current) is via p-Type well region 121 and flow into n+Type source region 122.Electric current 144a becomes At base current, parasitic bipolar element 143 becomes on state and occurs to jump logical (Snap-Back).
Lead to if parasitic bipolar element 143 occurs to jump, the resistance of circuit portion 142 drastically reduces and electric current 144a is concentrated on The n of lateral type n-channel MOSFET 120+Type source region 122.The n of lateral type n-channel MOSFET 120+Type source region 122 due to than Lesser area is formed, so the breakdown potential flow of lateral type n-channel MOSFET 120 is small.Therefore, it is possible to lateral type n-channel The n of MOSFET 120+Type source region 122 is breakdown because of the concentration of electric current 144a.
If the n of lateral type n-channel MOSFET 120+Type source region 122 is destroyed because of current convergence, even if then increasing longitudinal The pn-junction area of type diode 130 and the destruction tolerance for improving longitudinal type diode 130, the surge tolerance of Power IC entirety also root The logical electric current 144a of jump occurs according to parasitic bipolar element 143 and determines.Therefore, it is impossible to effectively improve the surge of Power IC entirety Tolerance.
In order to solve this problem, it needs to occur to jump even if parasitic bipolar element 143 and lead to, circuit portion 142 is not also breakdown Structure (hereinafter referred to as first structure), or parasitic bipolar element 143 is not susceptible to jump logical structure in circuit portion 142 (hereinafter referred to as second structure).In above-mentioned first structure, if even if in circuit portion 142 parasitic bipolar element 143 Occur to jump logical, circuit portion 142 is not also breakdown, then more than for scheduled current value when the parasitic bipolar element 143 become guarantor Shield element, the absorbability substantial increase of surge current, is thus beneficial to surge tolerance compared with longitudinal type diode 130 Raising.However when circuit portion 142 is miniaturize, the n of lateral type n-channel MOSFET 120+The area of type source region 122 subtracts It is few, and make n+The width that the contact hole 109a of contact is formed between type source region 122 and source electrode 127 narrows, contact hole 109a Breakdown current amount become smaller.Therefore, because parasitic bipolar element 143 occurs to jump the current convergence after leading to, thus and n+Type source region The contact hole 109a of 122 connections is easy to breakdown, and the breakdown potential flow of circuit portion 142 further decreases.Accordingly, it is difficult to the electricity that gets both The miniaturization in road portion 142 and the increase of breakdown potential flow.Thus it would be desirable to achieve above-mentioned second structure, is posted in circuit portion 142 Raw bipolar cell 143 is not susceptible to jump logical.
Above patent document 4~7 is to improve (surge about the characteristic for carrying out longitudinal type MOSFET using groove interface construction Tolerance improves, low on-resistance) technology, do not refer in above patent document 4~7 related solution by the circuit of Power IC The problem of parasitic structure in portion causes and the content for improving the surge tolerance of Power IC.In addition, not having in above patent document 4~7 Have refer in relation to by groove interface construction come and meanwhile improve the content of the deferent segment of Power IC and the characteristic of circuit portion.In addition, Vertical gate semiconductor element and electricity in relation to deferent segment can be suitably applied to are not referred in above patent document 4~7 The groove interface construction of both lateral type semiconductor elements on road.
The present invention in order to solve above-mentioned the problems of the prior art, and it is an object of the present invention to provide the same semiconductor substrate have In the semiconductor device of standby main circuit portion and the circuit portion for controlling the main circuit portion, the surge tolerance of circuit portion can be improved, and And it can be improved the semiconductor device of the electrical characteristics in main circuit portion and the manufacturing method of semiconductor device.
Technical solution
In order to solve above-mentioned problem, it achieves the object of the present invention, so that semiconductor device of the invention is same half Have first element and second element on conductor substrate, and there is following features.Above-mentioned first element has the second conduction First semiconductor region of type, the second semiconductor region of the first conductive type, the third semiconductor region of the second conductive type, the first conductive type Semiconductor layer, the first gate insulating film, first gate electrode, first groove, first electrode and second electrode.Above-mentioned the first half lead Body area is selectively arranged at the superficial layer of the first interarea of the above-mentioned semiconductor substrate of the first conductive type.Above-mentioned second semiconductor Area is selectively arranged at the inside of above-mentioned first semiconductor region.Above-mentioned third semiconductor region is selectively arranged at above-mentioned first The inside of semiconductor region.Above-mentioned third semiconductor region impurity concentration compared with above-mentioned first semiconductor region is high.
Above-mentioned semiconductor layer is set to above-mentioned first semiconductor region of ratio of above-mentioned semiconductor substrate closer to the second main surface side Position, and contacted with the first semiconductor region.Above-mentioned the second the half of above-mentioned first gate insulating film and above-mentioned first semiconductor region lead Region between body area and above-mentioned semiconductor layer is placed in contact with.Above-mentioned first gate electrode is set to across above-mentioned first gate insulation Film and the side opposite with above-mentioned first semiconductor region.Above-mentioned first groove is to spread above-mentioned second semiconductor region and above-mentioned third The mode of semiconductor region is arranged at a predetermined depth from the start of calculation of the first interarea of above-mentioned semiconductor substrate.Above-mentioned first electrode filling To the inside of above-mentioned first groove, it is electrically connected with above-mentioned second semiconductor region and above-mentioned third semiconductor region.Above-mentioned second electrode It is set to the second interarea of above-mentioned semiconductor substrate, is electrically connected with above-mentioned semiconductor substrate.
Above-mentioned second element has the 4th semiconductor region of the second conductive type, the 5th semiconductor region of the first conductive type, the The 7th semiconductor region, the second gate insulating film, the second gate electrode, second of 6th semiconductor region of one conductivity type, the second conductive type Groove, third groove, third electrode and the 4th electrode.Above-mentioned 4th semiconductor region is separated and is selected with above-mentioned first semiconductor region Selecting property it is set to the superficial layer of the first interarea of above-mentioned semiconductor substrate.Above-mentioned 5th semiconductor region is selectively arranged at State the inside of the 4th semiconductor region.On above-mentioned 6th semiconductor region and above-mentioned 5th semiconductor region are separated and are selectively arranged at State the inside of the 4th semiconductor region.Above-mentioned 7th semiconductor region is selectively arranged at the inside of above-mentioned 4th semiconductor region.On It is high to state the 7th semiconductor region impurity concentration compared with above-mentioned 4th semiconductor region.Above-mentioned second gate insulating film is led with the above-mentioned 4th half The region between above-mentioned 5th semiconductor region and above-mentioned 6th semiconductor region in body area is placed in contact with.Above-mentioned second gate electricity Pole is set to across above-mentioned second gate insulating film and the side opposite with above-mentioned 4th semiconductor region.
Above-mentioned second groove spreads above-mentioned 5th semiconductor region and above-mentioned 7th semiconductor region, from above-mentioned semiconductor substrate The start of calculation of first interarea is arranged at a predetermined depth.Above-mentioned third groove is started from the first interarea of above-mentioned semiconductor substrate with predetermined Depth be set to above-mentioned 6th semiconductor region.Above-mentioned third electrode is filled into the inside of above-mentioned second groove, with the above-mentioned 5th Semiconductor region and the electrical connection of above-mentioned 7th semiconductor region.Above-mentioned 4th electrode is filled into the inside of above-mentioned third groove, and above-mentioned The electrical connection of 6th semiconductor region.In the inside of above-mentioned 4th semiconductor region, separates with above-mentioned second element and be selectively arranged There is the 8th semiconductor region of the second conductive type.Above-mentioned 8th semiconductor region penetrates through above-mentioned from the first interarea of above-mentioned semiconductor substrate 4th semiconductor region and reach above-mentioned semiconductor layer.Above-mentioned 8th semiconductor region impurity concentration compared with above-mentioned 4th semiconductor region It is high.Depth as shallow of the depth of above-mentioned third groove than above-mentioned 6th semiconductor region.Above-mentioned 7th semiconductor region covering above-mentioned second Scheduled depth, impurity concentration highest are being started from the first interarea of above-mentioned semiconductor substrate in the bottom surface of groove.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned second groove Depth as shallow of the depth than above-mentioned 5th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned second groove Depth is deeper than the depth of above-mentioned 5th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that be also equipped with the second conduction 9th semiconductor region of type, the 9th semiconductor region are selectively arranged at the inside of above-mentioned 4th semiconductor region, and cover State second groove is the side wall of opposite side relative to above-mentioned 5th semiconductor region side, and above-mentioned 9th semiconductor region Impurity concentration is higher than the impurity concentration of above-mentioned 4th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned 7th semiconductor Area is contacted with above-mentioned 9th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned 7th semiconductor Area is contacted with above-mentioned 5th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned 7th semiconductor Area, which has, spreads the second conductive type impurity from the bottom surface of above-mentioned second groove to the inner radiation shape of above-mentioned 4th semiconductor region Made of circle or ellipse cross sectional shape.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned 7th semiconductor Area is set to across above-mentioned 5th semiconductor region and the side opposite with above-mentioned 6th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned third groove It is whole to be covered by above-mentioned 6th semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned first groove Depth as shallow of the depth than above-mentioned second semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned first groove is passed through Lead to above-mentioned second semiconductor region and reaches above-mentioned first semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned third semiconductor Area is contacted with above-mentioned second semiconductor region.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned third semiconductor Area, which has, spreads the second conductive type impurity from the bottom surface of above-mentioned first groove to the inner radiation shape of above-mentioned first semiconductor region Made of circle or ellipse cross sectional shape.
In addition, semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that above-mentioned 8th semiconductor Area is arranged along the periphery of above-mentioned 4th semiconductor region, surrounds around above-mentioned second element.
In addition, in order to solve above-mentioned problem, achieving the object of the present invention, the manufacturing method of semiconductor device of the invention It is to have the manufacturing method of the semiconductor device of first element and second element on the same semiconductor substrate, and have following Feature.The formation process of above-mentioned first element includes first step~the 8th process.In above-mentioned first step, led first The superficial layer of the semiconductor layer of electric type is formed selectively the first semiconductor region of the second conductive type, the semiconductor of the first conductive type The superficial layer of layer constitutes the first interarea of the above-mentioned semiconductor substrate of the first conductive type.In above-mentioned the second step, above-mentioned The inside in semiconductor area is formed selectively the second semiconductor region of the first conductive type.In above-mentioned the third step, above-mentioned The inside of first semiconductor region is formed selectively that impurity concentration is higher than the impurity concentration of above-mentioned first semiconductor region second to be led The third semiconductor region of electric type.
In above-mentioned the fourth step, above-mentioned second semiconductor region and above-mentioned semiconductor with above-mentioned first semiconductor region are formed First gate insulating film of the region contact between layer.In above-mentioned 5th process, across above-mentioned first gate insulating film and with it is upper It states the opposite side of the first semiconductor region and forms first gate electrode.In above-mentioned 6th process, above-mentioned second semiconductor region is spread With above-mentioned third semiconductor region, first groove is formed at a predetermined depth from the start of calculation of the first interarea of above-mentioned semiconductor substrate.? In above-mentioned 7th process, first electrode is inserted in the inside of above-mentioned first groove.In above-mentioned 8th process, in above-mentioned semiconductor Second interarea of substrate forms second electrode.
The formation process of above-mentioned second element includes the 9th process~the 18th process.In above-mentioned 9th process, upper The superficial layer for stating semiconductor layer separates with above-mentioned first semiconductor region and is formed selectively the 4th semiconductor of the second conductive type Area.In above-mentioned tenth process, the 5th half of the first conductive type is formed selectively in the inside of above-mentioned 4th semiconductor region and is led Body area.In above-mentioned 11st process, in the inside of above-mentioned 4th semiconductor region, separates and select with above-mentioned 5th semiconductor region Form to property the 6th semiconductor region of the first conductive type.In above-mentioned 12nd process, in the inside of above-mentioned 4th semiconductor region, It is formed selectively the 7th semiconductor region of the impurity concentration the second conductive type higher than the impurity concentration of above-mentioned 4th semiconductor region. In above-mentioned 13rd process, formed with above-mentioned 4th semiconductor region positioned at above-mentioned 5th semiconductor region and the 6th semiconductor region Between region contact the second gate insulating film.In above-mentioned 14th process, across above-mentioned second gate insulating film and with it is upper It states the opposite side of the first semiconductor region and forms the second gate electrode.In above-mentioned 15th process, above-mentioned 5th semiconductor is spread Area and above-mentioned 7th semiconductor region, form second groove from the first interarea of above-mentioned semiconductor substrate at a predetermined depth.
In above-mentioned 16th process, in above-mentioned 6th semiconductor region, from the first interarea of above-mentioned semiconductor substrate with Scheduled depth forms third groove.In above-mentioned 17th process, third electrode is inserted in the inside of above-mentioned second groove.? In above-mentioned 18th process, the 4th electrode is inserted in the inside of above-mentioned third groove.The 19th process is also carried out, the 19th In process, in the inside of above-mentioned 4th semiconductor region, is separated with above-mentioned second element and be formed selectively the second conductive type 8th semiconductor region, above-mentioned 8th semiconductor region penetrate through above-mentioned 4th semiconductor region from the first interarea of above-mentioned semiconductor substrate and Above-mentioned semiconductor layer is reached, and the impurity concentration of above-mentioned 8th semiconductor region is higher than the impurity concentration of above-mentioned 4th semiconductor region. Above-mentioned 12nd process is carried out after above-mentioned 15th process.In above-mentioned 12nd process, by above-mentioned second groove Bottom surface carry out the ion implanting of the second conductive type impurity and form the bottom surface for covering above-mentioned second groove the above-mentioned 7th half leads Body area.
In addition, the manufacturing method of semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that simultaneously Carry out above-mentioned the second step, above-mentioned tenth process and above-mentioned 11st process.
In addition, the manufacturing method of semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that simultaneously Carry out above-mentioned 6th process and above-mentioned 15th process.
In addition, the manufacturing method of semiconductor device of the invention is on the basis of above-mentioned invention, which is characterized in that simultaneously Carry out above-mentioned 6th process, above-mentioned 15th process and above-mentioned 16th process.
It according to above-mentioned invention, can be by p++Type contact zone (the 7th semiconductor region) is configured at the front than semiconductor substrate Deeper position thus tends to absorb the avalanche current generated in circuit portion.The avalanche current generated in circuit portion as a result, The electric current of a part difficultly flow into the n of second element+Type source region (the 5th semiconductor region), it is difficult to occur in circuit portion parasitic Bipolar action.
Invention effect
The manufacturing method of semiconductor device and semiconductor device according to the present invention has master in the same semiconductor substrate In the semiconductor device of the circuit portion in circuit portion (deferent segment portion) and control the main circuit portion, the wave that can be improved circuit portion is played Tolerance is gushed, and can be improved the effect of the electrical characteristics in main circuit portion.
Detailed description of the invention
Fig. 1 is the sectional view for indicating the structure of semiconductor device of embodiment 1.
Fig. 2 is the top view for indicating the layout of the circuit portion of Fig. 1 from the face side of semiconductor substrate.
Fig. 3 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 4 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 5 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 6 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 7 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 8 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Fig. 9 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 1.
Figure 10 is the sectional view for indicating the construction of semiconductor device of embodiment 2.
Figure 11 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 2.
Figure 12 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 2.
Figure 13 is the sectional view for indicating the state of the manufacturing process of semiconductor device of embodiment 2.
Figure 14 is the vertical view for indicating the layout of the semiconductor device of embodiment 3 from the face side of semiconductor substrate Figure.
Figure 15 is the vertical view for indicating the layout of the semiconductor device of embodiment 4 from the face side of semiconductor substrate Figure.
Figure 16 is the top view for indicating the semiconductor device of embodiment 5 from the face side of semiconductor substrate.
Figure 17 is the sectional view for indicating the structure of existing semiconductor device.
Symbol description
1:n+Type initial substrate
2:n-Type semiconductor layer
2a:n-Type substrate regions
3: the gate groove of longitudinal type MOSFET
4: the gate insulating film of longitudinal type MOSFET
5: the gate electrode of longitudinal type MOSFET
6: longitudinal type MOSFET p-type base area
7: the n of longitudinal type MOSFET+Type source region
8,8': the p of longitudinal type MOSFET++Type contact zone
8a: the p of longitudinal type MOSFET+Type contact zone
9: interlayer dielectric
9a~9d: contact hole
10: the longitudinal type MOSFET of deferent segment
11: source electrode
11a, 11a': the contact trench of longitudinal type MOSFET
11b: the conductive film of longitudinal type MOSFET
11c: the metal wiring layer of longitudinal type MOSFET
12: the drain electrode of longitudinal type MOSFET
13: semiconductor substrate
20: the lateral type n-channel MOSFET of circuit portion
21: the p of lateral type n-channel MOSFET-Type well region
21a: the p of lateral type n-channel MOSFET-The central portion of type well region
22: the n of lateral type n-channel MOSFET+Type source region
23: the n of lateral type n-channel MOSFET+Type drain region
24,24', 81,81', 84: the p of lateral type n-channel MOSFET++Type contact zone
25: the gate insulating film of lateral type n-channel MOSFET
26: the gate electrode of lateral type n-channel MOSFET
27: the source electrode of lateral type n-channel MOSFET
27a, 27a', 28a, 82a, 83a, 83a', 85: the contact trench of lateral type n-channel MOSFET
27b, 28b, 82b, 83b: the conductive film of lateral type n-channel MOSFET
27c, 28c: the metal wiring layer of lateral type n-channel MOSFET
28: the drain electrode of lateral type n-channel MOSFET
29: the p of lateral type n-channel MOSFET+Type contact zone
30: the longitudinal type diode of surge protection
31: the p of longitudinal type diode+Type diffusion region
32: the p of longitudinal type diode++Type contact zone
33: the contact electrode of longitudinal type diode
33a: the contact trench of longitudinal type diode
33b: the conductive film of longitudinal type diode
33c: the metal wiring layer of longitudinal type diode
41: deferent segment portion
42: circuit portion
44: avalanche current
51~55: active area
61:LOCOS film
62,64,66,67,69~71: resist film
63,65,68,72: ion implanting
X: the n of lateral type n-channel MOSFET+Type source region and n+Type drain region side arranged side by side
To (first direction)
Y: the direction (second direction) orthogonal with first direction
Z: depth direction
D1:n+The depth in type drain region
D2: the depth of third contact trench
D10, d10', d20, d20', d30: the distance in active section
Specific embodiment
Hereinafter, the preferred implementation referring to attached drawing, to the manufacturing method of semiconductor device and semiconductor device of the invention Mode is described in detail.In the present description and drawings, the layer for prefix n or p or region, respectively refer to electronics or hole For majority carrier.In addition, marking in n or p+or-refer to that be comparably high impurity with the layer or region for not marking them dense Degree or low impurity concentration.It should be noted that in the description of the following embodiments and the accompanying drawings, being marked to identical composition identical Symbol, and the repetitive description thereof will be omitted.
(embodiment 1)
The structure of the semiconductor device of embodiment 1 is illustrated.Fig. 1 is the semiconductor device for indicating embodiment 1 Structure sectional view.The cross section structure of circuit portion 42 shown in FIG. 1 is the cross section structure at the cutting line A-A' of Fig. 2.In Fig. 1 One example of the semiconductor device as embodiment 1 and show the longitudinal type n-channel power MOSFET of deferent segment The vehicle-mounted high-end being arranged on the same semiconductor substrate (semiconductor chip) with the lateral type CMOS of control circuit Power IC.Diagram, which is omitted, in Fig. 1 is configured at interelement and the mutual LOCOS of separating element (Local Oxidation of Silicon (local oxidation of silicon): minor insulation) film etc. thick insulating film (Fig. 2,14~16 in also identical).
The semiconductor device of embodiment 1 shown in FIG. 1 has deferent segment portion 41 and circuit portion on semiconductor substrate 13 42.Semiconductor substrate 13 is to make n-2 epitaxial growth of type semiconductor layer is in n+Epitaxial substrate made of on the front of type initial substrate 1. Deferent segment portion 41 and circuit portion 42 configure separated from each other.Ground terminal (the GND of output terminal (OUT terminal) and low potential side Terminal) it is set to the front of semiconductor substrate 13.The power supply voltage terminal (Vcc terminal) of hot side is set to semiconductor substrate 13 back side.
In deferent segment portion 41, as the longitudinal type n-channel power MOSFET of deferent segment, such as configured with trench gate structure Longitudinal type MOSFET (first element) 10.The longitudinal type MOSFET 10 of the deferent segment has to have to be contacted with source electrode 11 The groove interface construction of groove (hereinafter referred to as the first contact trench (first groove)) 11a.Longitudinal direction is illustrated only in Fig. 1 A unit cell of type MOSFET 10, the multiple unit cells for being also possible to identical composition adjacently configure.
In deferent segment portion 41, n+Type initial substrate 1 and n-Longitudinal type of the type semiconductor layer 2 respectively as deferent segment The drain region and drift region of MOSFET 10 and function.In the face side (n of semiconductor substrate 13-Type semiconductor layer 2 it is opposite In n+1 side of type initial substrate is opposite side), it is provided with the mos gate structure of longitudinal type MOSFET 10.
The mos gate structure of longitudinal type MOSFET 10 is by groove (hereinafter referred to as gate groove) 3, the gate insulating film (first grid Insulating film) 4, gate electrode (first gate electrode) 5, p-type base area (the first semiconductor region) 6, n+Type source region (the second semiconductor region) 7 with And p++The trench gate structure that type contact zone (third semiconductor region) 8 is constituted.It starts from the front of semiconductor substrate 13 with scheduled Gate groove 3 is arranged in depth.Gate electrode 5 is arranged in the inside of gate groove 3 across gate insulating film 4.
P-type base area 6 is to start the depth setting more shallow than gate groove 3 from the front of semiconductor substrate 13.P-type base area 6 is in grid The side-walls of groove 3 are opposed with gate electrode 5 across gate insulating film 4.n+Type source region 7 and p++Type contact zone 8 is respectively selectively It is set to the inside of p-type base area 6.n+Type source region 7 is opposed with gate electrode 5 across gate insulating film 4 in the side-walls of gate groove 3.
p++Type contact zone 8 covers the bottom surface of the first contact trench 11a.p++Type contact zone 8 can also cover the first contact ditch The bottom surface corner of slot 11a.The bottom surface corner of first contact trench 11a refers to the side wall of the first contact trench 11a and the friendship of bottom surface Boundary.p++Type contact zone 8 preferably and n+Type source region 7 contacts.
The p++Spread p while there is the inner radiation shape from the bottom surface of the first contact trench 11a to p-type base area 6 in type contact zone 8 Roughly circular or substantially elliptical cross sectional shape made of type impurity.p++The depth ratio n of type contact zone 8+The depth of type source region 7 Degree is deep.p++Type contact zone 8 can also be configured at the position separated along depth direction Z from the front of semiconductor substrate 13.
Fig. 1 shows p++Type contact zone 8 and n+The situation low compared to impurity concentration of type source region 7.In this case, p++Type connects It touches area 8 and covers n+The end of first side contact trench 11a of type source region 7, extends to n+Lower surface (the n of type source region 7+The first primordium of type The end of 1 side of plate).Although not shown, it but can be in p in Fig. 1++The inside of type contact zone 8 is selectively provided with p+Type Contact zone 8a (referring to Fig. 9).In this case, by p+Type contact zone 8a and p++Type contact zone 8 covers the first contact trench 11a's Bottom surface.
In the front of semiconductor substrate 13, interlayer dielectric 9 is provided in a manner of covering grid electrode 5.In layer insulation Positive first contact hole 9a~the 4th contact hole 9d for selectively exposing semiconductor substrate 13 is respectively set in film 9.First Contact trench 11a compares n to start from the front of semiconductor substrate 13+The shallow depth of type source region 7 is set to semiconductor substrate 13 In the part that the first contact hole 9a exposes.The width of first contact trench 11a for example with the width substantially phase of the first contact hole 9a Together.
The bottom surface of first contact trench 11a is in n+Type source region 7 and p++The inside of type contact zone 8 terminates.Ditch is contacted first The side wall of slot 11a exposes n+Type source region 7.In the case where the unit cell of longitudinal type MOSFET 10 adjacently configures multiple, Exposing in the two sidewalls of the first contact trench 11a has n+Type source region 7.Exposing in the bottom surface of the first contact trench 11a has p++Type connects Touching area 8 (is being provided with p+It is p in the case where type contact zone 8a+Type contact zone 8a and p++Type contact zone 8).
In conductive films 11b such as the inside of the first contact trench 11a, such as filling tungsten (W) as source electrode (source terminal (first electrode)) 11.n+Type source region 7 and p++Type contact zone 8 via conductive film 11b and metal wiring layer 11c and and output terminal Electrical connection.In the back side (n of semiconductor substrate 13+The back side of type initial substrate 1), it is provided with the electric leakage of longitudinal type MOSFET 10 Pole (drain terminal (second electrode)) 12.The drain electrode 12 is, for example, the Vcc terminal for being connected with vehicle battery.
Circuit portion 42 is provided with each circuit such as control circuit.It is only illustrated in the circuit portion 42 of Fig. 1 and constitutes control circuit use Lateral type CMOS complementary connection lateral type p-channel MOSFET and lateral type n-channel MOSFET in lateral type n-channel MOSFET (second element) 20.The lateral type n-channel MOSFET 20 of control circuit has and has and 27 contact of source electrode Groove (hereinafter referred to as the second contact trench (second groove)) 27a and with the groove of the contact of drain electrode 28 (hereinafter, claiming For third contact trench (third groove)) groove interface construction of 28a.
For example, being selectively provided with p in the positive superficial layer of semiconductor substrate 13 in circuit portion 42-Type well region (the Four semiconductor regions) 21.p-The depth of type well region 21 for example can be than the p-type base area 6 of the longitudinal type MOSFET 10 of deferent segment Depth is deep.In p-The inside of type well region 21 is respectively selectively provided with the n of lateral type n-channel MOSFET 20+Type source region (the Five semiconductor regions) 22, n+Type drain region (the 6th semiconductor region) 23 and p++Type contact zone (the 7th semiconductor region) 24.
n+Type source region 22 and n+Type drain region 23 separates and configures.n+A side wall of the type source region 22 in the second contact trench 27a It is contacted with conductive film 27b.n+The entire bottom surface of the covering of type drain region 23 third contact trench 28a.n+The depth d1 in type drain region 23 is for example It can be 0.5 μm or more and 0.6 μm of degree below.In addition, n+Type source region 22 and n+The depth in type drain region 23 is for example also possible to With the n of longitudinal type MOSFET 10+The depth of type source region 7 is identical.
p++Type contact zone 24 is set to n+Type source region 22 relative to n+The opposite side in 23 side of type drain region.p++Type contact zone The bottom surface of 24 the second contact trench 27a of covering.p++Type contact zone 24 can cover always from the bottom surface of the second contact trench 27a Bottom surface corner.The bottom surface corner of second contact trench 27a refers to the side wall of the second contact trench 27a and the boundary of bottom surface.p++Type Contact zone 24 preferably and n+Type source region 22 contacts.
p++Type contact zone 24 has from the bottom surface of the second contact trench 27a to p-Spread to the inner radiation shape of type well region 21 Roughly circular or substantially elliptical cross sectional shape made of n-type impurity.p++The depth ratio n of type contact zone 24+Type source region 22 Depth it is deep.p++Type contact zone 24 can be configured at the position separated on depth direction Z from the front of semiconductor substrate 13.Figure P is shown in 1++Type contact zone 24 and n+The situation low compared to impurity concentration of type source region 22.In this case, p++Type contact zone 24 Cover n+The end of second side contact trench 27a of type source region 22, and extend to n+Lower surface (the n of type source region 22+The first primordium of type The end of 1 side of plate).
Furthermore it is possible in p-The inside of type well region 21, with the second contact trench 27a of covering relative to n+22 side of type source region The mode of the side wall of opposite side is selectively provided with p+Type contact zone (the 9th semiconductor region) 29.p+Type contact zone 29 is excellent It is selected as and p++Type contact zone 24 contacts.The reason for this is that be capable of forming for make the inside of the second contact trench 27a conductive film 27b not With high-resistance p-The composition that type well region 21 contacts.
In p-Type well region 21 is sandwiched in n+Type source region 22 and n+On the surface of part between type drain region 23, across gate insulation Film (the second gate insulating film) 25 and be provided with gate electrode (the second gate electrode) 26.
In addition, in p-Type well region 21 is provided with and penetrates through p on depth direction Z-Type well region 21 and reach n-Type substrate regions The p of (the first conductive type layer) 2a+Type diffusion region (the 8th semiconductor region) 31.n-Type substrate regions 2a is n-Type semiconductor layer 2 is not Form p-Type well region 21 etc. and directly with the original remaining part of conductivity type and impurity concentration.Depth direction Z refers to from partly leading Structure base board 13 just facing towards the direction at the back side.That is, p+The depth of type diffusion region 31 is p-It is more than the depth of type well region 21.
p+The n of type diffusion region 31 and lateral type n-channel MOSFET 20+Type source region 22, n+Type drain region 23 and p++Type contact Area 24 separates and is arranged.In addition, p+Type diffusion region 31 is for example in p-Near the periphery of type well region 21, such as along p-Type well region 21 Periphery and be arranged, and surround p-Central portion (the p of type well region 21-The ratio p of type well region 21+Type diffusion region 31 is closer to inside portion Point) around 21a.Multiple unit cells of lateral type n-channel MOSFET 20 can also be adjacently configured at p-Type well region 21 Central portion 21a.
p+Type diffusion region 31 as prevent because on the front for being laminated in semiconductor substrate 13 metal wiring layer 27c, 28c, P caused by the current potential of 33c-The reversion of the reversion of type well region 21 prevents layer from functioning.In addition, p+Type diffusion region 31 is used as and prevents Lateral type n-channel MOSFET 20 is functioned from adjacent other devices by the protection ring of the influences such as noise.In addition, in p+Type diffusion region 31 and n-Pn-junction between type substrate regions 2a is formed with the longitudinal type diode 30 of surge protection.
In p+The inside of type diffusion region 31, is selectively provided with p++Type contact zone 32.p++Type contact zone 32 is covered and is connect The bottom surface of groove (hereinafter referred to as the 4th contact trench) 33a of the contact of the contact electrode 33 of ground potential.p++Type contact zone 32 The bottom surface corner of the 4th contact trench 33a can be covered.The bottom surface corner of 4th contact trench 33a refers to the 4th contact trench The side wall of 33a and the boundary of bottom surface.
p++Type contact zone 32 has from the bottom surface of the 4th contact trench 33a to p+Expand to the inner radiation shape of type diffusion region 31 Dissipate roughly circular or substantially elliptical cross sectional shape made of n-type impurity.p++The depth of type contact zone 32 for example can also be with With the p of longitudinal type MOSFET 10++The p of type contact zone 8 and/or lateral type n-channel MOSFET 20++The depth of type contact zone 24 It is identical.
Second contact trench 27a compares n to start from the front of semiconductor substrate 13+The shallow depth of type source region 22 is set to half The part in the second contact hole 9b exposing of conductor substrate 13.The bottom surface of second contact trench 27a is in n+Type source region 22, p++Type connects Touch area 24 and p+The inside of type contact zone 29 terminates.Width of the width of second contact trench 27a for example with the second contact hole 9b It spends roughly the same.
Exposing in the bottom surface of the second contact trench 27a has p++Type contact zone 24.In a side wall of the second contact trench 27a Exposing has n+Type source region 22 has p in the exposing of another side wall+Type contact zone 29.It is being not provided with p+The case where type contact zone 29 Under, there is p in another side wall exposing of the second contact trench 27a-Type well region 21.
In the inside of the second contact trench 27a, such as the conductive films 27b such as filling tungsten is as source electrode (source terminal (the Three electrodes)) 27.n+Type source region 22 and p++Type contact zone 24 is electrically connected via conductive film 27b and metal wiring layer 27c with GND terminal It connects.
Third contact trench 28a is set to semiconductor to start from the front of semiconductor substrate 13 as scheduled depth d2 The part in third contact hole 9c exposing of substrate 13.The depth d2 of third contact trench 28a for example can be with the second contact ditch The depth of slot 27a is identical, specifically, for example may be 0.2 μm or less and 0.3 μm or more of degree.Third contact trench The bottom surface of 28a is in n+The inside in type drain region 23 terminates.
That is, third contact trench 28a is completely by n+Type drain region 23 covers, and passes through n+Type drain region 23 makes drain electrode 28 and p-Type Well region 21 separates.If third contact trench 28a penetrates through n+Type drain region 23 and reach p as backgate-Type well region 21, then laterally Type n-channel MOSFET 20 is functioned not as MOSFET, thus not preferred.
The width of third contact trench 28a is for example roughly the same with the width of third contact hole 9c.In third contact trench The conductive film 28b of the inside of 28a, such as filling tungsten etc. is as drain electrode (drain terminal (the 4th electrode)) 28.n+Type drain region 23, via conductive film 28b and metal wiring layer 28c, are electrically connected with terminal more higher than 27 current potential of source electrode.
4th contact trench 33a is set to semiconductor-based with starting from the front of semiconductor substrate 13 as scheduled depth The part in the 4th contact hole 9d exposing of plate 13.The depth of 4th contact trench 33a for example can also be with the second contact trench The depth of 27a is identical.The bottom surface of 4th contact trench 33a is in p++The inside of type contact zone 32 terminates, in the 4th contact trench 33a Bottom surface expose p++Type contact zone 32.
The width of 4th contact trench 33a is for example roughly the same with the width of the 4th contact hole 9d.In the 4th contact trench The inside of 33a, such as the conductive film 33b of filling tungsten etc. is as the contact electrode 33 of earthing potential.P as backgate-Type trap Area 21 is via p+Type diffusion region 31, p++Type contact zone 32, conductive film 33b and metal wiring layer 33c are electrically connected with GND terminal.
Next, to the layout from the face side of the flat shape of each section of circuit portion 42 and semiconductor substrate into Row explanation.Fig. 2 is the top view for indicating the layout of the circuit portion of Fig. 1 from the face side of semiconductor substrate.As shown in Fig. 2, P as backgate-Type well region 21 is for example with substantially rectangular flat shape.In p-Type well region 21 is provided with lateral type n-channel The active area of the longitudinal type diode 30 of the active area (hereinafter referred to as the first active area) 51 and surge protection of MOSFET 20 (hereinafter referred to as the second active area) 52.
First active area 51 is the region for having principal current to circulate in the on state of lateral type n-channel MOSFET 20.The One active area 51 configures the central portion in semiconductor substrate 13 for example with substantially rectangular flat shape.Second active area 52 and One active area 51 is separated and is configured, and is surrounded around the first active area 51 substantially rectangularly.In the second active area 52, configured with wave Gush the longitudinal type diode 30 of protection.
The distance between first active area 51 and the second active area 52 d10 be with machining accuracy limitation LOCOS film most It more than few residual dimension, and can reduce to the p for surrounding the second active area 52+Type diffusion region 31 does not enter the first active area 51 In the part covered by gate electrode 26 inside degree distance.The first active area is shown with most thin dotted line in Fig. 2 51 wheel Guo (the first active area, the third active area of Figure 14, Figure 15 of Figure 14~16 are also identical).Second active area 52 is and table Show region (the second active area of Figure 14~16 between dotted line identical thin dotted line 52a, 52b of the wheel Guo of the first active area 51 Also identical).
Specifically, in the first active area 51, the n configured with lateral type n-channel MOSFET 20+Type source region 22, n+Type leakage Area 23 and p++Type contact zone 24.First active area 51 has the whole units that can configure lateral type n-channel MOSFET 20 Unit and surface area for example substantially rectangular flat shape as small as possible.n+Type source region 22, n+Type drain region 23 and p++Type connects Touching area 24 has for example substantially rectangular flat shape.n+The surface area in type drain region 23 can for example compare n+The surface of type source region 22 Product is big.
In n+Type source region 22 and n+Between type drain region 23, such as gate electrode 26 is provided with substantially rectangular flat shape.p++Type contact zone 24 as described above with n+Type source region 22 is placed in contact in n+Type source region 22 relative to n+23 side phase of type drain region Anti- side.p++Type contact zone 24 is terminated in the inside of the first active area 51, does not extend to the outside (p of the first active area 51+ 31 side of type diffusion region).p++The surface area of type contact zone 24 can for example compare n+The surface area of type source region 22 is small.
These n+Type source region 22, n+Type drain region 23, p++Type contact zone 24 and gate electrode 26 be configured to for example with n+Type source Area 22 and n+The direction arranged side by side of type drain region 23 (hereinafter referred to as first direction) X orthogonal direction (hereinafter referred to as second direction) Y What is linearly extended is band-like.Second contact trench 27a, third contact trench 28a are for example with substantially rectangular flat shape. Second contact trench 27a is configured to across n+Type source region 22 and p++Type contact zone 24.Third contact trench 28a is configured at n+Type leakage Area 23.
In the second active area 52, the p configured with the longitudinal type diode 30 for constituting surge protection+Type diffusion region 31 and p++ Type contact zone 32.Second active area 52 divides across the thick insulating film for illustrating LOCOS film omitted etc. with the first active area 51 It opens.That is, being provided with LOCOS film in the front of semiconductor substrate 13 between the first active area 51 and the second active area 52.
p+Layout configuration of the type diffusion region 31 for example to surround around lateral type n-channel MOSFET 20 substantially rectangularly In p-Type well region 21.p+Type diffusion region 31 can throughout than the second active area 52 closer to the position of inside (51 side of the first active area) It sets and/or compares the second active area 52 closer to the position of outside (end surface side of semiconductor substrate 13).p++Type contact zone 32 is for example P is set to the layout surrounded around the first active area 51+Type diffusion region 31.4th contact trench 33a is along p++Type contact Area 32 is with rectangular arrangement in the p++Type contact zone 32, and surround around the first active area 51.
For the layout in the deferent segment portion 41 of Fig. 1 from the face side of semiconductor substrate, the illustration is omitted, but is configured at The n of the longitudinal type MOSFET 10 of the deferent segment in deferent segment portion 41+Type source region 7, p++Type contact zone 8 and the first contact trench 11a's is laid out the n with the lateral type n-channel MOSFET 20 for the control circuit for being for example configured at circuit portion 42 respectively+Type source region 22, p++Type contact zone 24 and the second contact trench 27a are identical.
Next, the manufacturing method of the semiconductor device for embodiment 1, illustrates in longitudinal type MOSFET 10 P is respectively set with lateral type n-channel MOSFET 20+The case where type contact zone 8a, 29.Fig. 3~9 are indicate embodiment 1 half The sectional view of the state of the manufacturing process of conductor device.The circuit portion 42 for being configured at Fig. 1 is schematically shown in Fig. 3~Fig. 9 (a) Control circuit lateral type n-channel MOSFET 20, schematically show the deferent segment portion 41 for being configured at Fig. 1 in Fig. 9 (b) Deferent segment longitudinal type MOSFET 10 (also identical in Figure 10~13).
In Fig. 3~9, p is omitted in diagram+Type diffusion region 31, p++It type contact zone 32, the 4th contact trench 33a and leads Electrolemma 33b, but p+Type diffusion region 31 is for example in p-After the formation of type well region 21 and in p++Until before the formation of type contact zone 32 It is formed by ion implanting.p++Type contact zone 32, the 4th contact trench 33a and conductive film 33b respectively with lateral type n The p of channel mosfet 20++Type contact zone 24, the second contact trench 27a and conductive film 27b are formed simultaneously.
Firstly, by making n-2 epitaxial growth of type semiconductor layer is in n+The front of type initial substrate 1 and semiconductor substrate is made (semiconductor crystal wafer) 13 (referring to Fig.1).Next, as shown in figure 3, by photoetching and ion implanting, in deferent segment portion 41, in n- The superficial layer of type semiconductor layer 2 is formed selectively p-type base area 6.In addition, by photoetching and ion implanting, in circuit portion 42, n-The superficial layer of type semiconductor layer 2 is formed selectively the p as backgate-Type well region 21.
Next, for example by surround p-Mode around type well region 21 forms the thick insulation of LOCOS film 61 etc. Film makes circuit portion 42 and p-Part (such as deferent segment portion 41) other than the circuit portion 42 of type well region 21 separates.Next, defeated Section portion 41 out forms the gate groove 3 for penetrating through p-type base area 6 on depth direction Z from the front of semiconductor substrate 13, in the grid The inside of groove 3 forms gate electrode 5 across gate insulating film 4.
In addition, in circuit portion 42, in p-The surface of type well region 21 forms gate electrode 26 across gate insulating film 25.Gate insulation Film 4,25 can be formed simultaneously, such as be also possible to form the inner wall thermal oxide of the surface of semiconductor substrate 13 and gate groove 3 Silica (SiO2) film.Gate electrode 5,26 can be formed simultaneously, for example, can also will become gate insulating film 4,25 oxidation Polysilicon (poly-Si) layer accumulated on film is patterned in a manner of only remaining in predetermined position and is formed.It should be noted that P-type base area 6 can also be formed after forming gate groove 3, gate insulating film 4 and gate electrode 5.
Next, as shown in figure 4, forming the n with longitudinal type MOSFET10 in the front of semiconductor substrate 13+Type source region 7, the n of lateral type n-channel MOSFET 20+Type source region 22 and n+The corresponding outs open of the forming region in type drain region 23 it is against corrosion Agent film 62.At this point, that exposes gate electrode 26 is sandwiched in n in the opening portion of resist film 62+The forming region and n of type source region 22+Type Part between the forming region in drain region 23.Also, in the opening portion of resist film 62, that exposes gate groove 3 is sandwiched in adjacent n+Part between type source region 7.
Next, using resist film 62, LOCOS film 61 and gate electrode 5,26 as mask and to p-type impurity carry out from Son injection 63.As a result, in deferent segment portion 41, semiconductor substrate 13 positive superficial layer with 3 autoregistration landform of gate groove At the n for having longitudinal type MOSFET 10+Type source region 7.Also, in circuit portion 42, in the positive superficial layer of semiconductor substrate 13, The n of lateral type n-channel MOSFET 20 is formed self-aligned with gate electrode 26+Type source region 22 and n+Type drain region 23.
Next, as shown in figure 5, in the front of semiconductor substrate 13, being formed and vertical after eliminating resist film 62 To each p of type MOSFET 10 and lateral type n-channel MOSFET 20+Type contact zone 8a, 29 the corresponding portion of forming region separate Mouthful resist film 64.Next, carried out and by resist film 64 and LOCOS film 61 as mask n-type impurity from Son injection 65, is formed selectively p in the positive superficial layer of semiconductor substrate 13+Type contact zone 8a, 29.
Next, as shown in fig. 6, after eliminating resist film 64, in the front of semiconductor substrate 13, with cover grid The mode of electrode 5,26 forms interlayer dielectric 9.Next, being formed on the surface of interlayer dielectric 9 with contact hole 9a~9c's The resist film 66 of forming region corresponding outs open.Next, being lost and using resist film 66 as mask It carves, so that interlayer dielectric 9 be selectively removed, forms the first contact hole for penetrating through interlayer dielectric 9 on depth direction Z 9a~third contact hole 9c.
Next, as shown in fig. 7, by after eliminating resist film 66, using interlayer dielectric 9 as mask into Row etching, to distinguish shape in the part that the first contact hole 9a~third contact hole 9c exposes in the positive of semiconductor substrate 13 At the first contact trench 11a, the second contact trench 27a, third contact trench 28a.At this point, third contact trench 28a is than n+ The shallow depth d2 in type drain region 23 is formed, and makes its bottom surface in n+The inside in type drain region 23 terminates.In addition, third contact trench 28a is whole Body is by n+Type drain region 23 covers.
By the depth d2 ratio n for making third contact trench 28a+The depth d1 in type drain region 23 is shallow, and makes the first contact ditch The depth of slot 11a is formed as comparing n+Type source region 7 and p+The depth as shallow of type contact zone 8a, so that third contact trench 28a and first connects The bottom surface for touching groove 11a is terminated in the inside in these regions.Also, the second contact trench 27a is than n+Type source region 22 and p+Type connects The shallow depth in touching area 29 is formed, and the bottom surface of the second contact trench 27a is terminated in the inside in these regions.
Next, as shown in figure 8, inserting resist film 67 in third contact trench 28a and being covered using the resist film 67 Lid third contact trench 28a.By resist film 67, covers the positive of semiconductor substrate 13 and reveal in third contact trench 28a Part (n out+Type drain region 23).In the opening portion of resist film 67, exposing has the positive of semiconductor substrate 13 to connect first Touch the part (n that groove 11a, the second contact trench 27a expose+7,22 and p of type source region+Type contact zone 8a, 29).
Next, using resist film 67 and interlayer dielectric 9 as mask, in the first contact trench 11a, the second contact ditch The bottom surface of slot 27a carries out the ion implanting 68 of n-type impurity.As a result, than n+Type source region 7 and p+The type contact zone deeper position 8a Set, with n+Type source region 7 and p+The mode of type contact zone 8a contact forms the p of the bottom surface of the first contact trench 11a of covering++Type connects Touch area 8.Than n+Type source region 22 and p+The deeper position in type contact zone 29, with n+Type source region 22 and p+Type contact zone 29 contacts Mode be formed with covering the second contact trench 27a bottom surface p++Type contact zone 24.
P is formed to the ion implanting 68 of the second bottom surface contact trench 27a by utilizing++Type contact zone 24, so as to P is formed in position deeper from the front of semiconductor substrate 13++Type contact zone 24.Thereby, it is possible to improve as described later to To p when Vcc terminal application surge voltage-The absorbability for the avalanche current 44 (referring to Fig.1) that type well region 21 extends.Therefore, energy Enough improve the surge tolerance of circuit portion 42.
By to the first contact trench 11a, the second contact trench 27a, the 4th bottom surface contact trench 33a ion implanting 68 And form p++Type contact zone 8,24,32, thus in the first contact trench 11a, the second contact trench 27a, the 4th contact trench 33a Bottom surface or from the first contact trench 11a, the second contact trench 27a, the 4th contact trench 33a bottom surface towards semiconductor substrate The p at 13 back side++In type contact zone 8,24,32, there are p++The impurity concentration of type contact zone 8,24 becomes maximum position.p++ The impurity concentration of type contact zone 8,24,32 becomes acceleration voltage of the maximum position by ion implanting 68 when and determines.
In addition, the first contact trench 11a and p of the longitudinal type MOSFET 10 of deferent segment++Type contact zone 8 by with control The second contact trench 27a and p of the lateral type n-channel MOSFET 20 of circuit++(groove connects the identical structure in type contact zone 24 Touching construction) it is formed, but the electrical characteristics of longitudinal type MOSFET 10 are had no adverse effect.That is, the lateral type n ditch of control circuit The groove interface construction of road MOSFET 20 is also applied for the longitudinal type MOSFET 10 of deferent segment.
Next, as shown in figure 9, contacting ditch in the first contact trench 11a, second after eliminating resist film 67 Slot 27a, third contact trench 28a inside be respectively filled in conductive film 11b, 27b, 28b.Next, in semiconductor substrate 13 Front forms metal wiring layer 11c, 27c, the 28c contacted respectively with conductive film 11b, 27b, 28b.In semiconductor substrate 13 The back side forms drain electrode 12.Later, singualtion and semiconductor crystal wafer is cut into each shaped like chips, thus shown in FIG. 1 Semiconductor device is completed.
Next, the movement of the semiconductor device for embodiment 1, is illustrated referring to Fig.1.If because from the end Vcc The surge voltage of son intrusion causes the voltage between Vcc terminal and GND terminal to rise and to the application voltage of the application of circuit portion 42 Rise, is then configured at p-The longitudinal type diode 30 of the near the perimeter of surge protection of type well region 21 is in p+Type diffusion region 31 with n-Pn-junction breakdown between type substrate regions 2a, in p+Bottom (the n of type diffusion region 31+The end of 1 side of type initial substrate) generate electricity Flow (avalanche current (hole current)) 44.If increased in the avalanche current 44 that circuit portion 42 circulates, the one of avalanche current 44 Partial current expansion is to p-Type well region 21 and circulate.Utilize the p of the bottom of the second contact trench 27a of covering++Type contact zone 24, Make the electric current of a part of the avalanche current 44 compared with existing structure (Figure 17), deeper from the front of semiconductor substrate 13 Position to outside attract.Therefore, avalanche current 44 is inhibited to flow into the n of lateral type n-channel MOSFET 20+Type source region 22.It is tied Fruit is, with n+Type source region 22 is used as emitter, with p-Type well region 21 is used as base stage, with n-Type substrate regions 2a is as collector Parasitic bipolar element 43, which is not susceptible to jump, to be led to, and the surge tolerance between Vcc terminal and GND terminal is thus improved.
More than, as explained above, according to embodiment 1, in the p for being configured at circuit portion-Type well region is used in surge protection Longitudinal type diode surround around circuit lateral type n-channel MOSFET in, be formed with and the contact of source electrode Contact hole forms contact trench (the second contact trench), forms source electrode and n in the inner wall of second contact trench+Type source region with And p++The contact of type contact zone.Also, in the p++Type contact zone covers the bottom surface of the second contact trench.Thereby, it is possible to by p++Type Contact zone is configured at position more deeper than the front of semiconductor substrate, thus tends to absorb the avalanche current generated in circuit portion. The electric current of a part of the avalanche current generated as a result, in circuit portion is not easy to flow into the n of the lateral type n-channel MOSFET of circuit+Type source region is not likely to produce parasitic bipolar action in circuit portion.Therefore, it can be improved the surge tolerance of Power IC entirety.
In addition, forming contact of the electrode film with semiconductor portion, energy by the inner wall in contact trench according to embodiment 1 Unit cell is enough reduced, thus, it is possible to carry out the miniaturization of semiconductor device entirety.In addition, according to embodiment 1, it can be defeated The lateral type n-channel MOSFET of the longitudinal type MOSFET and circuit of section are formed simultaneously the same terms using same processes out Each section (conductivity type, the identical diffusion region of impurity concentration and diffusion depth and/or each contact trench), thus, it is possible to inhibit The increase of manufacturing cost.In addition, can be used and circuit in the longitudinal type MOSFET of deferent segment according to embodiment 1 The identical groove interface construction of lateral type n-channel MOSFET.That is, in the longitudinal type MOSFET of deferent segment, also in contact trench The inner wall of (the first contact trench) forms source electrode and n+Type source region and p++The contact of type contact zone.Thereby, it is possible to reduce output The conducting resistance of the longitudinal type MOSFET of section.
(embodiment 2)
Next, being illustrated to the structure of the semiconductor device of embodiment 2.Figure 10 is indicate embodiment 2 half The sectional view of the structure of conductor device.The difference of the semiconductor device of the semiconductor device and embodiment 1 of embodiment 2 exists In, the first contact trench 11a', the second contact trench 27a' depth respectively than longitudinal type MOSFET 10 and lateral type n-channel Each n of MOSFET 20+The depth of type source region 7,22 is deep.
In longitudinal type MOSFET 10, p++Type contact zone 8' covers the slave n of the first contact trench 11a'+Type source region 7 is to n+Type 1 side of initial substrate entire part outstanding.p++Type contact zone 8' preferably and n+Type source region 7 contacts.
In lateral type n-channel MOSFET 20, p++Type contact zone 24' covers the slave n of the second contact trench 27a'+Type source region 22 and p+Type contact zone 29 is to n+1 side of type initial substrate entire part outstanding.p++Type contact zone 24' preferably and n+Type source region 22 and p+Type contact zone 29 contacts.
First contact trench 11a', the second contact trench 27a' depth can arrive deeply and make p++8', 24' can not for type contact zone Reach n-The degree of type substrate regions 2a.
The manufacturing method of the semiconductor device of embodiment 2, will in the manufacturing method of the semiconductor device of embodiment 1 First contact trench 11a', the second contact trench 27a' are formed using the process different from third contact trench 28a.At this point, Make the depth of the first contact trench 11a', the second contact trench 27a' than third contact trench 28a depth.Specifically, real The manufacturing method for applying the semiconductor device of mode 2 is as described later.Figure 11~13 are the systems for indicating the semiconductor device of embodiment 2 Make the sectional view of the state of process.
Firstly, successively carrying out forming p-type base from semiconductor substrate (semiconductor crystal wafer) 13 in the same manner as embodiment 1 Area 6 and p-Type well region 21 arrive interlayer dielectric 9 formed the first contact hole 9a~third contact hole 9c process (referring to Fig. 3~ 6).It should be noted that p can not also be formed+Type contact zone 8a.In this case, the opening portion of resist film 64 is only formed in Fig. 5 In circuit portion 42.
Next, as shown in figure 11, after eliminating resist film 66, inserting resist film 69 in third contact hole 9c And utilize the positive part (n exposed in third contact hole 9c of the resist film 69 covering semiconductor substrate 13+Type drain region 23).In the opening portion of resist film 69, expose the positive in the first contact hole 9a, the second contact hole 9b of semiconductor substrate 13 Part (the n of exposing+7,22 and p of type source region+Type contact zone 8a, 29).
Next, by being etched using resist film 69 and interlayer dielectric 9 as mask, in semiconductor substrate 13 It is positive to be respectively formed the first contact trench 11a', the second contact in the part that the first contact hole 9a, the second contact hole 9b expose Groove 27a'.At this point, the first contact trench 11a', the second contact trench 27a' are respectively formed to compare n+Type source region 7,22 is deep, N is penetrated through on depth direction Z+Type source region 7,22, makes its bottom surface in p-type base area 6, p-The inside of type well region 21 terminates.In the first contact When groove 11a', the second contact trench 27a' formation, in the part for the opening portion for being exposed to resist film 69, interlayer dielectric 9 Also it is etched, in the part being etched, the thickness of interlayer dielectric 9 is thinning.
Next, as shown in figure 12, after eliminating resist film 69, in the first contact hole 9a, the second contact hole 9b And the first contact trench 11a', the second contact trench 27a' filling resist film 70 and partly led using the resist film 70 covering Positive part (the n exposed in the first contact hole 9a, the second contact hole 9b of structure base board 13+7,22 and p of type source region+Type contact Area 8a, 29).In the opening portion of resist film 70, expose the positive in the portion that third contact hole 9c exposes of semiconductor substrate 13 Point.
Next, by being etched using resist film 70 and interlayer dielectric 9 as mask, thus in semiconductor substrate The 13 positive part in third contact hole 9c exposing, is identically formed third contact trench 28a with embodiment 1.That is, the Three contact trench 28a are than n+The shallow depth d2 in type drain region 23 is formed, and makes its bottom surface in n+The inside in type drain region 23 terminates.? When the formation of three contact trench 28a, in the part that the opening portion of resist film 70 is exposed, interlayer dielectric 9 is also etched, at this The thickness of the part being etched, interlayer dielectric 9 is thinning.Can change third contact trench 28a and the first contact trench 11a', The formation sequence of second contact trench 27a'.
Next, as shown in figure 13, after eliminating resist film 70, inserting resist in third contact trench 28a Film 71 and utilize the resist film 71 cover third contact trench 28a.Semiconductor substrate 13 is being covered just using resist film 71 Part (the n exposed in third contact trench 28a in face+Type drain region 23).In the opening portion of resist film 71, expose semiconductor-based Positive part (the n exposed in the first contact trench 11a', the second contact trench 27a' of plate 13+7,22 and p of type source region+Type Contact zone 8a, 29).
Next, using resist film 71 and interlayer dielectric 9 as mask, in the first contact trench 11a', the second contact The bottom surface of groove 27a' carries out the ion implanting 72 of n-type impurity.Comparing embodiment party from the front start of calculation of semiconductor substrate 13 as a result, The deep position of formula 1 forms the p of the bottom surface of the first contact trench 11a' of covering++Type contact zone 8'.From semiconductor substrate 13 just The position deeper than embodiment 1 is started in face, forms the p of the bottom surface of the second contact trench 27a' of covering++Type contact zone 24'.p++Type Contact zone 8', 24' preferably respectively with n+Type source region 7,22 contacts.
Next, after eliminating resist film 71, in the same manner as embodiment 1, in the first contact trench 11a', Two contact trench 27a', third contact trench 28a inside be respectively filled in conductive film 11b, 27b, 28b.Later, with embodiment 1 likewise by the formation subsequent process for successively carrying out metal wiring layer 11c, 27c, 28c, thus semiconductor shown in Fig. 10 Device is completed.
In Figure 11~13, although p is omitted in diagram+Type diffusion region 31, p++Type contact zone 32, the 4th contact trench 33a with And conductive film 33b, but p+Type diffusion region 31 is for example in p-After type well region 21 is formed and in p++Benefit before type contact zone 32 is formed It is formed with ion implanting.p++Type contact zone 32, the 4th contact trench 33a and conductive film 33b respectively with lateral type n-channel The p of MOSFET 20++Type contact zone 24', the second contact trench 27a' and conductive film 27b are formed simultaneously.
More than, as explained above, according to embodiment 2, effect same as embodiment 1 can be obtained.In addition, root According to embodiment 2, by making the second contact trench be formed as the n of the lateral type n-channel MOSFET than control circuit+Type source region Depth it is deep, can be improved the absorbability of the electric current (surge current (i.e. avalanche current)) because of surge voltage circulation.
(embodiment 3)
The structure of the semiconductor device of embodiment 3 is illustrated.Figure 14 is the face side indicated from semiconductor substrate Observe the top view of the layout of the semiconductor device of embodiment 3.It is shown in Figure 14 from the face side of semiconductor substrate 13 and is seen Examine the layout of circuit portion 42.The semiconductor device of the semiconductor device and embodiment 1 of embodiment 3 the difference lies in that generation For the p of lateral type n-channel MOSFET 20++Type contact zone 24 and p is set++Type contact zone 81.The p++Type contact zone 81 and n+Type Source region 22 is separated and is configured.
p++Type contact zone 81 is configured at n in the same manner as embodiment 1+Type source region 22 relative to n+23 side of type drain region is opposite Side.The n of lateral type n-channel MOSFET 20+Type source region 22, n+Type drain region 23, p++Type contact zone 81 and gate electrode 26 It is such as configured to extend in the same direction of the frontoparallel with semiconductor substrate 13 band-like.
In n+Type source region 22, n+Type drain region 23 and p++Type contact zone 81 is each configured with the second contact trench 82a, Three contact trench 28a, the 5th contact trench 83a.The inside of third contact trench 28a and filling third contact trench 28a The composition of conductive film 28b is identical as embodiment 1.
Second contact trench 82a has substantially rectangular flat shape.Second contact trench 82a is only configured at n+Type source region 22, the second contact trench 82a is whole by n+Type source region 22 covers.The cross section structure of second contact trench 82a for example with only formed In n+The third contact trench 28a identical (referring to Fig.1, Fig. 2) in type drain region 23.
5th contact trench 83a is for example with the flat shape of rectangle.The bottom surface of 5th contact trench 83a is by p++Type contact Area 81 covers.p++Type contact zone 81 can cover always bottom surface corner from the bottom surface of the 5th contact trench 83a.As needed, Can with p++The p that the mode that type contact zone 81 contacts will illustrate in embodiment 1+Type contact zone 29 is to cover the 5th contact ditch The mode of the side of slot 83a is configured at around the 5th contact trench 83a.The cross section structure of 5th contact trench 83a and implementation Second contact trench 27a (referring to Fig.1, Fig. 2) of mode 1 is identical.
In the inside of the second contact trench 82a, the 5th contact trench 83a, it is respectively filled in conductive film 82b, 83b.It is conductive Film 82b, 83b are electrically connected via metal wiring layer with GND terminal.In the active area of lateral type n-channel MOSFET 20, (first has Source region) 53, it is configured with n+Type source region 22, n+Type drain region 23 and gate electrode 26.
It is configured with the active area (hereinafter referred to as third active area) 54 and the first active area 53, of the 5th contact trench 83a Two active areas 52 are separated and are configured.The distance between third active area 54 and the first active area 53 d20 can be reduced to processing The minimum residual dimension of the LOCOS film of precision limitation.The most short distance of the first direction X of third active area 54 and the second active area 52 It is the minimum residual dimension of the LOCOS film limited with machining accuracy or more from d30, and can reduces to surrounding the second active area 52 p+Type diffusion region 31 does not enter the distance of the degree of the inside of the part covered by gate electrode 26 in the first active area 53.
The p of the longitudinal type diode 30 of surge protection+Type diffusion region 31, p++Type contact zone 32, the 4th contact trench 33a And the composition of conductive film 33b is identical as embodiment 1.
Embodiment 3 can be applied to embodiment 2.
More than, as explained above, according to embodiment 3, it can obtain and embodiment 1,2 identical effects.In addition, According to embodiment 3, by with n+Type source region separates and configures the p of the lateral type n-channel MOSFET of control circuit++Type contact Area inhibits in manufacturing process from p++Type contact zone is to n+The inside diffused p-type impurity of type source region.Thus, for example in p++Type connects Touch the impurity concentration ratio n in area+In the case that the impurity concentration of type source region is high, it is able to suppress n+Type source region disappears.
(embodiment 4)
The structure of the semiconductor device of embodiment 4 is illustrated.Figure 15 is the face side indicated from semiconductor substrate Observe the top view of the layout of the semiconductor device of embodiment 4.It is shown in Figure 15 from the face side of semiconductor substrate 13 and is seen Examine the layout of circuit portion 42.The semiconductor device of embodiment 4 is with the semiconductor device of embodiment 3 the difference lies in that making The p of lateral type n-channel MOSFET 20++The type contact zone 81' and p functioned as protection ring+The inside of type diffusion region 31 p++Type contact zone 32 links.
p++Type contact zone 81' for example linearly extends in second direction Y and is attached to p++Type contact zone 32 and p++ 1 group of type contact zone 81' orthogonal opposite side.5th contact trench 83a' with p++Type contact zone 81' parallel linear layout Configuration, and it is attached to the 4th contact trench 33a.
The bottom surface of 5th contact trench 83a' is by p++Type contact zone 81' covering.p++Type contact zone 81' can connect from the 5th The bottom surface of touching groove 83a' covers always bottom surface corner.The of the cross section structure of 5th contact trench 83a' and embodiment 1 Two contact trench 27a (referring to Fig.1,2) are identical.As needed, can with p++The mode of type contact zone 81' contact is by embodiment party The p illustrated in formula 1+Type contact zone 29 is configured to two sides of the second direction Y-direction of the 5th contact trench 83a' of covering.
Active area (third active area) 54' for being configured with the 5th contact trench 83a' is attached to the second active area 52.Third The distance between active area 54' and the first active area 53 d20' can reduce minimum to the LOCOS film limited with machining accuracy Residual dimension.
Embodiment 4 can be applied to embodiment 2.
More than, as explained above, according to embodiment 4, effect identical with Embodiments 1 to 3 can be obtained.Separately Outside, according to embodiment 4, the p of the lateral type n-channel MOSFET by configuring control circuit with linear flat shape++ Type contact zone, so as to not increase p++In the case where the width of the first direction of type contact zone, increase the p++Type contact zone Surface area.Therefore, surge tolerance can be further increased.In addition, according to embodiment 4, due to p++The first of type contact zone The width in direction does not increase, so the p in manufacturing process++The diffusion to first direction of type contact zone is suppressed.As a result, can Enough shorten the distance between the first active area and third active area, can be realized the miniaturization of chip.
(embodiment 5)
The structure of the semiconductor device of embodiment 5 is illustrated.Figure 16 is from the face side of semiconductor substrate The top view of the layout of the semiconductor device of embodiment 5.It is shown in Figure 16 electric from the face side of semiconductor substrate 13 The layout in road portion 42.The semiconductor device of embodiment 5 is with the semiconductor device of embodiment 3 the difference lies in that by lateral The p of type n-channel MOSFET 20++Type contact zone 84 is with the n with substantially rectangular flat shape+Three sides of type source region 22 are opposed Mode be configured to surround the n+The flat shape of substantially U-shaped around type source region 22.
5th contact trench 85a is along p++The flat shape and n of the substantially U-shaped of type contact zone 84+The 3 of type source region 22 A side is opposed.The bottom surface of 5th contact trench 85a is by p++Type contact zone 84 covers.p++It type contact zone 84 can be from the 5th contact The bottom surface of groove 85a covers always bottom surface corner.The cross section structure of 5th contact trench 85a connects with the second of embodiment 1 It is identical to touch groove 27a (referring to Fig.1, Fig. 2).
As needed, can with p++The p that the mode that type contact zone 84 contacts will illustrate in embodiment 1+Type contact zone 29 are configured at around the 5th contact trench 85a in a manner of covering the side of the 5th contact trench 85a.First active area 55 with The distance between second active area 52 d10' is and the energy with more than the minimum residual dimension of the LOCOS film of machining accuracy limitation It is enough to reduce to the p for surrounding the second active area 52+Type diffusion region 31 does not enter being covered in the first active area 55 by gate electrode 26 The distance of the degree of partial inside.
Embodiment 5 can be applied to embodiment 2.
More than, as explained above, according to embodiment 5, the p of the lateral type n-channel MOSFET of control circuit++Type connects Touching area is only configured at n+Type source region relative to n+The opposite side in 23 side of type drain region and the inside of the first active area, no matter p++How is the flat shape of type contact zone, can obtain effect identical with Embodiments 1 to 4.
More than, in the present invention, it is not limited to above-mentioned each embodiment, without departing from the spirit and scope of the invention can It makes various changes.For example, in above-mentioned each embodiment, although the semiconductor element as deferent segment has been illustrated And the case where longitudinal type MOSFET of trench gate structure is set, but the semiconductor element as deferent segment, ditch also can be set The longitudinal type IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor) of slot grid structure and/ Or the various devices such as longitudinal type MOSFET, IGBT of planar gate structure.It should be noted that for longitudinal type IGBT, example N can such as be replaced+Type initial substrate 1 and use p+Type initial substrate, in the p+The back surface forming electrode of type initial substrate.In addition, The present invention can be applied to have the various devices (element) for constituting circuit portion on the same semiconductor substrate and protect these Device exempts from the semiconductor device for the protection element being affected by surge.In addition, for the present invention, even if conductivity type (N-shaped, p-type) Reversion, it is also the same to set up.
Industrial utilizability
More than, the manufacturing method of semiconductor device of the invention and semiconductor device is suitable for having deferent segment and circuit portion It is configured at the same semiconductor substrate and in p identical with the device of circuit portion is constituted-The internal protection of the type well region device is exempted from The semiconductor device for the protection diode being affected by surge.

Claims (18)

1. a kind of semiconductor device, which is characterized in that the semiconductor device has first yuan on the same semiconductor substrate Part and second element,
The first element includes
First semiconductor region of the second conductive type is selectively arranged at the first of the semiconductor substrate of the first conductive type The superficial layer of interarea；
Second semiconductor region of the first conductive type is selectively arranged at the inside of first semiconductor region；
The third semiconductor region of the second conductive type is selectively arranged at the inside of first semiconductor region, and impurity is dense It spends higher than the impurity concentration of first semiconductor region；
The semiconductor layer of the first conductive type is set to the first semiconductor region described in the ratio of the semiconductor substrate closer to second The position of main surface side, and contacted with first semiconductor region；
Area between first gate insulating film, with second semiconductor region of first semiconductor region and the semiconductor layer Domain is placed in contact with；
First gate electrode, be set to across first gate insulating film and the side opposite with first semiconductor region；
First groove, from the semiconductor substrate in a manner of throughout second semiconductor region and the third semiconductor region The first interarea start of calculation be arranged at a predetermined depth；
First electrode, is filled into the inside of the first groove, and with second semiconductor region and the third semiconductor Area's electrical connection；And
Second electrode is set to the second interarea of the semiconductor substrate, and is electrically connected with the semiconductor substrate,
The second element includes
4th semiconductor region of the second conductive type is separated and is selectively arranged at first semiconductor region and described partly led The superficial layer of first interarea of structure base board；
5th semiconductor region of the first conductive type is selectively arranged at the inside of the 4th semiconductor region；
6th semiconductor region of the first conductive type separates with the 5th semiconductor region and is selectively arranged at the described 4th The inside of semiconductor region；
7th semiconductor region of the second conductive type is selectively arranged at the inside of the 4th semiconductor region, and impurity is dense It spends higher than the impurity concentration of the 4th semiconductor region；
Second gate insulating film, with the 4th semiconductor region positioned at the 5th semiconductor region and the 6th semiconductor region Between region be placed in contact with；
Second gate electrode, be set to across second gate insulating film and the side opposite with the 4th semiconductor region；
Second groove, from the semiconductor substrate in a manner of throughout the 5th semiconductor region and the 7th semiconductor region The first interarea start of calculation be arranged at a predetermined depth；
Third groove is set to the 6th semiconductor from the start of calculation of the first interarea of the semiconductor substrate at a predetermined depth Area；
Third electrode, is filled into the inside of the second groove, and with the 5th semiconductor region and the 7th semiconductor Area's electrical connection；
4th electrode is filled into the inside of the third groove, and is electrically connected with the 6th semiconductor region；And
8th semiconductor region of the second conductive type separates with the second element and is selectively arranged at the described 4th half and leads The inside in body area, and penetrate through the 4th semiconductor region from the first interarea of the semiconductor substrate and reach the semiconductor Layer, the impurity concentration of the 8th semiconductor region is higher than the impurity concentration of the 4th semiconductor region,
Wherein, the depth of the third groove than the 6th semiconductor region depth as shallow,
7th semiconductor region covers the bottom surface of the second groove, pre- starting from the first interarea of the semiconductor substrate The position of depthkeeping degree, impurity concentration highest.
2. semiconductor device according to claim 1, which is characterized in that the depth of the second groove is than the described 5th half The depth as shallow of conductor region.
3. semiconductor device according to claim 1, which is characterized in that the depth of the second groove is than the described 5th half The depth of conductor region is deep.
4. semiconductor device described in any one of claim 1 to 3, which is characterized in that be also equipped with the second conductive type 9th semiconductor region, the 9th semiconductor region are selectively arranged at the inside of the 4th semiconductor region, and described in covering The side wall of the side opposite relative to the 5th semiconductor region side of second groove, and the impurity of the 9th semiconductor region Concentration is higher than the impurity concentration of the 4th semiconductor region.
5. semiconductor device according to claim 4, which is characterized in that the 7th semiconductor region is led with the described 9th half The contact of body area.
6. semiconductor device according to any one of claims 1 to 5, which is characterized in that the 7th semiconductor region with The 5th semiconductor region contact.
7. semiconductor device described according to claim 1~any one of 6, which is characterized in that the 7th semiconductor region tool Have and spreads the second conductive type impurity to the inner radiation shape of the 4th semiconductor region from the bottom surface of the second groove and form Circle or ellipse cross sectional shape.
8. semiconductor device according to any one of claims 1 to 7, which is characterized in that the 7th semiconductor region is set Be placed in across the 5th semiconductor region and the side opposite with the 6th semiconductor region.
9. semiconductor device described according to claim 1~any one of 8, which is characterized in that the entirety of the third groove It is covered by the 6th semiconductor region.
10. semiconductor device described according to claim 1~any one of 9, which is characterized in that the depth of the first groove Than the depth as shallow of second semiconductor region.
11. semiconductor device described according to claim 1~any one of 9, which is characterized in that the first groove penetrates through institute It states the second semiconductor region and reaches first semiconductor region.
12. semiconductor device described according to claim 1~any one of 11, which is characterized in that the third semiconductor region It is contacted with second semiconductor region.
13. semiconductor device described according to claim 1~any one of 12, which is characterized in that the third semiconductor region With the second conductive type impurity is spread to the inner radiation shape of first semiconductor region from the bottom surface of the first groove and At circle or ellipse cross sectional shape.
14. semiconductor device described according to claim 1~any one of 12, which is characterized in that the 8th semiconductor region It is arranged along the periphery of the 4th semiconductor region, and surrounds around the second element.
15. a kind of manufacturing method of semiconductor device, which is characterized in that the semiconductor device is on the same semiconductor substrate Have first element and second element,
The formation process of the first element includes:
First step is formed selectively the first semiconductor of the second conductive type in the superficial layer of the semiconductor layer of the first conductive type Area, the superficial layer of the semiconductor layer of the first conductive type constitute the first interarea of the semiconductor substrate of the first conductive type；
The second step is formed selectively the second semiconductor region of the first conductive type in the inside of first semiconductor region；
The third step, it is more miscellaneous than first semiconductor region in the selectively formed impurity concentration in inside of first semiconductor region The third semiconductor region of the highly concentrated the second conductive type of matter；
The fourth step, formed and first semiconductor region between second semiconductor region and the semiconductor layer First gate insulating film of region contact；
5th process is forming first grid electricity across first gate insulating film side opposite with first semiconductor region Pole；
6th process, in a manner of throughout second semiconductor region and the third semiconductor region, from the semiconductor substrate The first interarea start of calculation form first groove at a predetermined depth；
7th process inserts first electrode in the inside of the first groove；And
8th process forms second electrode in the second interarea of the semiconductor substrate,
The formation process of the second element includes:
9th process separates with first semiconductor region in the superficial layer of the semiconductor layer and is formed selectively second 4th semiconductor region of conductivity type；
Tenth process, in the inside of the 4th semiconductor region, the 5th semiconductor region of selectively formed the first conductive type；
11st process is separated and is formed selectively with the 5th semiconductor region in the inside of the 4th semiconductor region 6th semiconductor region of the first conductive type；
12nd process is formed selectively impurity concentration than the 4th semiconductor in the inside of the 4th semiconductor region 7th semiconductor region of the high the second conductive type of the impurity concentration in area；
13rd process is formed between the 5th semiconductor region and the 6th semiconductor region of the 4th semiconductor region Region contact the second gate insulating film；
14th process is forming second gate across second gate insulating film side opposite with first semiconductor region Electrode；
15th process, in a manner of throughout the 5th semiconductor region and the 7th semiconductor region, from described semiconductor-based The first interarea start of calculation of plate forms second groove at a predetermined depth；
16th process, in the 6th semiconductor region, to start scheduled depth from the first interarea of the semiconductor substrate Form third groove；
17th process inserts third electrode in the inside of the second groove；And
18th process inserts the 4th electrode in the inside of the third groove,
Further include the 19th process, in the inside of the 4th semiconductor region, is separated with the second element and selective landform At the 8th semiconductor region of the second conductive type, the 8th semiconductor region is from described in the perforation of the first interarea of the semiconductor substrate 4th semiconductor region and reach the semiconductor layer, and the impurity concentration of the 8th semiconductor region is than the 4th semiconductor region Impurity concentration it is high,
The 12nd process is carried out after the 15th process,
In the 12nd process, by the bottom that the second conductive type impurity is injected into the second groove with ionic means Face, and form the 7th semiconductor region for covering the bottom surface of the second groove.
16. the manufacturing method of semiconductor device according to claim 15, which is characterized in that while carrying out second work Sequence, the tenth process and the 11st process.
17. the manufacturing method of semiconductor device according to claim 15 or 16, which is characterized in that while carrying out described Six processes and the 15th process.
18. the manufacturing method of semiconductor device according to claim 17, which is characterized in that while carrying out the 6th work Sequence, the 15th process and the 16th process.
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