CN109119346B - Packaging method and structure of wafer-level chip - Google Patents
Packaging method and structure of wafer-level chip Download PDFInfo
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- CN109119346B CN109119346B CN201810932328.5A CN201810932328A CN109119346B CN 109119346 B CN109119346 B CN 109119346B CN 201810932328 A CN201810932328 A CN 201810932328A CN 109119346 B CN109119346 B CN 109119346B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
Abstract
The invention provides a packaging method and a structure of a wafer-level chip, wherein the method comprises the following steps: forming a conductive convex column on a welding pad on the front surface of the wafer; forming a welding column on the conductive convex column, wherein the cross section area of the welding column is unchanged along the thickness direction; forming a first plastic packaging layer on the front surface of the wafer, the periphery of the conductive convex column and the periphery of the welding column; and performing a thinning procedure on the first plastic packaging layer to expose the welding column. The invention provides a packaging method and a structure of a wafer-level chip, which have the advantages of good weldability, simple preparation process, low cost, high yield, smaller size of a packaged product and thinner thickness.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a packaging method and a structure of a wafer-level chip.
Background
The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
The wafer bumping technology is to form metal bumps on the metal pads of the bare wafer by a series of processes to electrically interconnect the package with the outside. In practice, the metal stud may be provided with a ball, and the ball may be used to electrically connect the packaged chip product to the outside. Wherein, the weldability is an index for checking whether the ball planting can reliably realize the electric connection with the outside.
Due to the trend of light and thin electronic devices, the packaged chip products are required to have smaller size and thinner thickness. However, under the demand of this trend, the solderability requirement of ball mounting of current chip products is difficult to be satisfied simply and at low cost.
It should be noted that the above background description is only for the sake of clarity and complete description of the technical solutions of the present invention and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the invention.
Disclosure of Invention
Based on the foregoing defects in the prior art, embodiments of the present invention provide a method and structure for packaging a wafer level chip, which have the advantages of good solderability, simple manufacturing process, low cost, high yield, smaller size of the packaged product, and thinner thickness.
In order to achieve the above object, the present invention provides the following technical solutions.
A packaging method of wafer level chips comprises the following steps: forming a conductive convex column on a welding pad on the front surface of the wafer; forming a welding column on the conductive convex column, wherein the cross section area of the welding column is unchanged along the thickness direction of the welding column; forming a first plastic packaging layer on the front surface of the wafer, the periphery of the conductive convex column and the periphery of the welding column; and performing a thinning procedure on the first plastic packaging layer to expose the welding column.
A wafer level chip package structure, comprising: the chip unit is provided with a plurality of conductive convex columns formed on a welding pad on the front surface, welding columns formed on the conductive convex columns, and the cross sectional areas of the welding columns are not changed along the thickness direction of the welding columns; the first plastic packaging layer covers the front face of the wafer unit, the conductive convex columns and the peripheries of the welding columns, the welding columns are exposed out of the first plastic packaging layer, and the shape and the cross-sectional area of the parts of the welding columns, which are exposed out of the first plastic packaging layer, are the same.
According to the packaging method and structure of the wafer-level chip, provided by the embodiment of the invention, the solder columns with unchanged shapes and section areas along the thickness direction are adopted to replace ball planting. After polishing and thinning, the exposed shapes and the cross-sectional areas of the welding columns are the same. Therefore, the process steps are saved, the exposed shape and the cross-sectional area of the welding column are easy to control, the preparation process is simple, the cost is reduced, and the packaging yield is greatly improved.
Simultaneously, the welding column is polished and thinned together with the plastic packaging layer, so that the end face of the welding column is flush with the surface of the plastic packaging layer. So, compare in prior art's plant ball, the solder column can not occupy packaging structure's thickness direction's spatial dimension for packaging structure's size is littleer, and thickness is thinner, thereby provides more excellent encapsulation solution for little volume product.
Specific embodiments of the present invention are disclosed in detail with reference to the following description and drawings, indicating the manner in which the principles of the invention may be employed. It should be understood that the embodiments of the invention are not so limited in scope. The embodiments of the invention include many variations, modifications and equivalents within the spirit and scope of the appended claims.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Drawings
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for facilitating the understanding of the present invention, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members of the present invention. Those skilled in the art, having the benefit of the teachings of this invention, may choose from the various possible shapes and proportional sizes to implement the invention as a matter of case. In the drawings:
FIG. 1 is a schematic diagram of a wafer structure;
FIG. 2 is a schematic diagram of a structure of a conductive pillar formed on a wafer;
FIG. 3 is a schematic diagram of a structure of forming a solder pillar on a conductive stud;
FIG. 4 is a schematic diagram illustrating a structure of forming grooves on the front surface of a wafer at locations corresponding to scribe lines;
FIG. 5 is a schematic structural diagram of a first molding compound layer formed on the front surface of the wafer and on the periphery of the conductive stud and the solder stud;
FIG. 6 is a schematic structural diagram of the thinned first plastic package layer and the back surface of the wafer;
fig. 7 is a schematic view of a package structure of a wafer level chip obtained after cutting the first plastic package layer.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a single embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The main reason for poor solderability of the existing packaged chip product adopting the planting balls is that the exposed areas of the planting balls are difficult to keep the same. In particular, in the known embodiments provided in the series of patent applications such as CN104952743A, CN104992936A, CN204614775U and CN104979318A, although the size and thickness of the packaged product can be reduced to some extent by grinding and thinning the molding compound, the conventional ball mounting process is still used. That is, the ball-planting is not ground, the ball-planting still occupies a part of the space in the thickness direction, so that the thickness reduction is limited.
If the known embodiment adopts the same or similar process as the present invention, the ball attachment is polished while the plastic package material is polished and thinned, so that the end face of the ball attachment is flush with the plastic package material, and the problem of poor solderability of the packaged chip product is difficult to completely solve.
The main reason is that the number of the planted balls is multiple. After the ball mounting is completed, reflow soldering operation is generally performed on the mounted balls, so that shapes of the mounted balls are difficult to keep completely consistent, and the finally formed mounted balls may have shape distortion. For example, some of the planted balls are ellipsoidal, some of the planted balls are rugby, or some of the planted balls are not strictly spherical. The cross-sectional shape and area of these spheroidal irregular planting balls vary. Thus, the shapes and cross-sectional areas of the exposed shapes and cross-sectional areas of the plurality of planting balls after being polished are different, thereby resulting in poor weldability.
Therefore, in the prior art, the ball-planting mode is adopted to realize the electrical connection, so that a reflow soldering process is added, the process is complex, and the problem of poor weldability of a packaged chip product caused by reflow soldering is solved.
Embodiments of the present invention provide a method and a structure for packaging a wafer level chip, which can better solve the above problems.
As shown in fig. 1, a wafer 1 with a circuit structure layer is provided, a plurality of chip units 100 with the same structure are formed on the wafer 1, and dicing streets are formed between the chip units 100 to distinguish the chip units 100.
One surface of the wafer 1 or each chip unit 100 on which the circuit layer is provided is a front surface 101 (an upper surface as illustrated in fig. 1), and the other surface opposite thereto is a rear surface 102. The front surface 101 of the wafer 1 or the chip unit 100 is provided with a plurality of exposed metal pads 2 arranged at intervals, and a passivation layer (not shown) can be formed between the pads 2, and the packaging method comprises the following steps:
as shown in fig. 2, step S1: forming a conductive convex column 3 on a welding pad 2 on the front surface 101 of the wafer 1;
as shown in fig. 3, step S2: forming a welding column 4 on the conductive convex column 3, wherein the cross section area of the welding column 4 is unchanged along the thickness direction;
as shown in fig. 5, step S3: forming a first plastic packaging layer 5 on the periphery of the front surface 101 of the wafer 1, the conductive convex column 3 and the welding column 4;
as shown in fig. 6, step S4: and thinning the first plastic packaging layer 5 to expose the welding columns 4.
In step S1, the conductive stud 3 is a copper pillar with a height of 5 to 50 um. In order to make the bonding force between the metal pad 2 of the wafer 1 and the conductive pillar 3 more stable and improve the reliability of the product, a seed layer (not shown) with a thickness of 0.5 to 1um and a composition of titanium and copper may be formed on the pad 2 of the wafer 1 by an electroplating process before step 1, and the conductive pillar 3 is formed on the seed layer by electroplating.
In step S2, the solder post 4 is a tin post, which may also be formed on the top end of the conductive stud 3 by electroplating, so that the solder post 4 can be easily formed or maintained in a regular shape.
Preferably, the cross-sectional shape and size of the solder post 4 in the thickness direction thereof are identical to the cross-sectional shape and size of the conductive stud 3 in the thickness direction thereof, for example, the conductive stud 3 and the solder post 4 may have a cylindrical shape or a polygonal column shape.
Of course, the shapes of the solder post 4 and the conductive post 3 are not limited to the above list. Since only the thinning of the solder columns 4 is needed subsequently and good solderability is obtained, only the solder columns 4 are required to have a regular shape. Therefore, as long as the cross-sectional area of the stud 4 remains constant in the thickness direction thereof, there is no need for the conductive stud 3 and the shape correlation thereof with the stud 4.
Since the solder columns 4 are regular in shape, the shape and area of the cross section thereof in the thickness direction are unchanged, for example, circular or polygonal. Thus, after the thinning step is performed, the exposed shapes and areas of the plurality of solder columns 4 are the same, so that the solderability of the package structure is better.
In step S3, the first molding compound layer 5 is made of epoxy resin material, and the surface of the first molding compound layer is higher than the top end of the solder post 4, specifically, the thickness of the first molding compound layer 5 at least exceeds the thickness of the solder post 4 by 20 um.
In step S4, the thickness of the first molding layer 5 is thinned by an amount greater than the height difference from the top end of the solder post 4. Thus, the solder columns 4 are collectively ground to be thinner. Thus, after the first plastic package layer 5 is thinned, the residual thickness of the welding column 4 is smaller than the initial thickness.
For example, the solder columns 4 have an initial thickness of 25 to 50um, and after thinning, the remaining thickness is 10 to 20 μm.
Because the welding column 4 and the first plastic-sealed layer 5 are polished and thinned together, after the thinning is finished, the end face of the welding column 4 is flush with the surface of the first plastic-sealed layer 5. Thus, the solder columns 4 do not occupy the spatial dimension in the thickness direction of the package structure, so that the package structure is smaller in size and thinner in thickness.
As shown in fig. 4, before step S3, the method further includes: grooves 103 are formed in the front surface 101 of the wafer 1 at positions corresponding to the dicing streets. Accordingly, in step S3, the first molding layer 5 is filled in the groove 103.
In the present embodiment, the grooves 103 are obtained by cutting the front surface 101 of the wafer 1 at the positions corresponding to the scribe lines, and the cutting depth is less than the thickness of the wafer 1, preferably 1/3, which is less than or equal to the original thickness of the wafer 1, and the cutting method is mechanical cutting using a blade.
By forming the groove 103 at the position of the front surface 101 of the wafer 1 corresponding to the scribe line, the first plastic package layer 5 filled into the groove 103 can cover the sidewall of the chip unit 100, and the second plastic package layer mentioned below is used to cover the back surface 102 of the chip unit 100, so that the package structure is fully covered, and the package effect is ensured.
As shown in fig. 6, after step S4, a thinning process may be performed on the back surface 102 of the wafer 1 to polish the bottom of the groove 103 and expose the first molding compound 5 filled in the groove 103.
Further, the back side 102 of the wafer 1 may be packaged, that is, a second molding compound layer (not shown) with a thickness greater than or equal to 50um is formed on the back side 102 of the wafer 1.
Subsequently, the first molding layer 5 is cut along the dicing streets to separate the plurality of wafer units 100 from each other, thereby obtaining the package structure shown in fig. 7. Specifically, a laser cutting process may be used to make full cuts along the centerline 104 of the street.
As shown in fig. 7, the individual package structure includes:
a plurality of conductive columns 3 are formed on a bonding pad 2 on the front surface 101 of the chip unit 100, bonding posts 4 are formed on the conductive columns 3, and the cross-sectional areas of the bonding posts 4 are not changed along the thickness direction;
the first plastic package layer 5 covers the front surface 101 of the wafer unit 100, the conductive posts 3 and the peripheries of the welding posts 4, the first plastic package layer 5 is exposed out of the welding posts 4, and the shapes and the cross-sectional areas of the parts of the welding posts 4 exposed out of the first plastic package layer 5 are the same.
The package structure may further include a second molding layer covering the back surface 102 of the chip unit 100.
According to the packaging method and structure of the wafer-level chip, provided by the embodiment of the invention, the solder columns 4 with unchanged shapes and section areas along the thickness direction are adopted to replace ball planting. The exposed shapes and cross-sectional areas of the plurality of welding columns 4 are the same after polishing and thinning. Therefore, the process steps are saved, the exposed shape and the cross-sectional area of the welding column 4 are easy to control, the preparation process is simple, the cost is reduced, and the packaging yield is greatly improved.
Meanwhile, the welding column 4 is polished and thinned together with the first plastic package layer 5, so that the end face of the welding column 4 is flush with the surface of the plastic package layer. So, compare in prior art's plant ball, weld post 4 can not occupy the space size of packaging structure's thickness direction for packaging structure's size is littleer, and thickness is thinner, thereby provides better encapsulation solution for little volume product.
It should be noted that, in the description of the present invention, the terms "first", "second", and the like are used for descriptive purposes only and for distinguishing similar objects, and no precedence between the two is considered as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego such subject matter, nor should the applicant consider that such subject matter is not considered part of the disclosed subject matter.
Claims (9)
1. A method for packaging wafer level chips, comprising:
forming a conductive convex column on a welding pad on the front surface of the wafer, wherein the cross-sectional area of the conductive convex column is unchanged along the thickness direction;
forming a welding column on the conductive convex column, wherein the cross section area of the welding column is unchanged along the thickness direction of the welding column;
forming a first plastic package layer on the front surface of the wafer, the periphery of the conductive convex column and the periphery of the welding column, wherein the surface of the first plastic package layer is higher than the top end of the welding column;
performing a thinning procedure on the first plastic package layer to expose the welding column, wherein the thickness thinning amount of the first plastic package layer is greater than the height difference between the first plastic package layer and the top end of the welding column, so that the residual thickness of the welding column is less than the initial thickness of the welding column after the first plastic package layer is thinned; the welding columns with unchanged shapes and section areas along the thickness direction are adopted to replace the ball planting, and after the grinding and thinning, the shapes and the section areas of the exposed welding columns are the same.
2. The packaging method of claim 1, wherein prior to the step of forming the conductive posts, the method further comprises: and forming a seed layer on the welding pad, wherein the conductive convex columns are formed on the seed layer, and the seed layer is formed through an electroplating process.
3. The packaging method of claim 1, wherein the conductive post and the solder post are formed by an electroplating process, and a cross-sectional shape of the solder post is the same as a cross-sectional shape of the conductive post.
4. The packaging method of claim 1,
before the step of forming the first molding layer, the method further comprises: forming a groove at the position of the front surface of the wafer corresponding to the cutting channel;
accordingly, when the first molding compound layer is formed, the first molding compound layer is filled in the groove.
5. The packaging method according to claim 4, wherein the groove is obtained by cutting the front surface of the wafer at a position corresponding to the scribe line, and the cutting depth is smaller than the thickness of the wafer.
6. The method of packaging of claim 4, wherein after the step of thinning the first molding layer, the method further comprises: and thinning the back surface of the wafer to expose the first plastic packaging layer filled in the groove.
7. The packaging method of claim 6, wherein after the step of thinning the backside of the wafer, the method further comprises: and cutting the first plastic packaging layer along the cutting path to separate the wafer units from each other.
8. The method for encapsulating according to claim 7, wherein before the step of cutting the first molding compound along the cutting street, the method further comprises: and forming a second plastic packaging layer on the back of the wafer.
9. A wafer level chip package structure manufactured by the method according to any one of claims 1 to 8, the wafer level chip package structure comprising:
the chip unit is provided with a plurality of conductive convex columns on a welding pad on the front surface, welding columns are formed on the conductive convex columns, and the cross sectional areas of the welding columns are not changed along the thickness direction of the welding columns;
the first plastic packaging layer covers the front surface of the wafer unit, the conductive convex columns and the peripheries of the welding columns, the plurality of welding columns are exposed out of the first plastic packaging layer, and the shapes and the cross-sectional areas of the parts of the plurality of welding columns, which are exposed out of the first plastic packaging layer, are the same; the welding columns with unchanged shapes and section areas along the thickness direction are adopted to replace the ball planting, and after the grinding and thinning, the shapes and the section areas of the exposed welding columns are the same.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204216021U (en) * | 2014-09-28 | 2015-03-18 | 南通富士通微电子股份有限公司 | Wafer stage chip encapsulating structure |
| CN105428251A (en) * | 2015-12-16 | 2016-03-23 | 南通富士通微电子股份有限公司 | Stacked packaging method for semiconductor |
| CN107946256A (en) * | 2016-11-01 | 2018-04-20 | 日月光半导体制造股份有限公司 | Semiconductor device packages and its forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001176899A (en) * | 1999-12-21 | 2001-06-29 | Sanyo Electric Co Ltd | Manufacturing method for semiconductor device |
| JP3829325B2 (en) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
| US7112524B2 (en) * | 2003-09-29 | 2006-09-26 | Phoenix Precision Technology Corporation | Substrate for pre-soldering material and fabrication method thereof |
| WO2006035321A2 (en) * | 2004-05-06 | 2006-04-06 | United Test And Assembly Center, Ltd. | Structurally-enhanced integrated circuit package and method of manufacture |
| JP5337404B2 (en) * | 2008-05-21 | 2013-11-06 | ローム株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2012069704A (en) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204216021U (en) * | 2014-09-28 | 2015-03-18 | 南通富士通微电子股份有限公司 | Wafer stage chip encapsulating structure |
| CN105428251A (en) * | 2015-12-16 | 2016-03-23 | 南通富士通微电子股份有限公司 | Stacked packaging method for semiconductor |
| CN107946256A (en) * | 2016-11-01 | 2018-04-20 | 日月光半导体制造股份有限公司 | Semiconductor device packages and its forming method |
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