CN208433406U - Encapsulate chip - Google Patents
Encapsulate chip Download PDFInfo
- Publication number
- CN208433406U CN208433406U CN201820414812.4U CN201820414812U CN208433406U CN 208433406 U CN208433406 U CN 208433406U CN 201820414812 U CN201820414812 U CN 201820414812U CN 208433406 U CN208433406 U CN 208433406U
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- Prior art keywords
- metal column
- chip
- metal
- column
- plastic packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
This application discloses encapsulation chips.The encapsulation chip includes: chip；First plastic packaging layer, covers the chip；And multiple metal columns, respectively include opposite first end and second end, wherein the first end is contacted with the chip, and the second end is exposed to outside the first plastic packaging layer.The encapsulation chip provides external electrical connections using metal column, to reduce package area and improve reliability.
Description
Technical field
The utility model relates to field of chip manufacture technology, more particularly, to encapsulation chip.
Background technique
With the extensive use and fast development of mobile terminal and consumer electronics product, the charge protection core of electronic product
Piece is more and more important.Charge protection chip not only needs to meet the requirement that electronic product area persistently reduces, but also needs full
Sufficient quick charge is to save the requirement in charging time, and meets the needs of test is to screen failure circuit chip.Therefore, to electricity
The requirement of the performance of sub- product, especially charging protection chip for lithium battery is gradually increased, and the area of chip is gradually reduced, and wants simultaneously
Chip is asked to have preferably heat dissipation to cope with the demand of quick charge.It is smaller, thinner and lighter, bigger that this requires circuit chips
Electric current, smaller conducting resistance and preferably heat dissipation.
However, existing circuit chip using die-attach area support chip, using plain conductor by the pad of chip with
The pin of lead frame is connected, and is then encapsulated using plastic packaging layer, forms encapsulation chip (chip package).With traditional
For charging protection chip for lithium battery, scribing goes out one single chip from chip, is then packaged, for example, by using SOT-23-6's
Packing forms.Due to providing external electrical connections using the pin of lead frame, it is therefore desirable to which additional pin space, this at least increases
The area of former chip 20%.In encapsulation chip interior, internal electrical connection is provided using plain conductor, this is it is difficult to ensure that pass through big
Electric current, it is also difficult to obtain small conducting resistance, be also all restricted on heat dissipation characteristics.In other circuit chips, by chip
On face-down bonding lead frame, although high current ability can be provided, lead frame still needs additional pin space, causes to seal
It is larger to fill area.
Before by charging protection chip for lithium battery supply market, it is also necessary to test it, such as before encapsulation
It is tested.The test pin of existing charging protection chip for lithium battery design specialized, or be also used as surveying using grounding pin
Try pin.In chip testing, being connected to power supply using dedicated test pin can reduce test delay, and test effect is substantially improved
Rate.Test pin can be covered or exposed in encapsulation process.However, exposure is the dedicated test pin in the final product
Unfavorable, pin number increase is not only resulted in, and accordingly result in package area increase, and need to be distinguished in use
Not, cause inconvenient for use.If being the incorrect link test pin in final products, in some instances it may even be possible to lead to wafer damage.Using
The test pin of dual-purpose then will lead to excessive, the as a result testing efficiency reduction that is delayed.
Therefore, it is desirable to which ground is further improved the encapsulating structure of chip, chip is improved while adapting to chip miniaturization
Energy and reliability, and improve testing efficiency.
Utility model content
In view of this, providing external electric using metal column the purpose of this utility model is to provide a kind of encapsulation chip
It connects to reduce package area and improve reliability.
It is according to the present utility model in a first aspect, providing a kind of encapsulation chip characterized by comprising chip；First modeling
Sealing covers the chip；And multiple metal columns, respectively include opposite first end and second end, wherein the multiple gold
The first end for belonging to column is contacted with the chip, and the second end is exposed to outside the first plastic packaging layer.
Preferably, the first plastic packaging layer encapsulates the chip.
It preferably, further include the second plastic packaging layer, core described in the first plastic packaging layer and the second plastic packaging layer coencapsuiation
Piece.
Preferably, the multiple metal column is respectively column, cross sectional shape be selected from cylinder, semicircle, prismatic, polygon and
It is irregular follow it is any in shape.
Preferably, the height of the multiple metal column is 1 micron -200 microns.
Preferably, the height of the multiple metal column is 20 microns.
Preferably, the multiple metal column is made of nickel, and the second end of the multiple metal column plates weldability metal
Or its alloy.
Preferably, the weldability metal is any one in gold, silver and copper.
Preferably, the multiple metal column is formed by chemical plating.
Preferably, the chip respectively includes pad, the first end of the multiple metal column and the contact pads.
Preferably, the chip is charging protection chip for lithium battery.
Preferably, the first plastic packaging layer and the second plastic packaging layer selected from epoxies sealing, organic silicon respectively by sealing
Any one composition in glue, polyurethane sealing and ultraviolet photo-curing sealing.
Preferably, the first plastic packaging layer and the second modeling seal coat thickness are respectively 20 microns to 30 microns.
Preferably, the multiple metal column includes the first metal column for test and the second metal for ground connection
Column, first metal column and second metal column are disposed proximate to, by described first after the encapsulation chip completes test
Metal column and the second metal pole interconnection.
Preferably, it is separated by between first metal column and second metal column by the first plastic packaging layer, in institute
The second end of first metal column and the second end of second metal column after encapsulation chip completion is tested is stated to weld together.
Preferably, it is separated by between first metal column and second metal column by air, in the encapsulation chip
The second end of first metal column and the second end of second metal column after testing is completed to weld together.
Preferably, the shape of the chip is rectangle, and first metal column and second metal column are set to described
The center of rectangle.
Preferably, first metal column is identical with the second metal column shape, and is symmetrically set.
Preferably, first metal column and second metal column are prism, first metal column and described
One side of two metal columns is relative to each other and is parallel to the side of the rectangle.
Preferably, the multiple metal column further include: for connecting the third metal column of power supply side；It is controlled for connecting
4th metal column of discharge switch signal end processed；For connecting the fifth metal column of control charge switch signal end；And it is used for
Connect the 6th metal column at induced current end.
Preferably, the third metal column, the 4th metal column, the fifth metal column and the 6th metal column
It is set to the corner location of the rectangle.
Preferably, the third metal column, the 4th metal column, the fifth metal column and the 6th metal column
It is prism, the third metal column, the 4th metal column, the fifth metal column and the 6th metal column are respective
At least one side is parallel to the side of the rectangle.
Preferably, the third metal column, the 4th metal column, the fifth metal column and the 6th metal column
At least one respective side, it is relative to each other at least one side of one of first metal column and second metal column
And it is parallel to each other.
Second aspect according to the present utility model provides a kind of manufacturing method for encapsulating chip characterized by comprising
The chip for having multiple chips is provided；Multiple metal columns are formed on the wafer；The first plastic packaging material is covered on the wafer,
To form package assembling；And scribing is carried out to be separated into multiple encapsulation chips to the package assembling, wherein described more
The first end of a metal column is contacted with the chip, and the second end is exposed to outside the first plastic packaging layer.
Preferably, between the step of forming multiple metal columns and the step of covering the first plastic packaging material, further includes: will be described
Chip is placed on the second plastic packaging layer.
Preferably, the step of chip is provided and formed multiple metal columns the step of between, further includes: to the chip into
Row scribing is to form groove between the multiple chip.
Preferably, to the chip carry out scribing the step of include: from least one front and back of the chip into
Row scribing.
Preferably, the step of scribing being carried out to the package assembling include: from the front and back of the package assembling to
It is one of few to carry out scribing.
Preferably, before the step of chip is provided, further includes: the chip is thinned to reduce the encapsulation core
The thickness of piece.
Preferably, the multiple metal column includes the first metal column for test and the second metal for ground connection
Column, first metal column and second metal column are disposed proximate to.
Preferably, it between the step of carrying out scribing the step of forming the first plastic packaging layer and to the package assembling, also wraps
It includes: being tested using first metal column.
Preferably, after the step of being tested, further includes: first metal column and second metal column is mutual
Even.
Preferably, wherein the second end of first metal column and the second end of second metal column weld together,
To realize interconnection.
According to the encapsulation chip of the utility model embodiment, external electrical connections are provided using metal column, so as to save
Lead frame and plain conductor further save pin space and reduce package area.Another advantage using metal column is gold
The current carrying capacity for belonging to column is higher than plain conductor, and ghost effect is less than plain conductor, and heat-sinking capability is excellent.With existing skill
The soldered ball of art is compared, and metal column side wall has encapsulated layer protection.Therefore, which can be improved Performance And Reliability.
In a preferred embodiment, in encapsulation chip, the height of metal column is 1 micron -200 microns, and optimal is 20
Micron, and can accomplish smaller thinner.Compared with the soldered ball of the prior art, the diameter of soldered ball is, for example, 100 micron -200 micro-
Rice.Therefore, which can reduce thickness.
In a preferred embodiment, multiple chips in chip or package assembling can integrally be picked up in the fabrication process
It takes, chip can be encapsulated on a large scale to improve to multiple chip integrated testabilities in chip or package assembling in test phase
Manufacture efficiency and testing efficiency.It is final that independent encapsulation chip is formed using scribing twice, so as to stop aqueous vapor and prevent
It only collides, improves yield rate.
In a preferred embodiment, which uses the first metal column to be tested to reduce test delay, is surveying
The first metal column and the second metal column are connected as one after examination, so as to improve testing efficiency and reduce final products
Number of terminals.In the final product, which does not have extra terminal, to both not need labeled test terminal, not yet
There are the risks that incorrect link calibrating terminal leads to wafer damage, so as to further increase chip reliability.
In a preferred embodiment, the chip form of the encapsulation chip is rectangle, first metal column and described second
Metal column is set to the center of the rectangle, the third metal column, the 4th metal column, the fifth metal column and institute
State the corner location that the 6th metal column is set to the rectangle.The maximum of distance between multiple metal columns may be implemented in the layout
Change, to prevent the short-circuit of terminals and improve the reliability for encapsulating chip, realization makes full use of package area, is conducive to encapsulate
The miniaturization of chip.
In a preferred embodiment, the third metal column, the 4th metal column, the fifth metal column and described
6th metal column is prism, the third metal column, the 4th metal column, the fifth metal column and the 6th gold medal
Belong at least one respective side of column and is parallel to the side of the rectangle, it is the third metal column, the 4th metal column, described
Fifth metal column and described at least one respective side of 6th metal column, with first metal column and second metal
At least one side of one of column is relative to each other and parallel to each other.In said structure, positioned at periphery metal column side with
The side of central metal column is opposite to each other and parallel, between the two not opposite protruding portion.Periphery gold may be implemented in the shape
Belong to the maximization of distance between column and central metal column, it can be to avoid the reliability of short circuit and raising encapsulation chip, further
Be conducive to encapsulate the miniaturization of chip.
In a preferred embodiment, chip is encapsulated using the first plastic packaging layer and the second plastic packaging layer.First plastic packaging layer and second
The thickness of plastic packaging layer is respectively 20 microns to 30 microns, chip can also be carried out before forming the first plastic packaging layer it is thinned so that
The area of final encapsulation chip and the area of chip are very close, meet chip size packages (Chip Scale Package,
CSP) the requirement of technique.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, the above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 a and 1b show the perspective view of the package assembling according to the utility model embodiment；
The perspective view of the encapsulation chip according to the utility model embodiment is shown respectively in Fig. 2 a and 2b；
Fig. 3 shows the flow chart of the manufacturing method of the encapsulation chip according to the utility model embodiment；
Fig. 4 a to Fig. 4 f shows cutting for each stage of the manufacturing method of the encapsulation chip according to the utility model embodiment
Face figure.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar
Appended drawing reference indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown
Certain well known parts.
It should be appreciated that being known as being located at another layer, another region when by one layer, a region when describing some structure
When " above " or " top ", can refer to above another layer, another region, or its with another layer, another
Also comprising other layers or region between region.Also, if the structure overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".If in order to describe located immediately at another layer, another region above scenario,
It herein will be using the form of presentation of " A is directly on B " or " A on B and therewith abut ".
In the description of the present invention, it should be understood that term " first ", " second " etc. are used for description purposes only,
It is not understood to indicate or imply relative importance.In addition, in the description of the present invention, unless otherwise indicated, it is " more
It is a " it is meant that two or more.
Fig. 1 a and 1b show the perspective view of the package assembling according to the utility model embodiment, wherein show in fig 1 a
The overall structure of package assembling removes the top plastic packaging layer of package assembling in Figure 1b to show the internal junction of package assembling
Structure.In this application, package assembling is the encapsulating structure that formation is integrally encapsulated to chip.
Package assembling 100 includes plastic packaging layer 110, chip 120, plastic packaging layer 130, metal column 140.Plastic packaging layer 110 and 130 point
Not Wei Yu chip following above and, thus coencapsuiation chip 120.Metal column 140 extends through plastic packaging layer 130.Metal column
140 include first end and second end relative to each other, and first end is contacted with the chip in chip 120, and second end is exposed to plastic packaging
Outside layer 130, for providing external electrical connections.
Further, chip 120 includes multiple chips 121 that groove 122 separates.The groove 122 is, for example, to use scribing
Method chip 120 upper and lower surfaces at least under the upper groove formed.The upper surface of chip 121 is formed with pad
123, it is electrically connected with the first end of metal column 140.
The material of plastic packaging layer 110 is, for example, epoxies sealing, organic silicon sealing, polyurethane sealing and UV-light photocuring
Change sealing etc..The color of plastic packaging layer 110 can be clear, colorless, also can according to need and makes any other color.It is preferred that
Ground, plastic packaging layer 110 with a thickness of 20 microns to 30 microns.
Plastic packaging layer 130 is, for example, epoxy resin, by being encapsulated chip 120 with plastic packaging layer 130 and plastic packaging layer 110
Come, so that chip 120 is isolated with external environment, reduces the influence for chip 120 such as steam in environment.Plastic packaging layer
130 thickness are preferably 20 microns to 30 microns.
In the above-described embodiment, the coencapsuiation of plastic packaging layer 110 and 130 chip 120 is described.In alternative embodiment
In, plastic packaging layer 130 can integrally encapsulate chip 120, or only cover the upper surface of chip 120, so as to save plastic packaging layer
110。
The perspective view of the encapsulation chip according to the utility model embodiment is shown respectively in Fig. 2 a and 2b, wherein in fig. 2 a
The overall structure of encapsulation chip is shown, removal encapsulates the top plastic packaging layer of chip to show the inside of encapsulation chip in figure 2b
Structure.In this application, encapsulation chip is that single package structure of the scribing to be separated into is carried out to package assembling.
Encapsulating chip 200 includes plastic packaging layer 110, chip 121, plastic packaging layer 130, metal column 140.Plastic packaging layer 110 and 130 point
Not Wei Yu chip 121 following above and, thus coencapsuiation chip 121.The upper surface of chip 121 is formed with pad 123.
Metal column 130 extends through plastic packaging layer 130.Metal column 130 includes first end and second end relative to each other, first end and chip
121 pad 123 contacts, and second end is exposed to outside plastic packaging layer 130, for providing external electrical connections.
Chip 121 can be circuit product chip, be also possible to mems chip or other chips, in the present embodiment, core
Piece 121 is circuit product chip, is e.g. suitable for single lithium battery charge protection chip.Chip 121 may include pad
123, the position that metal column corresponds to pad 123 is arranged.The first end of metal column is contacted with pad 123, the second end of metal column
For being electrically connected.The encapsulation chip of the utility model embodiment is applied to imitate in the relatively small circuit product chip of number of pads
Fruit is more excellent.The pad 123 of chip 121 can provide multiple terminals.As single lithium battery charge protection chip, generally include
Vdd terminal (power supply side), the end GND (ground terminal), the end OD (control discharge switch signal end), the end OC (control charge switch signal
End), the end CS (induced current end), the end TD (test lead).The end TD is one for reducing the terminal of test delay, in chip 121
It is connected to power supply when test, can reduce test delay, testing efficiency is substantially improved.
It is corresponding with the pad 123 of chip 121, it may include the first metal for test in multiple metal columns 140
Column 140a and the second metal column 140b for ground connection, the first metal column 140a are disposed proximate to the second metal column 140b,
After the encapsulation chip completes test, first metal column 140a and the second metal column 140b is interconnected using solder 151.
Multiple metal columns 140 can be formed by way of chemical plating, and material may include tin, gold etc..In this implementation
In example, multiple metal columns include the first metal column 140a for test and the second metal column 140b for ground connection, and first
Metal column 140a is disposed proximate to the second metal column 140b, can be separated by tiny slit between the two, is completed in encapsulation chip
The first metal column 140a and the second metal column 140b is mutually linked together after test.
Before testing, it is separated from each other between the first metal column 140a and the second metal column 140b, such as filling encapsulating compound.?
After the completion of test, the first metal column 140a and the second metal column 140b are connected to each other by solder 151, as shown in figures 2 a and 2b.
In the present embodiment, the shape of chip 121 is rectangle, and the first metal column 140a is set to the second metal column 140b
The center of the rectangle.First metal column 140a can be roughly the same with the second metal column 140b shape, and symmetrically sets
It sets.In the present embodiment, the first metal column 140a and the second metal column 140b is triangular prism, and the triangular prism is extremely
A few side is parallel to the side of the rectangle.
In addition, in the encapsulation chip 200 of the present embodiment, multiple metal columns can also include third metal column 140c, the
Four metal column 140d, fifth metal column 140e and the 6th metal column 140f.Wherein, third metal column 140c is for connecting power supply
Feeder ear, the 4th metal column 140d are filled for connecting control discharge switch signal end, fifth metal column 140e for connecting control
Electric switch signal end, the 6th metal column 140f is for connecting induced current end (charger end).Third metal column 140c, the 4th gold medal
Belong to the periphery setting that column 140d, fifth metal column 140e and the 6th metal column 140f correspond to chip 121.When chip 121 is in square
When shape, third metal column 140c, the 4th metal column 140d, fifth metal column 140e and the 6th metal column 140f be can be set
In the corner location of the rectangle.
In the present embodiment, the material of the second end of multiple metal columns is the stronger gold of weldability.The second of multiple metal columns
End can be more than or equal to its first end with the flush with outer surface of plastic packaging layer 130, the area of the second end of multiple metal columns
Area, convenient for welding or heat dissipation.
In the above-described embodiment, the coencapsuiation of plastic packaging layer 110 and 130 chip 121 is described.In alternative embodiment
In, plastic packaging layer 130 can integrally encapsulate chip 121, or only cover the upper surface of chip 121, so as to save plastic packaging layer
110。
In the above-described embodiment, the multiple metal columns 140 for describing chip 121 include the first metal column for test
140a and the second metal column 140b for ground connection, after the encapsulation chip completes test, using solder 151 by the first gold medal
Belong to column 140a and the second metal column 140b to interconnect.It in alternate embodiments, can be in multiple metal columns 140 of chip 121
The first metal column 140a for test is saved, the second metal column 140b for being used to be grounded is also used as calibrating terminal.
According to the encapsulation chip 200 of the utility model embodiment, using plastic packaging layer 110 and plastic packaging layer 130 by chip 121
It is encapsulated, so that chip 121 is isolated with external environment, reduces the influence for chip 121 such as steam in environment.
In encapsulation chip 200, the first end of multiple metal columns is contacted with chip 121, and second end is exposed to outside plastic packaging layer 130.Work as gold
When belonging to the first end and the contact pads of chip 121 of column, second end can be used for being electrically connected with other circuits.Metal column is compared
Plain conductor used in existing encapsulation can guarantee passing through for more high current, and can obtain smaller conducting resistance.Modeling
110 thickness of sealing and 130 thickness of plastic packaging layer can be 20 microns to 30 microns, so that the area and core of final encapsulation chip
The area of piece 121 is very close, meet 121 sized package of wafer level chip (Wafer Level Chip Scale Package,
WLCSP) the requirement of technique.In addition, the number of the pad 123 of chip 121 can be to be multiple, metal column can be for pad 123
Position setting, the second end of metal column can be formed with the flush with outer surface of plastic packaging layer 130, metal column by chemical plating, and
The material of second end is weldability metallic gold, so that encapsulation chip and external circuitry with circuit product chip 121 are more convenient
It welds and realizes electrical connection, when the hot zone of the first end of metal column and chip 121 contacts, second end can be used for chip
It radiates 121 hot zone.
Fig. 3 shows the flow chart of the manufacturing method of the utility model embodiment encapsulation chip 200, specifically includes step S101
To step S107.Fig. 4 a to Fig. 4 f shows the perspective view in each stage of the manufacturing method of encapsulation chip 200.
In step s101, the chip with multiple chips is provided.As described in fig. 4 a, chip 120 includes opposite first
Surface 120a and second surface 120b.
Preferably, in step s 102, chip 120 is carried out thinned.Chip 120 be thinned after thickness and final encapsulation at
The thickness of product is close.
In step s 103, form metal column 140 on chip 120, the metal column 140 include opposite first end and
Second end, the first end correspondence are contacted with the multiple chip on chip 120.The step of forming metal column 140 includes adopting
The metal column 140 is formed with chemical plating, and the material of the second end of metal column 140 is the stronger gold of weldability.
In this embodiment, the chip 121 in chip 120 is substantially rectangular in shape.Each chip 121 respectively includes more
A metal column 140, wherein the first metal column 140a and the second metal column 140b is set to the center of the rectangle, third metal
Column 140c, the 4th metal column 140d, fifth metal column 140e and the 6th metal column 140f are set to the turning position of the rectangle
It sets.First metal column 140a is disposed proximate to the second metal column 140b, can be separated by tiny slit between the two.
In step S104, scribing is carried out to form groove 122, as illustrated in fig. 4 c to chip 120.The scribing steps are for example
Along the dicing lane scribing chip 120 reserved between multiple chips, however, the scribing steps do not penetrate plastic packaging layer 110, Jin Jin
Groove 122 is formed between the chip 121 of chip 120, so that chip 121 is separated from each other.Multiple chips 121 are still integrally formed in
On the same chip 120, to whole to multiple chips 121 can be picked up in subsequent manufacturing process.
In step s105, plastic packaging layer 110 and 130 is covered each by the following above and of chip 120.110 He of plastic packaging layer
130 coencapsuiation chips 120, to form package assembling 100, as shown in fig 4e.The thickness of plastic packaging layer 110 and 130 is for example distinguished
It is 20 microns to 30 microns.
In the present embodiment, the thickness of plastic packaging layer 130 is greater than the height of metal column 140.Preferably, plastic packaging is being formed
Layer 130 after, further plastic packaging layer 130 is carried out it is thinned so that the second end of metal column 140 is exposed to outside plastic packaging layer 130.
Preferably, in step s 106, the chip 120 in package assembling 100 is tested.The step can test
Stage is to 120 integrated testability of chip, to improve the testing efficiency of package assembling.
In this embodiment, the first metal column 140a is, for example, dedicated calibrating terminal, and the second metal column 140b is for connecing
Ground.In test phase, the probe of test device 210 is connected to the first metal column 140a, to provide test signal or acquisition
Detect signal.
In step s 107, scribing is carried out to package assembling 100 and is separated into multiple encapsulation chips 200, as shown in fig. 4f.?
In this step, drawn along scheduled position scribing package assembling 100, such as along the dicing lane reserved between multiple chips
It cuts.The scribing step, which penetrates, successively penetrates plastic packaging layer 130, chip 120 and plastic packaging layer 110, so that chip 120 is together with plastic packaging layer
130 and plastic packaging layer 110 be separated from each other together.
The chip form of the encapsulation chip 200 is rectangle, and first metal column and second metal column are set to institute
The center of rectangle is stated, the third metal column, the 4th metal column, the fifth metal column and the 6th metal column are set
It is placed in the corner location of the rectangle.The maximization of distance between multiple metal columns may be implemented in the layout, to prevent circuit
Reliability that is short-circuit and improving encapsulation chip, makes full use of package area, is conducive to the miniaturization for encapsulating chip.
In above-mentioned the utility model embodiment, multiple chips respectively include multiple metal columns, including first for test
Metal column 140a and the second metal column 140b, the first metal column 140a and the second metal column 140b for ground connection are close to setting
It sets, the first metal column 140a and the second metal column 140b can be separated by by plastic packaging layer 120.In test phase, chip passes through the
One metal column 140a is connected with the test circuit for reducing delay of external circuitry, to reduce test delay, is substantially improved
Testing efficiency.By the second end of the second end of the first metal column 140a and the second metal column 140b after encapsulation chip completes test
It is welded to each other by solder 151, so that the first metal column 140a is mutually linked together with the second metal column 140b.This is practical
When novel encapsulation chip and other circuit structures encapsulates, without extra useless terminal, the property easy to use of encapsulation chip is improved,
Ensure the stabilization of performance.
In the utility model embodiment, third metal column 140c, the 4th metal column 140d, fifth metal column 140e and
Six metal column 140f are prism, third metal column 140c, the 4th metal column 140d, fifth metal column 140e and the 6th metal
At least one the respective side column 140f is parallel to the side of the rectangle, third metal column 140c, the 4th metal column 140d,
Five metal column 140e and at least one the respective side the 6th metal column 140f, with the first metal column 140a and the second metal
At least one side of one of column 140b is relative to each other and parallel to each other.In said structure, positioned at periphery metal column side
Face is opposite to each other and parallel with the side of central metal column, between the two not opposite protruding portion, to realize circumferential metal
The maximization of distance between column and central metal column can further have to avoid the reliability of short circuit and raising encapsulation chip
Conducive to the miniaturization of encapsulation chip.
In encapsulation chip, the second end that metal column is exposed to plastic packaging layer surface be can be according to chip surface pad locations
It is determining, as long as therefore the design of basis product chips solder joint it is different, the product shape difference encapsulated can in packaging appearance
Flexibly to change, the encapsulation chip of completion can with the Background Grid array packages of traditional wire-bonding package (Land Grid Array,
LGA), quad flat non-pin package (Quad Flat No-lead package, QFN), bilateral pin flat package (Dual
Flat package, DFN) shape is very close but smaller than the area of LGA, QFN, DFN of traditional wire-bonding package.
The center of the first metal column 140a of the present embodiment chip corresponding with the second metal column 140b is arranged, the two shape phase
Together, it and is symmetrically set, the first metal column 140a and the second metal column 140b are for example triangular prism, and described three
At least one side of prism is parallel to the side of the rectangle so that after the completion of test phase, the first metal column 140a with
Second metal column 140b's is welded to each other more convenient stabilization, further increases the reliability of encapsulation chip.
In above-described embodiment, before testing, pass through plastic packaging layer 130 between the first metal column 140a and the second metal column 140b
It is separated by, after the completion of test, the first metal column 140a and the second metal column 140b will the respective second ends by solder 151
Weld together.In other embodiments, the first metal column and the second metal column can also be other arrangements.
In the above description, well known structural element and step are not described in detail.But this field
It will be appreciated by the skilled person that can be by various technological means, to realize corresponding structural element and step.In addition, for shape
At identical structural element, those skilled in the art be can be devised by and process as described above not fully identical side
Method.In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot have
It is used in combination sharply.
The embodiments of the present invention are described above.But the mesh that these embodiments are merely to illustrate that
, and it is not intended to limitation the scope of the utility model.The scope of the utility model is limited by appended claims and its equivalent
It is fixed.The scope of the utility model is not departed from, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications
It should all fall within the scope of the utility model.
Claims (23)
1. a kind of encapsulation chip characterized by comprising
Chip；
First plastic packaging layer, covers the chip；And
Multiple metal columns respectively include opposite first end and second end,
Wherein, the first end of the multiple metal column is contacted with the chip, and the second end is exposed to first modeling
Outside sealing.
2. encapsulation chip according to claim 1, which is characterized in that the first plastic packaging layer encapsulates the chip.
3. encapsulation chip according to claim 1, which is characterized in that further include the second plastic packaging layer, the first plastic packaging layer
With chip described in the second plastic packaging layer coencapsuiation.
4. encapsulation chip according to claim 1, which is characterized in that the multiple metal column is respectively column, section shape
Shape is any in cylinder, semicircle, prismatic, polygon.
5. encapsulation chip according to claim 1, which is characterized in that the height of the multiple metal column is 1 micron -200
Micron.
6. encapsulation chip according to claim 5, which is characterized in that the height of the multiple metal column is 20 microns.
7. encapsulation chip according to claim 1, which is characterized in that the multiple metal column is made of nickel, and described
The second end plating weldability metal of multiple metal columns or its alloy.
8. encapsulation chip according to claim 7, which is characterized in that the weldability metal is in gold, silver and copper
Any one.
9. encapsulation chip according to claim 1, which is characterized in that the multiple metal column is formed by chemical plating.
10. encapsulation chip according to claim 1, which is characterized in that the chip respectively includes pad, the multiple gold
The first end of category column and the contact pads.
11. encapsulation chip according to claim 1, which is characterized in that the chip is charging protection chip for lithium battery.
12. encapsulation chip according to claim 3, which is characterized in that the first plastic packaging layer and the second plastic packaging layer
Respectively by any one in epoxies sealing, organic silicon sealing, polyurethane sealing and ultraviolet photo-curing sealing
Composition.
13. encapsulation chip according to claim 3, which is characterized in that the first plastic packaging layer and the second plastic packaging layer
Thickness is respectively 20 microns to 30 microns.
14. encapsulation chip according to claim 1, which is characterized in that the multiple metal column includes for test
One metal column and the second metal column for ground connection, first metal column and second metal column are disposed proximate to, in institute
Encapsulation chip is stated to complete first metal column and the second metal pole interconnection after testing.
15. encapsulation chip according to claim 14, which is characterized in that first metal column and second metal column
Between be separated by by the first plastic packaging layer, it is described encapsulation chip complete test after first metal column second end and institute
The second end for stating the second metal column welds together.
16. encapsulation chip according to claim 14, which is characterized in that first metal column and second metal column
Between be separated by by air, it is described encapsulation chip complete test after first metal column second end and second metal
The second end of column welds together.
17. encapsulation chip according to claim 14, which is characterized in that the shape of the chip be rectangle, described first
Metal column and second metal column are set to the center of the rectangle.
18. encapsulation chip according to claim 17, which is characterized in that first metal column and second metal column
Shape is identical, and is symmetrically set.
19. encapsulation chip according to claim 17, which is characterized in that first metal column and second metal column
It is prism, a side of first metal column and second metal column is relative to each other and is parallel to the side of the rectangle
Side.
20. encapsulation chip according to claim 14, which is characterized in that the multiple metal column further include:
For connecting the third metal column of power supply side；
For connecting the 4th metal column of control discharge switch signal end；
For connecting the fifth metal column of control charge switch signal end；And
For connecting the 6th metal column at induced current end.
21. encapsulation chip according to claim 20, which is characterized in that the third metal column, the 4th metal column,
The fifth metal column and the 6th metal column are set to the corner location of the rectangle.
22. encapsulation chip according to claim 21, which is characterized in that the third metal column, the 4th metal column,
The fifth metal column and the 6th metal column are prism, the third metal column, the 4th metal column, described
Five metal columns and described at least one respective side of 6th metal column are parallel to the side of the rectangle.
23. encapsulation chip according to claim 21, which is characterized in that the third metal column, the 4th metal column,
The fifth metal column and described at least one respective side of 6th metal column, with first metal column and described second
At least one side of one of metal column is relative to each other and parallel to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820414812.4U CN208433406U (en) | 2018-03-26 | 2018-03-26 | Encapsulate chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820414812.4U CN208433406U (en) | 2018-03-26 | 2018-03-26 | Encapsulate chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208433406U true CN208433406U (en) | 2019-01-25 |
Family
ID=65105358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820414812.4U Active CN208433406U (en) | 2018-03-26 | 2018-03-26 | Encapsulate chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208433406U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389845A (en) * | 2018-03-26 | 2018-08-10 | 杭州士兰微电子股份有限公司 | Encapsulate chip and its manufacturing method |
-
2018
- 2018-03-26 CN CN201820414812.4U patent/CN208433406U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389845A (en) * | 2018-03-26 | 2018-08-10 | 杭州士兰微电子股份有限公司 | Encapsulate chip and its manufacturing method |
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