CN109103185A - A kind of bi-directional ESD protective device of anti-latch-up - Google Patents
A kind of bi-directional ESD protective device of anti-latch-up Download PDFInfo
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- CN109103185A CN109103185A CN201810973152.8A CN201810973152A CN109103185A CN 109103185 A CN109103185 A CN 109103185A CN 201810973152 A CN201810973152 A CN 201810973152A CN 109103185 A CN109103185 A CN 109103185A
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- buried layer
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- 230000001681 protective effect Effects 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 abstract description 20
- 238000013461 design Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 102000005741 Metalloproteases Human genes 0.000 description 1
- 108010006035 Metalloproteases Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002650 habitual effect Effects 0.000 description 1
- 230000009021 linear effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The present invention provides the bi-directional ESD protective device of anti-latch-up a kind of, comprising: P type substrate, N-type region, the first contact zone P+, the first contact zone N+, the first P+ isolated area, the first p type buried layer；2nd contact zone P+, the 2nd contact zone N+, the 2nd P+ isolated area, the second p type buried layer；First contact zone N+, the first contact zone P+ are shorted to form metal anode by metal；2nd contact zone N+, the 2nd contact zone P+ are shorted by metal and to form metal anode, and the present invention can adjust maintenance electric current by adjusting p type buried layer concentration below the contact zone P+, to avoid device that latch occurs；The presence of p type buried layer can change current distribution, and device IV curve is made to show the characteristic of multiple snapback, improve robustness of the device under esd pulse electric current.
Description
Technical field
The invention belongs to Electronics Science and Technology fields, are mainly concerned with integrated circuit on piece electrostatic leakage
(ElectroStatic Discharge, referred to as ESD) guard technology particularly relates to a kind of while having low-power consumption,
Strong anti-latch (latch-up) ability, the ESD protection device for high voltage integrated circuit.
Background technique
ESD, that is, electrostatic leakage is the generally existing phenomenon of nature.ESD is present in each corner of people's daily life.
It and be exactly electrical phenomena habitual in this way for accurate integrated circuit is fatal threat.However, for
For chip through completing encapsulation, each power supply/input/output pin just becomes manikin (HBM), machine mould (MM),
The channel of the entrance of human metalloproteinase model (HMM) isopulse electric current.Strong esd pulse not only results in the hard failure of chip, also
It can induce due to the design of ESD protection device improper brought various effect (such as latch-up latch-up, soft leakage
Soft failure etc.).In addition to this, in the manufacturing process of chip, the ESD failure of only only a few can directly be detected.
Most ESD damage, which can't generate the performance of chip, to be significantly affected, by standard testing, to enter eventually into client
In hand.This kind of chip " goes to work braving one's illness " in various applications, the reliability of system where constantly threaten it.
For high voltage integrated circuit, due to the presence of class latch-up (latch-up like), LDMOS structure is (such as
Shown in Fig. 1) ESD protection generally can not be directly used in.And the maintenance voltage of LDMOS is such as promoted to VDD by some modes
More than voltage, to meet the traditional design window of ESD protection device.Although such high maintenance voltage design can be eliminated
Latch-up phenomenon, but the voltage that also can improve device ON state simultaneously when is born is to improve power, along under high current
The robustness of the influence of Ke Erke effect, LDMOS itself will be greatly reduced.
In order to enable LDMOS has high robustness, the raising ESD robust that more finger-like layout designs theoretically can be linear
Property, but influenced due to strong snapback plus fabrication error etc..Each finger may not be opened simultaneously.Therefore more
The relevant technologies (the ESD grid coupling technique proposed in such as IEDM) very good solution problem.However, there is strong ESD
It is required that high-voltage applications chip in, the area of ESD device may be very big, to improve manufacturing cost.Therefore ESD device domain
Area avoids latch-up and strong ESD robustness three from constituting the contradictory relation for being difficult to compromise.That is: it needs without door bolt
Lock work can then reduce robustness, and the ESD robustness for if desired improving no latch devices then needs to increase area.
In order to solve this problem, result of study shows to improve the class for maintaining electric current that can solve device to a certain extent
Latch problem.If the maximum current that power supply provides not can guarantee the minimal maintenance current requirements of ESD device, latch-up will not
It can generate.This just provides a new approaches without the design of latch ESD protection device for low maintenance voltage.ESD protection of the present invention
Device breaches the high maintenance voltage design window of habit, proposes to carry out device design with high maintenance current design window.Cause
This, the maintenance voltage of the device is lower than the ESD protection device of traditional high maintenance voltage, release esd pulse when power consumption also therewith
It reduces, improves the ESD robustness of device.Specifically, the present invention passes through one layer of high concentration p-type on the basis of traditional SCR
Buried layer realizes trigger voltage and maintains current adjustment, the features such as power of releasing is low, robustness is high.
Summary of the invention
The problem to be solved in the present invention is: realize the accurate and quick triggering (trigger voltage is suitable) of ESD device, it is high
The features such as maintenance electric current, low ESD power consumption, high robustness.
For achieving the above object, technical solution of the present invention is as follows:
A kind of bi-directional ESD protective device of anti-latch-up, comprising: P type substrate 00, the N-type region above P type substrate
01；The first contact zone P+ 211 on the left of 01 inner upper of N-type region, the first N+ on the left of 01 inner upper of N-type region connect
Touch area 111, the first P+ isolated area 221 on the left of 01 inner upper of N-type region, the first p type buried layer inside N-type region 01
231；Wherein, the first contact zone P+ 211 is located at 111 left side of the first contact zone N+, and the first P+ isolated area 221 is located at the first N+ contact
111 right side of area, the first p type buried layer 231 are located under the first contact zone N+ 111, the first contact zone P+ 211, the first P+ isolated area 221
It is square and tangent with the first contact zone N+ 111, the first contact zone P+ 211, the first P+ isolated area 221；Positioned at 01 inner upper of N-type region
2nd contact zone P+ 212 on right side, is located in N-type region 01 the 2nd contact zone N+ 112 on the right side of 01 inner upper of N-type region
2nd P+ isolated area 222 of portion's upper right is located at 01 the second p type buried layer 232 of inside of N-type region；Wherein, the 2nd contact zone P+
212 are located at 112 right side of the first contact zone N+, and the 2nd P+ isolated area 222 is located at 112 left side of the first contact zone N+, the second p type buried layer
232 be located at the 2nd contact zone N+ 112, the 2nd contact zone P+ 212, the lower section of the 2nd P+ isolated area 222 and with the 2nd contact zone N+
112, the 2nd contact zone P+ 212, the 2nd P+ isolated area 222 are tangent；First contact zone N+ 111 passes through with the first contact zone P+ 211
Metal is shorted to form metal anode 31；2nd contact zone N+ 112, the 2nd contact zone P+ 212 are shorted to form metal yin by metal
Pole 32；N-type region 01 is the area NWELL or N-type epitaxy layer.
It is preferred that the first contact zone N+ 111, the first contact zone P+ 211 and the first P+ isolated area 221 pass through metal
Short circuit forms metal anode 31；2nd contact zone N+ 112, the 2nd contact zone P+ 212 and the 2nd P+ isolated area 222 are short by metal
It connects to form metal anode 32.
It is preferred that 01 upper surface of N-type region is equipped with the 3rd contact zone P+ 223, wherein the 3rd contact zone P+ 223 is located at
It is between first P+ isolated area 221 and the 2nd P+ isolated area 222 and nontangential；Third p-type is equipped with below 3rd contact zone P+ 223 to bury
Layer 233.
It is preferred that device upper surface is equipped with gate oxide 030, and 030 left side of gate oxide is isolated with the first P+
Area 221 is tangent, the right and the 2nd P+ isolated area 222 are tangent, and gate oxide 030 is equipped with polysilicon or metal gates 040.
It is preferred that each doping type accordingly becomes opposite doping in the device, i.e. p-type doping becomes N-type
N-type doping becomes p-type doping while doping.
Beneficial effects of the present invention are 1: high maintenance electric current ESD protection device proposed by the present invention can be by improving electrode
P type buried layer concentration and thickness below contact zone adjust maintenance electric current, to avoid latch-up.The presence of 2:P type buried layer
So that device IV curve is showed the characteristic of multiple snapback, improves robustness of the device under esd pulse electric current.
Detailed description of the invention
Fig. 1 (a) is traditional high maintenance voltage ESD design window；
Fig. 1 (b) is high maintenance electric current ESD design window；
Fig. 2 is the two-way SCR device structure chart of tradition；
Fig. 3 is the structure chart of embodiment 1；
Fig. 4 is the structure chart of embodiment 2；
Fig. 5 is the structure chart of embodiment 3；
Fig. 6 is the structure chart of embodiment 4；
Fig. 7 is embodiment 1 and the two-way SCR device I-V characteristic simulation comparison figure of tradition；
Fig. 8 is HBM hybrid simulation circuit diagram；
Fig. 9 is the time-domain simulation results of embodiment 1；
00 is P type substrate, and 01 is N-type region；111 be the first contact zone N+, and 211 be the first contact zone P+, and 221 be the first P+
Isolated area, 231 be the first p type buried layer, and 223 be the 3rd contact zone P+, and 233 be third p type buried layer, and 030 is gate oxide, 040
It is the area PWELL for polysilicon or metal gates, 20,112 be the 2nd contact zone N+, and 212 be the 2nd contact zone P+, and 222 be the 2nd P
+ isolated area, 232 be the second p type buried layer, and 31 be metal anode, and 32 be metallic cathode.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
As shown in figure 3, the present embodiment device architecture, comprising: P type substrate 00, the N-type region 01 above P type substrate；Position
The first contact zone P+ 211 on the left of 01 inner upper of N-type region, the first contact zone N+ on the left of 01 inner upper of N-type region
111, the first P+ isolated area 221 on the left of 01 inner upper of N-type region, the first p type buried layer 231 inside N-type region 01；
Wherein, the first contact zone P+ 211 is located at 111 left side of the first contact zone N+, and the first P+ isolated area 221 is located at the first contact zone N+
111 right sides, the first p type buried layer 231 are located at the first contact zone N+ 111, the first contact zone P+ 211,221 lower section of the first P+ isolated area
And it is tangent with the first contact zone N+ 111, the first contact zone P+ 211, the first P+ isolated area 221；It is right positioned at 01 inner upper of N-type region
2nd contact zone P+ 212 of side, is located inside N-type region 01 the 2nd contact zone N+ 112 on the right side of 01 inner upper of N-type region
2nd P+ isolated area 222 of upper right is located at 01 the second p type buried layer 232 of inside of N-type region；Wherein, the 2nd contact zone P+ 212
Positioned at 112 right side of the first contact zone N+, the 2nd P+ isolated area 222 is located at 112 left side of the first contact zone N+, the second p type buried layer 232
Positioned at the 2nd contact zone N+ 112, the 2nd contact zone P+ 212, the lower section of the 2nd P+ isolated area 222 and with the 2nd contact zone N+ 112, the
Two contact zones P+ 212, the 2nd P+ isolated area 222 are tangent；First contact zone N+ 111 is short by metal with the first contact zone P+ 211
It connects to form metal anode 31；2nd contact zone N+ 112, the 2nd contact zone P+ 212 are shorted to form metallic cathode 32 by metal；N
Type area 01 is the area NWELL or N-type epitaxy layer.
The working principle of this example are as follows:
When anode ESD voltage rises, device is first at the PN junction that the 2nd P+ isolated area 222/N type area 01 of surface is constituted
Puncture.Hole current after breakdown flow through the 2nd P+ isolated area 222, the second p type buried layer 232, the 2nd contact zone N+ 112 with
And the 2nd contact zone P+ 212, it is taken away by metallic cathode 32.Just most of electronic current when breakdown will flow through N-type region 01, first
P type buried layer 231, the first contact zone N+ 111, are taken away by metal anode.Due to the presence of the second p type buried layer 232, electric hole current
Low-resistance region is walked, current convergence will occur in the 2nd P+ isolated area 222 and 232 left side of the second p type buried layer.Correspondingly, since kirk is imitated
Answer 232 left side of the second p type buried layer that a peak electric field will occur, which makes the maintenance voltage V of device when low currenthCompared with
It is high.
Although when the electric current that flow through on the second p type buried layer 232 increases to certain value, so that the 2nd contact zone N+ 112 and the
Pressure drop between two p type buried layers 232 reaches 0.7V, then the PN junction is opened.But since the concentration of the second p type buried layer 232 is higher, and
When low current the 2nd contact zone N+ 112 be injected into the second p type buried layer 232 electronics it is less, will be all by the second p type buried layer 232
Compound, so that can get over without electronics to N-type region 01, the positive feedback that such SCR mutually provides base area electric current can not yet
It carries out.So having to when electric current is sufficiently large, just there is electronics that can get over the second p type buried layer 232 and reach N-type region 01, accordingly
SCR positive feedback open, device maintenance voltage also decreases.
In order to prove that the device can work in the case where VDD is higher than its maintenance voltage and not occur latch-up phenomenon,
It is now verified by circuit hybrid simulation.
Fig. 7 is embodiment 1 and the two-way SCR device I-V curve simulation comparison of tradition, wherein Conv.SCR is that tradition is two-way
IV curve obtained by SCR device structure simulation, This proposed SCR are that embodiment 1 emulates gained IV curve.From simulation result
As can be seen that the two-way SCR device of tradition cannot achieve high maintenance electric current, and the maintenance electric current of embodiment 1 is obviously more two-way than tradition
SCR high.
Fig. 8 is manikin (HBM) artificial circuit figure.It uses the part HBM circuit in the circuit left-hand broken line frame
Esd pulse waveform when simulating human body static electricity discharge；Right loop is the power supply circuit of the device, wherein HV
Source is supply voltage, RLFor load resistance, DUT is test module, and passes through diode-isolated HBM circuit and HV
The circuit source, it is ensured that the esd pulse that HBM circuit is generated does not interfere with HV source.
Fig. 9 is that hybrid simulation result curve is immunized in the latch of embodiment 1, and HBM circuit simulation obtains the curve as shown in Figure 8
's.It can be seen that latch will occur for the two-way SCR device of tradition after the analog waveform of input HBM, cause device in HBM waveform
Later can not normal turn-off so that supply voltage VDD is clamped at 15V or less.And one kind that the patent is proposed is anti-
The bi-directional ESD protective device of latch-up, although can also be clamped to a slightly below supply voltage VDD current potential at 180ns
ESD is carried out to release, but due to the maintenance electric current I of the devicehIt is very high, it, only can not with supply voltage after esd pulse subsides
The electric current in entire circuit is set to maintain IhMore than, to achieve the purpose that latch is immune.
Embodiment 2
As shown in figure 4, the difference of the device architecture and embodiment 1 of the present embodiment is: the first contact zone N+ 111, the first P
+ contact zone 211 and the first P+ isolated area 221 are shorted to form metal anode 31 by metal；2nd contact zone N+ 112, the 2nd P+
Contact zone 212 and the 2nd P+ isolated area 222 are shorted to form metal anode 32 by metal.
Embodiment 3
As shown in figure 5, the main distinction of the present embodiment and embodiment 1 is: 01 upper surface of N-type region is contacted equipped with the 3rd P+
Area 223, wherein the 3rd contact zone P+ 223 is between the first P+ isolated area 221 and the 2nd P+ isolated area 222 and nontangential；The
Third p type buried layer 233 is equipped with below three contact zones P+ 223.
Embodiment 4
As shown in fig. 6, the difference of the present embodiment and embodiment 1 is: device upper surface is equipped with gate oxide 030, and grid
030 left side of oxide layer and the tangent, the right of the first P+ isolated area 221 and the 2nd P+ isolated area 222 are tangent, set on gate oxide 030
There are polysilicon or metal gates 040.
Claims (5)
1. a kind of bi-directional ESD protective device of anti-latch-up, characterized by comprising: P type substrate (00) is located at P type substrate
The N-type region (01) of top；The first contact zone P+ (211) on the left of N-type region (01) inner upper is located in N-type region (01)
First contact zone N+ (111) of portion's upper left, the first P+ isolated area (221) being located on the left of N-type region (01) inner upper, position
In internal the first p type buried layer (231) of N-type region (01)；Wherein, the first contact zone P+ (211) is located at the first contact zone N+ (111)
Left side, the first P+ isolated area (221) are located on the right side of the first contact zone N+ (111), and the first p type buried layer (231) is located at the first N+ and connects
Touch area (111), the first contact zone P+ (211), below the first P+ isolated area (221) and with the first contact zone N+ (111), the first P+
Contact zone (211), the first P+ isolated area (221) are tangent；The 2nd contact zone P+ on the right side of N-type region (01) inner upper
(212), it is located at the 2nd contact zone N+ (112) on the right side of N-type region (01) inner upper, is located on the right side of N-type region (01) inner upper
The 2nd P+ isolated area (222), be located at N-type region (01) internal second p type buried layer (232)；Wherein, the 2nd contact zone P+ (212)
On the right side of the first contact zone N+ (112), the 2nd P+ isolated area (222) is located on the left of the first contact zone N+ (112), the second p-type
Buried layer (232) is located at the 2nd contact zone N+ (112), the 2nd contact zone P+ (212), below the 2nd P+ isolated area (222) and with the
Two contact zones N+ (112), the 2nd contact zone P+ (212), the 2nd P+ isolated area (222) are tangent；First contact zone N+ (111) and the
One contact zone P+ (211) is shorted to form metal anode (31) by metal；2nd contact zone N+ (112), the 2nd contact zone P+
(212) it is shorted to form metallic cathode (32) by metal；N-type region (01) is the area NWELL or N-type epitaxy layer.
2. the bi-directional ESD protective device of anti-latch-up according to claim 1 a kind of, it is characterised in that: the first N+ connects
Touching area (111), the first contact zone P+ (211) and the first P+ isolated area (221) are shorted to form metal anode (31) by metal；The
Two contact zones N+ (112), the 2nd contact zone P+ (212) and the 2nd P+ isolated area (222) are shorted to form metal anode by metal
(32)。
3. the bi-directional ESD protective device of anti-latch-up according to claim 1 a kind of, it is characterised in that: N-type region (01)
Upper surface is equipped with the 3rd contact zone P+ (223), wherein the 3rd contact zone P+ (223) is located at the first P+ isolated area (221) and the 2nd P
It is between+isolated area (222) and nontangential；Third p type buried layer (233) are equipped with below 3rd contact zone P+ (223).
4. the bi-directional ESD protective device of anti-latch-up according to claim 1 a kind of, it is characterised in that: table on device
Face is equipped with gate oxide (030), and gate oxide (030) left side and the first P+ isolated area (221) is tangent, the right and the 2nd P+ every
Tangent from area (222), gate oxide (030) is equipped with polysilicon or metal gates (040).
5. the bi-directional ESD protective device of anti-latch-up according to claim 1 a kind of, it is characterised in that: the device
In each doping type accordingly become opposite doping, i.e., n-type doping becomes p-type doping while p-type doping becomes n-type doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810973152.8A CN109103185A (en) | 2018-08-24 | 2018-08-24 | A kind of bi-directional ESD protective device of anti-latch-up |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810973152.8A CN109103185A (en) | 2018-08-24 | 2018-08-24 | A kind of bi-directional ESD protective device of anti-latch-up |
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| CN109103185A true CN109103185A (en) | 2018-12-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080309394A1 (en) * | 2005-07-08 | 2008-12-18 | Texas Instruments Incorporated | Guardringed scr esd protection |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
| US9343558B1 (en) * | 2015-05-08 | 2016-05-17 | Global Unichip Corporation | Silicon controlled rectifier |
-
2018
- 2018-08-24 CN CN201810973152.8A patent/CN109103185A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080309394A1 (en) * | 2005-07-08 | 2008-12-18 | Texas Instruments Incorporated | Guardringed scr esd protection |
| US9343558B1 (en) * | 2015-05-08 | 2016-05-17 | Global Unichip Corporation | Silicon controlled rectifier |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
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Application publication date: 20181228 |