CN109102838A - Built-in self test engine - Google Patents
Built-in self test engine Download PDFInfo
- Publication number
- CN109102838A CN109102838A CN201810840386.5A CN201810840386A CN109102838A CN 109102838 A CN109102838 A CN 109102838A CN 201810840386 A CN201810840386 A CN 201810840386A CN 109102838 A CN109102838 A CN 109102838A
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- self test
- engine
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of built-in self test engines, it is related to semiconductor integrated circuit technology, the built-in self test engine includes the first sub- built-in self test engine, second sub- built-in self test engine and a register, the register connects the first sub- built-in self test engine and the second sub- built-in self test engine, the first sub- built-in self test engine includes an interface, for connecting a memory, the second sub- built-in self test engine includes an interface, for connecting a memory, so that the built-in self test engine supports multiple types memory and different testing algorithms.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit technology more particularly to a kind of memory design for Measurability technologies.
Background technique
In semiconductor integrated circuit, memory (such as Static RAM and dynamic RAM) accounts for very big
Area has significant impact to the performance of entire integrated circuit.How to carry out test to memory is a crucial design work
Make.Currently, common test method is built-in self-test (BIST, Built-in Self Test), built-in self-test is to set
Timing is implanted into related functional circuits for providing the technology of selftest function in circuit.
However, built-in self-test need to use different tests for different type of memory or different testing requirements
Algorithm.In this way, the built-in self-test circuit of each memory wants individually designed, and inflexible, it is specific that some can only be run
Algorithm, if midway needs to redesign the circuit of built-in self test engine, increase test because test needs replacing algorithm
Time and cost of labor.
Therefore it in semiconductor integrated circuit, needs to design and a kind of supports multiple types memories and difference testing algorithm
General built-in self test engine.
Summary of the invention
The purpose of the present invention is to provide a kind of built-in self test engine, the built-in self test engine is made to support multiple types
Memory and different testing algorithms.
Built-in self test engine provided by the invention, comprising: the first sub- built-in self test engine, the second sub- built-in self-test
Engine and a register, the register connects the first sub- built-in self test engine and the second sub- built-in self-test draws
It holds up, the first sub- built-in self test engine includes an interface, and for connecting a memory, the second sub- built-in self-test draws
It holds up including an interface, for connecting a memory.
Further, in the described first sub- built-in self test engine and the second sub- built-in self test engine wherein
One of be leading engine, engine supplemented by another.
Further, under default conditions, the first sub- built-in self test engine is leading engine；Second son is built-in
Engine supplemented by Selftest Engine.
Further, the register includes Bit2, when Bit2 is set as 1, the second sub- built-in self test engine
As leading engine, the first sub- built-in self test engine becomes auxiliary engine.
Further, the register connects a sub- built-in self test engine, and connects another son by a phase inverter
Built-in self test engine.
Further, the memory is single port memory, and the memory only connects the leading engine.
Further, the memory is twoport or two mouthfuls of memories, and the Single port of the memory passes through described the
The interface of one sub- built-in self test engine connects the first sub- built-in self test engine, the another port of the memory
The second sub- built-in self test engine is connected by the interface of the described second sub- built-in self test engine.
Further, the Single port of memory is master port, and supplemented by another port port, under default conditions, described the
One sub- built-in self test engine is leading engine, connects the master port of memory；The second sub- built-in self test engine is
Auxiliary engine connects the auxiliary port of memory.
Further, the described first sub- built-in self test engine and the second sub- built-in self test engine include posting
Buffer module, sub- built-in self test engine control module, address generator, number generator, clock and control signal generator
And data comparator.
Further, the interface of the described first sub- built-in self test engine connects the first sub- built-in self-test
The address generator in engine；The interface connection of the second sub- built-in self test engine second son is built-in certainly
The address generator in testing engine.
Further, single port testing algorithm or twoport testing algorithm are realized by configuring the register module.
Further, the register connects the sub- built-in self test engine control in described one sub- built-in self test engine
Molding block, and the sub- built-in self test engine in another sub- built-in self test engine is connected by the phase inverter and controls mould
Block.
Built-in self test engine provided by the invention, by including the first sub- built-in self-test in built-in self test engine
Engine and the second sub- built-in self test engine, then can support the test to single port memory, can also support to deposit twoport or two mouthfuls
Various single port or twoport testing algorithm can be achieved accordingly, make being more widely applied for built-in self test engine for the test of reservoir；
And good corresponding register is configured in practical applications, so that it may directly use, considerably reduce the electricity of built-in self test engine
The design time and cost of labor on road.
Detailed description of the invention
Fig. 1 is the built-in self test engine schematic diagram of one embodiment of the invention.
Fig. 2 is the schematic diagram of the sub- built-in self test engine of one embodiment of the invention.
Fig. 3 is a 9N March algorithm schematic diagram.
The reference numerals are as follows for main element in figure:
100, built-in self test engine；110, the first sub- built-in self test engine；120, the second sub- built-in self test engine；
130, register；112,122, interface.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In one embodiment of the invention, a kind of built-in self test engine is provided.Referring to Fig. 1, Fig. 1 is one embodiment of the invention
Built-in self test engine schematic diagram.As shown in Figure 1, built-in self test engine 100 of the invention includes the first sub- built-in self-test
Engine 110, the second sub- built-in self test engine 120 and a register 130 are tried, register 130 connects the first sub- built-in self-test
Engine 110 and the second sub- built-in self test engine 120, the first sub- built-in self test engine 110 includes an interface 112, for connecting
A memory is connect, the second sub- built-in self test engine 120 includes an interface 122, for connecting a memory.
The memory mentioned in above-described embodiment can be Static RAM or dynamic RAM.
Referring to Fig. 2, Fig. 2 is the schematic diagram of the sub- built-in self test engine of one embodiment of the invention.As shown in Fig. 2, the
One sub- built-in self test engine 110 and the second sub- built-in self test engine 120 draw including register module, sub- built-in self-test
Hold up control module, address generator, number generator, clock and control signal generator and data comparator.First son is built-in
The interface 112 of Selftest Engine 110 connects the address generator in the first sub- built-in self test engine 110；Second son is built-in certainly
The interface 122 of testing engine 120 connects the address generator in the second sub- built-in self test engine 120.
In an embodiment of the present invention, in the first sub- built-in self test engine 110 and the second sub- built-in self test engine 120
One of be leading engine, engine supplemented by another.In an embodiment of the present invention, leading engine can do read operation and can also do
Write operation, auxiliary engine can only do read operation.Under default conditions, the first sub- built-in self test engine 110 is leading engine；In second son
Build engine supplemented by Selftest Engine 120.
Wherein, register 130 is used to be arranged the attribute of auxiliary engine, including Bit2.Bit2 is for being arranged cutting for major-minor engine
It changes, if Bit2 is set as 1, the second sub- built-in self test engine 120 becomes leading engine, and the first sub- built-in self test engine
110 become auxiliary engine.In an embodiment of the present invention, register 130 connects a sub- built-in self test engine, and passes through a reverse phase
Device connects another sub- built-in self test engine, and more specifically, it is built-in that register 130 connects the son in a sub- built-in self test engine
Selftest Engine control module, and the sub- built-in self test engine in another sub- built-in self test engine is connected by a phase inverter
Control module.As register 130 connect the first sub- built-in self test engine 110, and by a phase inverter connection second son it is built-in
Selftest Engine 120 then can make one of them sub- built-in self test engine leading engine by the way that Bit2 is arranged, and another height is built-in
Engine supplemented by Selftest Engine.
Register 130 further includes Bit0, and when Bit0 is set as 0, auxiliary engine does BL address offset；It is auxiliary when Bit0 is set as 1
Engine does WL address offset.
In an embodiment of the present invention, if memory is single port memory, memory only connects leading engine, according to test
Register module in algorithm configuration leading engine, clock and control signal generator, which will issue corresponding test and excitation and be sent to, deposits
Reservoir reads data from memory, and the data of reading is sent to the data comparator in leading engine and are compared, and so tests
The performance of memory.Such as, by default, then memory is connected by the interface 112 of the first sub- built-in self test engine 110
First sub- built-in self test engine 110, at this point, memory is not connected to the second sub- built-in self test engine 120.According to testing algorithm
The register module in the first sub- built-in self test engine 110 is configured, clock and control signal generator will issue accordingly
Test and excitation is sent to memory, reads data from memory, and the data of reading are sent to the number in built-in self test engine 110
It is compared according to comparator, so tests the performance of memory.
In an embodiment of the present invention, if memory is twoport or two mouthfuls of memories, the wherein Single port of memory is logical
The interface 112 for crossing the first sub- built-in self test engine 110 connects the first sub- built-in self test engine 110, the other end of memory
Mouth connects the second sub- built-in self test engine 120 by the interface 122 of the second sub- built-in self test engine 120.In the present invention one
In embodiment, the Single port of memory is master port, port supplemented by another port.Under default conditions, the first sub- built-in self-test
Engine 110 is leading engine, connects the master port of memory；Engine supplemented by second sub- built-in self test engine 120 connects memory
Auxiliary port.According to testing algorithm configure the first sub- built-in self test engine 110 in register module and second son it is built-in from
Register module in testing engine 120, clock and control signal generator and in the first sub- built-in self test engine 110
Clock and control signal generator in two sub- built-in self test engines 120 will issue corresponding test and excitation and be sent to storage
Device reads data from memory, and by the data of reading be sent to data comparator in the first sub- built-in self test engine 110 and
Data comparator in second sub- built-in self test engine 120 is compared, and so tests the performance of memory.
Register 130 further includes Bit1, and whether Bit1, which does data for auxiliary engine to be arranged, is compared, if auxiliary when being set as 1 draw
It holds up and does data and compare, if being set as not comparing when 0.Then for twoport or two mouthfuls of memories, under default conditions, if Bit1 is arranged
It is 1, then the second sub- built-in self test engine 120 does data and compares, if Bit2 is set as 1, the first sub- built-in self test engine
110, which do data, compares.
Testing algorithm of the invention can be the test of the single port such as All0/All1, CheckBoard, March15N or March22N
The twoports testing algorithm such as algorithm or MMCA or MarchCn-.
The each algorithm of march algorithm description is used as follows, referring to Fig. 3, Fig. 3 is a 9N March algorithm schematic diagram.Such as
Shown in Fig. 3, a march algorithm by several march element (ME:march element) Mn (such as: M0, M1 ..., M4)
It constitutes, each march element is made of a series of operation OP (such as OP0 and OP2) to each unit again, is operated to individual unit
Aforesaid operations are repeated to next unit according to certain addressing order after the completion, then proceed to the behaviour of next march element
Make.March algorithm can indicate with specific symbol, and a complete march algorithm by braces { ... } by being bracketed
March element is constituted.Each march element with ↑ (...) indicate, wherein ↑ represent addressing order, it includes ↑ (address rises suitable
Sequence), ↓ (address descending order) and(arbitrary address sequence).It is the operation of a series of pairs of units, including w0 in round bracket (...)
(writing 0), w1 (writing 1), r0 (reading 0) and r1 (reading 1).
In an embodiment of the present invention, it includes register that the first built-in self test engine, which posts the register module in 110,
ACR1, it includes register ACR2 that the second built-in self test engine, which posts the register module in 120, is matched as follows to two registers
It sets and does as described below:
ACR1 is for configuring each March element.Low 4 numbers for indicating March element in the algorithm of ACR1,
If low four are 4 ' b0000, indicate there was only 1 March element, 4 ' b1111 indicate 16 March elements.ACR1 the 5 to 16th
Position is incremented to maximum from 0 if it is 0 expression address for indicating the direction of each March address change；Indicate ground if it is 1
Location is decremented to 0 by maximum address.
Each March can include multiple operations (OP), and the width of ACR2 register is 456, for configuring all March
OP.Each OP totally 5, Gao Sanwei (OP [4:2]) is used to configure the operation of auxiliary engine, and meaning is as follows:
3'b000 closes auxiliary engine, and auxiliary engine is without operation；
The auxiliary Engine Address of 3'b001 is that main Engine Address adds 1；
The auxiliary Engine Address of 3'b010 is that main Engine Address adds 2；
The auxiliary Engine Address of 3'b011 is that main Engine Address adds 3；
The auxiliary Engine Address of 3'b100 is identical as leading engine address；
The auxiliary Engine Address of 3'b101 is that main Engine Address subtracts 1；
The auxiliary Engine Address of 3'b110 is that main Engine Address subtracts 2；
3'b111 closes leading engine, and leading engine is without operation；
Low two are used for the operation of leading engine (OP [1:0]), and 00/01/10/11 is respectively defined as W0/W1/R0/R1.
The algorithm configuration of certain above-mentioned register is only an embodiment, can be carried out according to actual test algorithm requirements different
Configuration.
In conclusion built-in certainly by built-in self test engine including the first sub- built-in self test engine and the second son
Testing engine can then support the test to single port memory, can also support the test to twoport or two mouthfuls of memories, accordingly may be used
It realizes various single port or twoport testing algorithm, makes being more widely applied for built-in self test engine；And it configures in practical applications
Good corresponding register, so that it may directly use, considerably reduce the design time and manually of the circuit of built-in self test engine
Cost.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of built-in self test engine, which is characterized in that including the first sub- built-in self test engine, the second sub- built-in self-test
Engine and a register, the register connects the first sub- built-in self test engine and the second sub- built-in self-test draws
It holds up, the first sub- built-in self test engine includes an interface, and for connecting a memory, the second sub- built-in self-test draws
It holds up including an interface, for connecting a memory.
2. built-in self test engine according to claim 1, which is characterized in that the first sub- built-in self test engine and
It is leading engine, engine supplemented by another one of in the second sub- built-in self test engine.
3. built-in self test engine according to claim 2, which is characterized in that under default conditions, first son is built-in
Selftest Engine is leading engine；Engine supplemented by the second sub- built-in self test engine.
4. built-in self test engine according to claim 2, which is characterized in that the register includes Bit2, works as Bit2
It is set as 1, the second sub- built-in self test engine becomes leading engine, and the first sub- built-in self test engine becomes auxiliary and draws
It holds up.
5. built-in self test engine according to claim 1, which is characterized in that the register connects a sub- built-in self-test
Engine is tried, and another sub- built-in self test engine is connected by a phase inverter.
6. built-in self test engine according to claim 2, which is characterized in that the memory is single port memory, institute
It states memory and only connects the leading engine.
7. built-in self test engine according to claim 2, which is characterized in that the memory is twoport or two mouthfuls of storages
The Single port of device, the memory is built-in by interface connection first son of the described first sub- built-in self test engine
Selftest Engine, the interface connection described second that the another port of the memory passes through the described second sub- built-in self test engine
Sub- built-in self test engine.
8. built-in self test engine according to claim 7, which is characterized in that the Single port of memory is master port, separately
Port supplemented by Single port, under default conditions, the first sub- built-in self test engine is leading engine, connects the master of memory
Port；Engine supplemented by the second sub- built-in self test engine connects the auxiliary port of memory.
9. built-in self test engine according to claim 1, which is characterized in that the first sub- built-in self test engine and
The second sub- built-in self test engine include register module, sub- built-in self test engine control module, address generator,
Number generator, clock and control signal generator and data comparator.
10. built-in self test engine according to claim 9, which is characterized in that the first sub- built-in self test engine
The interface connect the address generator in the described first sub- built-in self test engine；The second sub- built-in self-test
The interface of engine connects the address generator in the described second sub- built-in self test engine.
11. built-in self test engine according to claim 9, which is characterized in that real by configuring the register module
Existing single port testing algorithm or twoport testing algorithm.
12. built-in self test engine according to claim 5, which is characterized in that the register connects in a son
The sub- built-in self test engine control module in Selftest Engine is built, and built-in certainly by phase inverter connection another son
Sub- built-in self test engine control module in testing engine.
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| CN201810840386.5A CN109102838A (en) | 2018-07-27 | 2018-07-27 | Built-in self test engine |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810840386.5A CN109102838A (en) | 2018-07-27 | 2018-07-27 | Built-in self test engine |
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| CN201810840386.5A Pending CN109102838A (en) | 2018-07-27 | 2018-07-27 | Built-in self test engine |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115985379A (en) * | 2023-02-09 | 2023-04-18 | 长鑫存储技术有限公司 | MBIST control circuit, method, memory and device |
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| US8677196B1 (en) * | 2011-06-20 | 2014-03-18 | Cadence Design Systems, Inc. | Low cost production testing for memory |
| CN103871478A (en) * | 2012-12-10 | 2014-06-18 | 德州仪器公司 | Programmable Built In Self Test (pBIST) system |
| US20150262713A1 (en) * | 2014-03-12 | 2015-09-17 | International Business Machines Corporation | Built-in testing of unused element on chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101114527A (en) * | 2006-07-28 | 2008-01-30 | 日立超大规模集成电路系统株式会社 | Semiconductor device |
| CN201562462U (en) * | 2009-04-28 | 2010-08-25 | 新思科技有限公司 | Device for testing multiport memory device to detect fault of multiport memory |
| US8677196B1 (en) * | 2011-06-20 | 2014-03-18 | Cadence Design Systems, Inc. | Low cost production testing for memory |
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| CN115985379A (en) * | 2023-02-09 | 2023-04-18 | 长鑫存储技术有限公司 | MBIST control circuit, method, memory and device |
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