CN109067493A

CN109067493A - Detection system, sensor and microcomputer

Info

Publication number: CN109067493A
Application number: CN201810508113.0A
Authority: CN
Inventors: 芋川直; 冈田纪雄
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2017-05-25
Filing date: 2018-05-24
Publication date: 2018-12-21
Also published as: TW201907666A; KR20180129662A; JP2018200666A

Abstract

The present invention relates to a kind of detection system, sensor and microcomputers.The disclosure is intended to correct the frequency of the clock signal of sensor based on the clock signal input from microcomputer.Detection system includes sensor and microcomputer.The sensor is configured to export by executing analog/digital conversion sampled data generated to the analog signal based on clock signal samples.The microcomputer generates clock signal and the clock signal is output to the sensor, and reads the sampled data from the sensor.The sensor corrects the frequency of the clock signal based on the clock signal.

Description

Detection system, sensor and microcomputer

Technical field

This disclosure relates to a kind of detection system, sensor and microcomputer.

Background technique

In recent years, the detection system for acquiring data from various sensors and handling data collected has been used.? Sensing system (the Japanese Unexamined Patent Application public affairs another example is processing by multiple sensors data collected through proposing Open No.2015-228172).

Within the system, the data communication among controller, execution first sensor and second sensor.In the example In, the first input end of controller and the input/output terminal of first sensor are connected to each other.Second input terminal of controller and The input/output terminal of second sensor is connected to each other.The input of the input/output terminal and second sensor of first sensor/ Output end is connected to each other.Second sensor receives the first sensor signal, and in response to inputting the first sensor signal, goes here and there The second sensor signal including the second synchronization signal and the second sensor data based on the second synchronization signal are exported capablely.Cause This, within the system, the data exported from least two or more than two sensor become in one cycle it is obtained from The data of sensor output, and this can be realized by simple sensing system and simple sensor.

Summary of the invention

In aforementioned arrangements, although working as however, the timing when data are exported from sensor can be synchronized with each other Timing when data are sampled may not identical be possible.In this case, the result detected instruction in sensor After analog signal is converted to digital signal, sensor output data.In this case, analog/digital conversion is according to clock Signal executes, and is used as the reference of sampling timing.Therefore, in order to synchronous when data are in multiple sensors with pinpoint accuracy Timing when place is sampled, it is desirable that maintain the accuracy of the frequency of clock signal used in respective sensor.However, sensing Each sensor in device does not usually include the crystal oscillating circuit etc. with pinpoint accuracy, because it will lead to power consumption Increase in terms of increasing with cost.Thus it is common to use simple oscillating circuit (such as ring oscillator).However, there is frequency Rate tends to the problems in the simple oscillation circuit of fluctuation.

The description and attached drawing of other problems and novel feature from specification will be apparent.

According to one embodiment, detection system includes: sensor, when being configured to output by based on first The analog signal of clock signal sampling executes analog/digital conversion sampled data generated；And microcomputer, it is configured It is output to sensor at generation second clock signal and by second clock signal, and reads sampled data from sensor, In, sensor corrects the frequency of the first clock signal based on second clock signal.

According to one embodiment, sensor is configured to export by the simulation based on the first clock signal samples Signal executes analog/digital conversion sampled data generated, wherein the frequency of the first clock signal is based on by microcomputer Second clock signal generated corrects, and sampled data is read by microcomputer.

According to one embodiment, microcomputer is configured to generate second clock signal and second clock signal is defeated Sensor is arrived out, is configured to export by executing analog/digital turn to the analog signal based on the first clock signal samples Sampled data generated is changed, microcomputer is further configured to that sampled data can be read from sensor, wherein the first clock The frequency of signal is based on second clock signal by sensor calibration.

According to one embodiment, the clock signal of sensor is corrected based on the clock signal input from microcomputer Frequency is possible.

Detailed description of the invention

The above and other aspect, advantages and features from being described below for some embodiments understood in conjunction with attached drawing will be brighter Aobvious, in which:

Fig. 1 is the diagram for schematically showing the basic configuration of detection system according to first embodiment；

Fig. 2 is the diagram for schematically showing the configuration of detection system according to first embodiment；

Fig. 3 is the diagram for showing the operation timing of detection system according to first embodiment；

Fig. 4 is the diagram for illustrating in greater detail the configuration of sensor according to first embodiment；

Fig. 5 is the diagram for showing the configuration of frequency/voltage converter；

Fig. 6 is the diagram for showing the configuration of voltage hold circuit；

Fig. 7 is the diagram for showing the configuration of oscillator；

Fig. 8 is the diagram for showing the recovery operation when sensor has accidentally entered sleep pattern.

Fig. 9 is the diagram for showing the recovery operation when microcomputer has accidentally entered sleep pattern.

Figure 10 is the diagram for schematically showing the configuration of detection system according to the second embodiment；

Figure 11 is the diagram for schematically showing the configuration of detection system according to the third embodiment；

Figure 12 is the diagram for showing the operation timing of detection system according to the third embodiment；

Figure 13 is the diagram for schematically showing the configuration of the detection system according to fourth embodiment；

Figure 14 is the diagram for schematically showing the configuration of modification of the detection system according to fourth embodiment；

Figure 15 is the diagram for schematically showing the configuration of the detection system according to the 5th embodiment；

Figure 16 is the diagram for schematically showing the configuration of the detection system according to sixth embodiment；And

Figure 17 is the diagram for schematically showing the configuration of modification of the detection system according to sixth embodiment.

Specific embodiment

The specific embodiment of the disclosure will hereinafter be explained with reference to the drawings.In the accompanying drawings, similar elements are by identical attached drawing Label expression, and in order to which the clear repeated description of explanation will be avoided by as needed.

First embodiment

Hereinafter, with reference to attached drawing, embodiment of the disclosure will be explained.Fig. 1 is to schematically show to implement according to first The diagram of the basic configuration of the detection system 100 of example.Fig. 2 is to schematically show detection system 100 according to first embodiment Configuration diagram.

Detection system 100 includes sensor 1 and microcomputer 2.Sensor 1 and microcomputer 2 being capable of mutual numbers According to communication.Data communication between sensor 1 and microcomputer 2 can by or wire communication or wireless communication hold Row.Sensor 1 is configured to detect in such as physical quantity (amount of pressure or amount of acceleration) and the result that will test be stored in In portion's memory.Microcomputer 2 configures in this way: its result that instruction detection can be read from sensor 1 Data and the operation for controlling sensor 1.

Firstly, sensor 1 will be explained.Sensor 1 includes communication unit 11, detector 12, oscillator 13, simulation/number Word (A/D) converter 14, memory 15 and frequency corrector 16.Communication unit 11, oscillator 13, analog/digital (A/D) conversion Device 14, memory 15 and frequency corrector 16 form signal processor 1A, are executed to the analog signal for carrying out self-detector 12 The A/D converting unit of A/D conversion.

Communication unit 11 (unit is also known as the first input/output interface) is for executing and microcomputer 2 The input/output device of data communication.

Detector 12 detects predetermined physical quantities (such as amount of pressure or amount of acceleration) and exports the result conduct of detection Analog signal AS.

Oscillator 13 generates clock signal clk 1 by oscillating operation and signal generated is output to A/D converter 14.In this embodiment, oscillator 13 has relatively simple configuration and is formed by such as ring oscillator.In this feelings Under condition, there is oscillator 13 frequency of oscillation to tend to the feature fluctuated due to change with the time and environment change.Therefore, it is The frequency of clock signal clk 1 is maintained at predetermined value, oscillator 13 is configured to according to from frequency corrector 16 Control signal CON input, adjust clock signal clk 1 frequency.

A/D converter 14 is executed to the analog signal AS sampled based on the clock signal clk 1 received from oscillator 13 Analog/digital conversion (A/D conversion) and digital signal upon the transition is exported as sampled data SD.

Memory 15 includes the function for the sampled data SD that storage is sequentially exported from A/D converter 14.Memory 15 It is defeated that via communication unit 11 sampled data SD therein will be stored according to the data read request REQ from microcomputer 2 Microcomputer 2 is arrived out.Memory 15 can be such as FIFO (first entering, first go out).

Frequency corrector 16 receives clock signal clk 2 from microcomputer 2 via communication unit 11, and is based on clock Signal CLK2 exports control signal CON to oscillator 13, controls signal CON and is used to correct the clock signal exported from oscillator 13 The frequency of CLK1.The details for correcting the operation of the frequency of clock signal CLK1 will be described later.

Secondly, microcomputer 2 will be explained.As described above, microcomputer 2 is configured to from sensing Device 1 reads sampled data SD.Microcomputer 2 includes communication unit 21 and clock-signal generator 22.Microcomputer 2 also wraps CPU and memory are included, but it is not shown in the accompanying drawings.

Communication unit 21 (unit is also known as the second input/output interface) is the data communication executed with sensor 1 Input/output device.

Clock-signal generator 22 includes such as oscillating circuit, and exports clock signal clk 2 based on oscillating operation, when Clock signal CLK2 is used to provide the processing of the element in microcomputer 2.Clock signal clk 2 also connects via communication unit 21 Sensor 1 is output to such as read requests REQ.As described above, the clock signal of sensor 1 is had been enter into CLK2 is used for the correction process in frequency corrector 16.

Fig. 3 shows an example of operation timing.Sensor 1 is to the signal exported at time T1 from detector 12 (analog signal AS) is sampled, and converts a signal into digital signal (sampled data SD) by A/D converter 14, and then Converted signal is maintained in memory 15.In a similar way, sensor 1 is exported at time T2 from detector 12 Signal (analog signal AS) sampled, converted a signal into digital signal (sampled data SD) by A/D converter 14, and And then converted signal is maintained in memory 15.Then, the mode of microcomputer 2 at time T3 from Sleep pattern changes to after activity pattern, and clock signal clk 2 and read requests REQ are output to sensor by microcomputer 2 1.When receiving read requests REQ, sensor 1 will be maintained at adopting in memory 15 via communication unit 11 at T1 and T2 Sample data SD is output to microcomputer.At time T4, microcomputer 2 enters sleep pattern.In a similar way, when micro- When type computer 2 enters activity pattern at time T8, the sampled data SD at time T5, T6 and T7 is exported from sensor 1.

In this embodiment, clock-signal generator 22 include there is pinpoint accuracy can stabilize clock signal clk 2 Frequency oscillating circuit (for example, crystal oscillating circuit or using pinpoint accuracy adjust on piece oscillating circuit), and with Such mode configures: it has more higher than the frequency stability of oscillator 13 frequency stability.

Further, microcomputer 2, which has, is arranged from sensor 1 sequentially based on clock signal clk 2 with time series Multiple sampled data SD of reading and the function of analyzing these data.

Then, it will be explained for correcting the processing of clock signal CLK1.Fig. 4 is to illustrate in greater detail to implement according to first The diagram of the configuration of the sensor 1 of example.As shown in FIG. 4, frequency corrector 16 includes frequency divider 161, frequency/voltage conversion Device 162, frequency/voltage converter 163, comparator 164, difference amplifier 165, voltage holding unit (voltage hold circuit) 166 and switch 167.

Clock signal clk 2 is input into frequency divider 161 from microcomputer 2 via communication unit 11.Frequency divider 161 will The frequency of clock signal clk 2 is divided by predetermined ratio n.That is, frequency divider 161 is defeated when the frequency of clock signal CLK2 is indicated by f Provide the fractional frequency signal CLKD of the frequency of f/n.

Frequency/voltage converter 162 (converter is also known as first frequency/electric pressure converter) will be defeated from oscillator 13 Clock signal clk 1 out is converted to voltage signal V1 (signal is also known as the first signal).Fig. 5 shows frequency/voltage and turns One example of the configuration of parallel operation 162.Clock signal clk IN (signal corresponds to CLK1) is input into timing control circuit 33.Timing control circuit 33 is based on clock signal clk IN and generates charging signals CHR and discharge signal DCHR.Switch 34 is in this way Mode provide: it allows the electrical conduction between constant current circuit 32 and capacitor 36, and switch 34 be controlled to by Charging signals CHR is turned on or off.Switch 35 provides in this way: it can connect capacitor 36 and ground potential It connects, and switch 35 is controlled to be turned on or off by discharge signal DCHR.Therefore, according to clock signal clk IN, charge is logical It crosses and is electrically charged in capacitor 36 from the electric current that constant current circuit 32 exports and is maintained at the charge quilt in capacitor 36 Electric discharge is exported thus according to the voltage VOUT (this corresponds to voltage signal V1) of the frequency of clock signal clk IN.

Frequency/voltage converter (converter is also known as second frequency/electric pressure converter) 163 is by fractional frequency signal CLKD Frequency conversion be voltage signal V2 (signal is also known as second signal).Frequency/voltage converter 163 with in Fig. 5 Shown in the mode that is configured of frequency/voltage converter 162 similar mode configure.

Voltage signal V2 is compared with predetermined voltage Vth and by signal Vc (it is comparison result) by comparator 164 Voltage hold circuit 166 and switch 167 are output to as switching signal.

Voltage signal V1 is input into an input of difference amplifier 165, and voltage signal V2 is input into difference Another input of amplifier 165.For example, in this embodiment, the reverse phase that voltage signal V2 is input into difference amplifier 165 is defeated Enter, and voltage signal V1 is input into the non-inverting input of difference amplifier 165.Then, the output of difference amplifier 165 instruction The output voltage Vd of differential voltage between voltage signal V1 and voltage signal V2.

Voltage hold circuit 166 keeps the output voltage Vd of difference amplifier 165 according to signal Vc.Fig. 6 shows voltage One example of the configuration of holding circuit.Switch 42 is controlled to be turned on or off by signal Vc.When switch 42 is in ON shape When state, output voltage Vd is applied to capacitor 43.When switch 42 is in OFF state, the voltage value of output voltage Vd is protected It holds in capacitor 43.The voltage value kept is by using the voltage follower circuit of operational amplifier 41 to export as voltage Vh。

Switch 167 will be in the output end of the output end of difference amplifier 165 and voltage hold circuit 166 according to signal Vc One connect with the control terminal of oscillator 13.Fig. 7 shows an example of the configuration of oscillator 13.Oscillator 13 includes annular Oscillator, wherein n (n is positive odd number) a inverter cricuit INV_1-INV_n is connected with annular shape.Supply voltage is controlled from voltage Device is supplied to each inverter cricuit in inverter cricuit.The voltage value supplied from voltage control circuit 31 is by control signal CON Control, is changed the retardation of each inverter cricuit, the frequency of the clock signal clk 1 thus exported from oscillator 13 It is controlled.

As described above, the clock-signal generator 22 of microcomputer 2 not with 1 simultaneously operating of sensor.Therefore, The frequency of clock signal clk 1 is independently fluctuated with clock signal clk 2.In addition, as described above, clock signal clk 1 Frequency is tended to relatively easy fluctuate.Therefore, in order to guarantee microcomputer 2 data time Series Processing it is accurate Degree, the frequency of clock signal clk 1 need to be maintained at predetermined value based on clock signal clk 2.It is received when from microcomputer 2 To the frequency of oscillation of clock signal clk 1 cannot shift to an earlier date as known to sensor when, the frequency information for the clock that be used to communicate can To be sent to sensor 1 from microcomputer 2.The transmission of frequency information can be performed at suitable timing.

In the following description, the operation for correcting the frequency of clock signal CLK1 will be explained.

[1. when clock signal CLK2 is input into sensor 1]

When clock signal CLK2 is input into sensor 1, the output instruction fractional frequency signal of frequency/voltage converter 163 The voltage signal V2 of the frequency of CLKD.

The predetermined voltage Vth for being input to comparator 164 is set to voltage signal when clock signal CLK2 is entered V2 becomes larger than such value of voltage Vth.Therefore, in this case, comparator 164 exports such as HIGH as signal Vc。

When signal Vc is HIGH, switch 167 connects the output end of the control terminal of oscillator 13 and difference amplifier 165 It connects.Further, in difference amplifier 165, the voltage signal V1 and instruction frequency dividing letter of the frequency of telltable clock signal CLK1 The voltage signal V2 of the frequency of number CLKD compares, and output voltage Vd (it is the differential voltage between them) is made by output To control signal CON.

Oscillator 13 increases or the frequency of reduction clock signal clk 1 according to the value of control signal CON to export, by This can make the frequency of clock signal clk 1 consistent with the frequency of fractional frequency signal CLKD.

While being stopped [2. when clock signal clk 2 is input to sensor 1]

When clock signal clk 2 being input to sensor 1 being stopped, the voltage letter of the frequency of fractional frequency signal CLKD is indicated Number V2 becomes such as " 0 ".

Therefore, voltage signal V2 becomes smaller than voltage Vth.Therefore, comparator 164 exports such as LOW as signal Vc.

When signal Vc is LOW, voltage hold circuit 166 keeps the control signal CON exported from difference amplifier 165 (that is, output voltage Vd).

Switch 167 connects the control terminal of oscillator 13 with the output end of voltage hold circuit 166.Therefore, have by electricity The control signal CON for the constant voltage Vh that pressure holding circuit 166 is kept is input into oscillator 13.Therefore, oscillator 13 is corrected In the operation of frequency of clock signal clk 1 be interrupted.

[3. when clock signal CLK2 is again input to sensor 1]

In this case, as described above, the operation of the frequency of the clock signal clk 1 in oscillator 13 is corrected It is restarted.

Then, the example for correcting the operation of clock signal CLK1 will be explained.

[example 1: when sensor 1 has accidentally entered sleep pattern]

Sensor 1 can enter sleep pattern for example to inhibit power consumption.In this case, for microcomputer 2 Data are read from sensor 1, sensor 1 is activated and clock signal clk 1 is corrected.

Step S11

Sensor 1 accidentally enters sleep pattern.

Step S12

The read requests REQ for reading the data being stored in memory 15 is sent sensor 1 by microcomputer 2.

Step S13

Microcomputer 2 determines whether there is the response to the read requests from sensor 1.

Step S14

When there is no the response to the reading order from sensor 1, initiation command is sent biography by microcomputer 2 Sensor 1.

Step S15

It has been sent after initiation command predetermined amount of time passes by since microprocessor 2, process return step S12。

Step S16

When having existed the response to the reading order from sensor 1, microcomputer 2 sends out clock signal clk 2 It is sent to sensor 1.1 reference clock signal CLK2 of sensor and the operation for executing correction clock signal CLK1.Therefore, clock is believed The frequency of number CLK1 is corrected to desired value.

Step S17

Microcomputer 2 reads predetermined sampled data SD from sensor 1.

[example 2: when microcomputer 2 has accidentally entered sleep pattern]

Microcomputer 2 can enter sleep pattern for example to inhibit power consumption.In this case, work as microcomputer 2 from when sleep pattern recovery, and the needs of clock signal clk 1 are corrected.

Fig. 9 is the diagram for showing the recovery operation when microcomputer 2 has accidentally entered sleep pattern.

Step S21

Microcomputer (MCU) 2 accidentally enters sleep pattern.

Step S22

Microcomputer (MCU) 2 restores from sleep pattern.

Step S23

Microcomputer 2 sends sensor 1 for read requests REQ and exports clock signal clk 2.Sensor 1 refers to Clock signal clk 2 and the operation for executing correction clock signal CLK1.Therefore, the frequency of clock signal clk 1, which is corrected, expires Prestige value.

Step S24

Microcomputer 2 reads predetermined sampled data SD from sensor 1.

As discussed above, according to the configuration, even if when the clock signal clk 1 exported from the oscillator 13 of sensor 1 Frequency fluctuation when, the frequency of clock signal clk 1 also can be based on the clock signal clk 2 supplied from microcomputer 2 by school Just arrive value appropriate.

Further, when microcomputer 2 from have and that similar configuration of sensor 1 multiple sensors read When data, in order to make respective sensor data sample-synchronous, the corresponding frequencies of the clock signal clk 1 of respective sensor need If identical.On the other hand, in the configuration, clock signal clk 2 is output to each of sensor by microcomputer 2 Sensor, and each sensor in sensor can be corrected corresponding clock signal clk 1.Therefore, easily school The clock signal clk 1 of just each sensor is possible.

Moreover, microcomputer 2 can by will for example necessary signal be output to sensor 1 set sample frequency and The frequency of clock signal clk 1.For example, the frequency of sample frequency and clock signal clk 1 in 2 setting sensor 1 of microcomputer Rate, thus sensor 1 can set the frequency dividing ratio of clock signal clk 2.Much less, microcomputer 2 being capable of setting sensor 1 In clock signal clk 2 frequency dividing ratio itself.

Second embodiment

Detection system 100 according to the second embodiment will be explained.Figure 10 is to schematically show according to second embodiment Detection system 200 configuration diagram.Detection system 200 has in wherein detection system 100 according to first embodiment The configuration that microcomputer 2 is replaced by microcomputer 3.Detection system 200 is configurable for being based on working as data for calculating The information of time when being sampled is come the system for calculating the sampling time of data, and information is from sensor 1 by microcomputer Calculation machine 3 receives.Further, the operation timing of detection system 200 is similar with shown in fig. 3 that.

In addition to the component being included in microcomputer 2, microcomputer 3 includes operating unit (computing circuit) 23.Computing circuit 23 can include logic circuit.Further, computing circuit 23 can be by being executed by CPU (not shown) Program is realized.

In this embodiment, memory 15 stores the sampled data SD exported from A/D converter 14, and according to from micro- The request REQ of type computer 3 exports the sampled data SD and serial data SER that will be exported, serially via communication unit 11 Data SER is indicated when the information of the timing when data are sampled after resetting sampled data SD.

In Figure 10, as an example, the first sampled data after reset is indicated by SD1, after reset first Serial data is indicated that the second sampled data after reset is indicated by SD2, the second serial data after reset by SER1 It is indicated by SER2 ... ..., the i-th sampled data after reset is indicated by SDi, and the i-th serial data after reset It is indicated by SERi.

Then, it will be explained for calculating the operation in the sampling time of microcomputer 3.Microcomputer 3 can work as The serial data of the memory 15 of sensor 1 is reset at timing when detection system 200 is activated or at desired timing SER。

Particularly, microcomputer 3 exports reset signal RS.Reset signal RS is input into memory 15, and serial Data SER is reset as " 0 ".After that, whenever receiving sampled data, serial data SER increment is made by memory 15, And serial data SER is added to sampled data SD.

When microcomputer 3 receives sampled data SD and serial data SER, computing circuit 23 refers to serial data The time of SER and calculating when corresponding sampled data SD is sampled.Hereinafter, calculation method will be explained.

As shown in following formula [1], microcomputer 3 will pass through time by sampling period Ps multiplied by instruction sampling The value N value obtained of several serial data SER is added to reference time Tref, to calculate sampling time Ts.Reference time Tref is the time when reset signal RS is output to sensor 1 by microcomputer 3.Computing circuit 23 keep for example when The time that reset signal RS has been exported as reference time Tref, thus its can as needed to reference time Tref into Row reference.

Ts=Tref+NPs [1]

Further, it is also possible for more accurately calculating the sampling time.For example, actually being sampled in the presence of when data When timing and when microcomputer 3 calculate the sampling time when timing between for the transmission of signal and the processing institute of signal It is required that delay time.The delay time as caused by the A/D conversion process in A/D converter 14 is indicated by TD1.It is converted by A/D Delay time caused by processing mean to convert since the rising edge or failing edge of clock signal clk 1 to A/D herein institute It is required that time.Further, delay time required by time synchronization is indicated by TD2.For required by time synchronization Delay time TD2 be from when microcomputer 3 export reset signal RS when time to by memory 15 reset serial number Time required time when being completed according to SER.In this case, sampling time Ts can be counted by following formula [2] It calculates.

Ts=Tref+NPs+TD1+TD2 [2]

Although having assumed that delay time TD1 and delay time TD2 herein, but it go without saying that, as caused by another factor Delay time can take the circumstances into consideration to be added.

Further, the information about the sampling period and delay time that be used to calculate, which can be stored in, is for example mentioned For in the memory (not shown) in microcomputer 3.Further, the sampling period can be by that will indicate the sampling period Signal is supplied to sensor 1 in sensor 1 from the memory of microcomputer 3 and is set.

As described above, miniature in addition to the frequency of the clock signal clk 1 of correction sensor 1 according to the configuration Computer 3 can calculate the sampling time of sampled data SD based on serial data SER.Therefore, sampled data is correctly obtained The time series of SD is possible.

Further, according to the configuration, serial data SER is incremented whenever executing sampling in sensor 1.Therefore, When microcomputer 3 is lacked from the received sampled data of sensor 1, this lacks the value of serial data SER also.Therefore, The presence for failing obtained sampled data can be easily detected.In this case, for example, microcomputer 3 can be with Request sensor 1 exports the sampled data for failing to be obtained again.

Sampled data is read from multiple sensors with the configuration similar with the configuration of sensor 1 when microcomputer 3 When, in order to which the sampled data sampled simultaneously in corresponding sensor is associated with each other in microcomputer 3, miniature calculating Machine 3 needs to refer to the sampling time of the sampled data of corresponding sensor.On the other hand, according to the configuration, as described above , the sampling time of the sampled data of corresponding sensor can be calculated, and thus will easily be adopted simultaneously in multiple sensors It is possible that the sampled data of sample, which is associated with each other,.

According to the configuration, in order to calculate the sampling time in microcomputer 3, serial data SER is exported from sensor 1 To microcomputer 3.Thus, for example, not needing to provide part and the instruction of the data of the time in output indication sensor 1 The time data in sampling time itself do not need to be sent to microcomputer 3 from sensor 1.Therefore, which is advantageous, Because reducing the size of sensor and improvement is possible to be output to the compression ratio of the data of microcomputer from sensor.

3rd embodiment

Detection system 300 according to the third embodiment will be explained.Figure 11 is to schematically show according to third embodiment Detection system 300 configuration diagram.Detection system 300 includes multiple sensors.Detection system 300 includes microcomputer 2, first sensor 4 and second sensor 5.In this example, sensor 4 and 5 has and the sensor 1 of detection system 100 Configure similar configuration.Microcomputer 2 is similar with the microcomputer 2 of detection system 100.

Figure 12 shows an example of operation timing.First sensor 4 is by the sampled data at time T9 and time T10 SD is kept in memory.Second sensor 5 keeps the sampled data at time T11 in memory.Then, in microcomputer After calculation machine 2 enters activity pattern from sleep pattern at the time T12, clock signal clk 2 and read requests REQ are output to First sensor 4.When receiving read requests REQ, first sensor 4 exports the sampled data SD at time T9 and T10 To microcomputer 2.Further, clock signal clk 2 and read requests REQ are output to second sensor 5.It is receiving When read requests REQ, the sampled data SD at time T11 is output to microcomputer 2 by second sensor 5.Then, microcomputer Calculation machine 2 enters sleep pattern at time T3.

Detection system 300 is the system for example for acquiring and handling biological information.For example, sensor 4 is impulse wave Sensor detects biological pulsation wave and exports the result of detection as sampled data SD4.For example, sensor 5 is that electrocardiogram is retouched The sensor of note, the electrocardiogram for detecting living body and the result of detection is exported as sampled data SD5.Microcomputer 2 is based on Sampled data SD4 and sampled data SD5, the propagation of the phase difference estimation impulse wave between the peak of electrocardiogram and the peak of impulse wave Speed.

Therefore, in order to guarantee impulse wave spread speed estimation accuracy, by the time of the data of sensor sample Accuracy becomes important.On the other hand, according to the configuration, the clock frequency of sensor 4 and 5 can with in detection system 100 Those of similar mode correct, it is possible for thus increasing the processing accuracy of sampled data.

In this embodiment, according to second embodiment, microcomputer 2 can be replaced by microcomputer 3.In this feelings Under condition, the sampling time of the sampled data received from multiple sensors can be calculated, thus more reliably and more acurrate The more multiple time series datas in ground are possible.

Fourth embodiment

It will be explained according to the detection system 400 of fourth embodiment.Figure 13 is schematically shown according to fourth embodiment Detection system 400 configuration diagram.Detection system 400 includes that (n is equal to or greater than 1 to multiple detector 12_0-12_n Integer), signal processor 6A and microcomputer 2.Due to microcomputer 2 and that described class in the first embodiment Seemingly, thus its description will be omitted.

Detector 12_0-12_n all types having the same or can be the detection including different types Device.Analog signal AS0-ASn (it is the signal exported from detector 12_0-12_n) is input into signal processor 6A.

Signal processor 6A includes communication unit 11, oscillator 13, A/D converter 14, memory 15, frequency corrector 16 With multiplexer 17.In this example, communication unit 11, oscillator 13, A/D converter 14, memory 15,16 and of frequency corrector Multiplexer 17 is organized into A/D converting unit so that (it is the letter exported from detector 12_0-12_n to analog signal AS0-ASn Number) execute A/D conversion.Due to communication unit 11, oscillator 13, A/D converter 14, memory 15 and frequency corrector 16 and Those of one embodiment is similar, thus its description will be omitted.

Multiplexer 17 is configured to receive analog signal AS0-ASn (it is the signal exported from detector 12_0-12_n), And any one of analog signal AS0-ASn is output to A/D converter 14.In this case, multiplexer 17 can be with Such as clock signal clk 1 is received, and is based on clock signal clk 1, switches letter to be output among analog signal AS0-ASn Number.

Multiplexer 17 may include the sampling and holding function to be input to the signal of multiplexer 17.In this case, Multiplexer 17 can be exported by sampling analog signal AS0-ASn while taking the circumstances into consideration they switching signal obtained.Into one Step ground, sampling and holding circuit including analog switch and capacitor can be provided for example in detector 12_0-12_n Between each detector and multiplexer 17.In this case, analog switch can concurrently ON/OFF so that the time difference Not for each inspection of the sampling timing about analog signal AS0-ASn (it is the signal exported from detector 12_0-12_n) Device is surveyed to be generated.Timing when analog signal AS0-ASn is sampled can be determined for example based on clock signal clk 1.

The operation of those of other operations and detection system 100 according to first embodiment due to detection system 400 is similar, Thus its description will be omitted.

In this example, detector 12_0-12_n and signal processor 6A are physically separated each other.However, it is to be understood that Detector 12_0-12_n and signal processor 6A integrally forms the sensor 6 for corresponding to the sensor according to previous embodiment. In other words, detector may be provided as the external component of signal processor.By physically will test device and signal processing Device separation, detector can select among multiple detectors or a detector can depend on application and be replaced by another It changes, thus the flexibility of the configuration of detection system can be modified.

Although the analog signal AS0-ASn for carrying out self-detector 12_0-12_n has been described, when it is input into figure When multiplexer 17 in 13, multiple A/D converters can replace multiplexer 17 and be provided.Figure 14 is to schematically show detection system The diagram of the configuration of system 401, is the modification according to the detection system 400 of fourth embodiment.As shown in Figure 14, it detects System 401 is included therein the configuration that the signal processor 6A of detection system 400 is replaced by signal processor 7A.Signal processor 7A is included therein the A/D converter 14 of signal processor 6A and multiplexer 17 is matched by what A/D converter 14_0-14_n was replaced It sets.

A/D converter 14_0-14_n respectively samples analog signal AS0-ASn, and analog signal AS0-ASn is turned It is changed to digital signal (sampled data SD0-SDn), and digital signal (sampled data SD0-SDn) is then output to memory 15.In this case, the only one in A/D converter 14_0-14_n is based on the clock signal clk 1 supplied from oscillator 13, Selectively export sampled data.Then, the A/D converter for exporting sampled data switches according to clock signal clk 1, thus Memory 15 can selectively receive from A/D converter 14_0-14_n export sampled data SD0-SDn in one and Sequentially keep the sampled data received.

The operation of those of other operations and detection system 100 according to first embodiment due to detection system 401 is similar, Thus its description will be omitted.

Also in this case, detector 12_0-12_n and signal processor 7A is physically separated.However, it is to be understood that Detector 12_0-12_n and signal processor 7A integrally forms the sensor 7 for corresponding to the sensor according to previous embodiment. In other words, detector may be provided as the external component of signal processor.By physically will test device and signal processing Device separation, detector can select among multiple detectors or thus a detector can be detected by another replacement The flexibility of the configuration of system can be modified.

From discussed above, similar with first embodiment according to the configuration, or even when multiple detectors are provided, response In the request from microcomputer, sampled data can be output to microcomputer from signal processor.

Although detection system 400 has described as the modification of detection system 100 according to first embodiment above, But this is only example.Much less, multiple detectors and multiplexer also may be provided in detection system according to the second embodiment In the sensor of system 200.In a second embodiment, the interpreted computing circuit 23 in wherein microcomputer 3 uses expression Formula [2] calculates the example of sampling time Ts in the case where considering delay time TD1 and TD2.On the other hand, according to the configuration, Switching may be used also from the delay of multiplexer signal required time to be output or the signal occurred in multiplexer etc. itself Sampling time Ts is calculated to be added as delay time.

Further, much less, multiple detectors and multiple A/D converters also may be provided according to second embodiment Detection system 200 sensor in.

Further, much less, the sensor of detection system 300 according to the third embodiment can be by this embodiment Multiple detectors and the signal processor replacement described as one sees fit.

5th embodiment

It will be explained according to the detection system 500 of the 5th embodiment.Figure 15 is schematically shown according to the 5th embodiment Detection system 500 configuration diagram.Detection system 500 be according to the modification of the detection system 400 of fourth embodiment, and And the reference clock CLKR as referenced by oscillator 13 is supplied to vibration by the oscillator 50 provided outside signal processor 6A Swing device 13.The operation of those of other configurations and detection system 400 due to detection system 500 is similar, thus its description will be saved Slightly.

According to the configuration, oscillator 13 can export clock signal clk 1, and frequency adjusts in this way, makes It takes the circumstances into consideration to pass through control signal CON based on reference clock CLKR and the frequency of the clock signal clk 2 in microcomputer is same Step.

In this example, detector 12_0-12_n and signal processor 6A are physically separated each other.However, and detection system It unites 400 similar, it is to be understood that detector 12_0-12_n and signal processor 6A, which is integrally formed, to be corresponded to according to previous embodiment Sensor sensor 6.In other words, detector may be provided as the external component of signal processor.By physically It will test device to separate with signal processor, detector can select among multiple detectors or a detector can depend on In application by another replacement, thus the flexibility of the configuration of detection system can be modified.

Although detection system 500 has described as the modification of the detection system 400 according to fourth embodiment above, But this is only example.That is, oscillator 50 may be provided in the inspection in addition to the detection system 400 according to fourth embodiment In examining system.

Sixth embodiment

It will be explained according to the detection system 600 of sixth embodiment.Figure 16 is schematically shown according to sixth embodiment Detection system 600 configuration diagram.Detection system 600 is included therein according to the detection system 400 of fourth embodiment The configuration that signal processor 6A is replaced by micro-control unit (MCU) 8A is the one aspect of signal processor.Due to detection system The configuration of those of other configurations and the detection system 400 of system 600 is similar, thus its description will be omitted.

Detection system 600 realizes frequency by the frequency corrector 16 of detection system 400 by the calculating as performed by CPU Calibration function.Therefore, as shown in Figure 16, in the MCU 8A of detection system 600, the signal processor of detection system 400 The communication unit 11 and frequency corrector 16 of 6A is removed, and alternatively provides bus 61 and CPU 62.Due to oscillator 13, A/D converter 14, memory 15 and multiplexer 17 are similar with those of detection system 400, thus its description will be omitted.

Bus 61 configures in this way, enables address information and data in oscillator 13, A/D converter 14, it is exchanged among memory 15 and CPU 62.

CPU 62 is configured to export control signal CON to control oscillator 13 in this way, so that being based on from vibration The clock signal clk 2 for swinging the clock signal clk 1 of the output of device 13 and being exported from microcomputer 2, via bus 61, clock signal The Frequency Synchronization of the clock signal clk 2 of the frequency and oscillator 13 of CLK1.

In this example, CPU 62 can receive the clock signal clk 1 exported from oscillator 13 and from microcomputer 2 The clock signal clk 2 of output.Then, CPU 62 compares clock signal clk 1 with clock signal clk 2, detects these clocks Deviation between the frequency of signal, and control signal CON is exported based on the result of detection.Oscillator 13 is according to received Control signal CON take the circumstances into consideration adjust clock signal clk 1 frequency.

In this example, detector 12_0-12_n and signal processor 8A are physically separated each other.However, it is to be understood that Detector 12_0-12_n and signal processor 8A integrally forms the sensor 8 for corresponding to the sensor according to previous embodiment. In other words, detector may be provided as the external component of signal processor.By physically will test device and signal processing Device separation, detector can select among multiple detectors or a detector can depend on application and be replaced by another It changes, thus the flexibility of the configuration of detection system can be modified.

It is then detected that the modification of system 600 will be explained.Figure 17 is the configuration for schematically showing detection system 601 Diagram, be the modification according to the detection system 600 of sixth embodiment.Detection system 601 is included therein detection system The configuration that 600 MCU 8A is replaced by MCU 9A is a form of signal processor.

In addition to the component being provided in MCU 8A, MCU 9A further includes communication unit 71, direct memory access (DMA) control Device (DMAC) 72, read-only memory (ROM) 73 and timer 74 processed.

Communication unit 71 is connected to bus 61, and including functionally similar with communication unit 11 as described above Function.

DMAC 72 can be executed via data transmission performed by CPU, and can for example be executed instead of CPU 62 from depositing Reservoir 15 arrives the data transmission of communication unit 71.Therefore, it is possible for reducing the load of the data transmission as performed by CPU 62. The example is not limited to by the data transmission that DMAC is executed.

ROM 73 stores the parameter for for example defining the program of the processing in CPU 62 and being used for the treatment of, and 62 energy of CPU It is enough to read program or parameter from ROM 62 as needed.

Timer 74 receives the clock signal clk 1 exported from oscillator 13 via bus 61.Further, timer 74 The clock signal clk 2 exported from microcomputer 2 is received via communication unit 71 and bus 61.Timer 74 can pass through meter When device Function detection clock signal clk 1 and CLK2 pulse width and frequency.Therefore, timer 74 detects clock signal clk 1 Frequency relative to clock signal clk 2 frequency deviation.CPU 62 receives instruction and is detected via bus 61 by timer 74 Clock signal clk 1 frequency deviation data DET, and according to data DET by control signal CON be output to oscillator 13, thus make the frequency of clock signal clk 1 relative to the Frequency Synchronization of clock signal clk 2 be possible.

Since the other configurations of detection system 601 and operation are similar with those of detection system 400 configuration and operation, thus Its description will be omitted.

In this example, detector 12_0-12_n and signal processor 9A are physically separated each other.However, it is to be understood that Detector 12_0-12_n and signal processor 9A integrally forms the sensor 9 for corresponding to the sensor according to previous embodiment. In other words, detector may be provided as the external component of signal processor.By physically will test device and signal processing Device separation, detector can select among multiple detectors or a detector can depend on application and be replaced by another It changes, thus the flexibility of the configuration of detection system can be modified.

Pass through CPU or the calculation processing quilt of microcomputer instead of the frequency corrector 16 including circuit according to the configuration Using, it is thus similar to the 5th embodiment with first embodiment, make the frequency of clock signal clk 1 relative to clock signal clk 2 Frequency Synchronization be possible.

Much less, similar with fourth embodiment, switching is from multiplexer signal required time to be output or is being multiplexed The signal delay occurred in device itself etc. can also be added as delay time and also calculate sampling time Ts in the configuration. Further, similar with the 5th embodiment, the reference clock CLKR as referenced by oscillator 13 can be by outside signal processor The oscillator that portion provides is supplied to oscillator 13.

Further, much less, A/D converter 14_ similar with detection system 401, corresponding to detector 12_0-12_n 0-14_n, which also may be provided in, replaces A/D converter 14 and multiplexer 17 in MCU 8A and 9A.

Other embodiments

Note that the present disclosure is not limited to embodiments set forth above and can be without departing from the spirit of the present disclosure Change as one sees fit.Although the sensing that it includes detector and signal processor of the first embodiment into 3rd embodiment has been described Device, but the configuration of detection system is not limited to the example.It is similar to the 5th embodiment with fourth embodiment, much less, detector It can be physically separated each other with signal processor.In other words, detector may be provided as the external portion of signal processor Part.It is separated by physically will test device with signal processor, detector can select or one among multiple detectors Detector can depend on application by another replacement, and thus the flexibility of the configuration of detection system can be modified.

Although such as data, clock signal and the information of request are in sensor or signal processor in the aforementioned embodiment Be transmitted and received between microcomputer, but the transmission of information and receive can by or wire communication or nothing Line communicates to execute.

Although serial data SER has been described in a second embodiment, serial data SER may be not added into biography All 7 sampled data SD of sensor output.Serial data SER can be added when sampled data SD is by output pre-determined number To sampling time SD.For example, the serial data SER of increment " 10 " can be whenever sampled data compared with previous data output SD is added when being exported ten times.Then, when the integral multiple in sampling period is added to sampling calculated by microcomputer 3 Between, so as to calculate the sampling time for the output data that serial data SER is not added to.

In the foregoing written description, in a second embodiment, not only according to the frequency of the clock signal clk of first embodiment 1 It corrects and has been described based on the serial data SER sampling time for calculating data.However, the sampling time is based on wherein Serial data SER described in second embodiment does not presuppose correction clock according to first embodiment come the configuration calculated The presence of the configuration of the frequency of signal CLK1.That is, the configuration of the frequency of correction clock signal CLK1 according to first embodiment Lack and does not forbid according to the second embodiment including the realization for calculating the detection system of configuration in sampling time.

Although having been based on embodiment by the disclosure that the present inventor makes to be described in detail, but it go without saying that, this It is open to be not limited to the embodiment above stated and the spirit that change in various ways without departing from the disclosure.

Although describing the configuration of frequency corrector by reference to Fig. 4 in the first embodiment, this is only example.It is another Configuration can be taken the circumstances into consideration to apply, as long as similar control signal can be output to oscillator.

First embodiment and second embodiment can be combined, such as desired by those skilled in the art.

Although embodiment has been described above, aforementioned inspection systems, sensor, microcomputer and correction detection system The method of system can be described as follows.

(supplementary explanation 1) a kind of detection system, comprising: sensor is configured to output sampled data, is logical It crosses and analog/digital conversion digital signal generated is executed to the analog signal of instruction testing result, analog signal is based on first Clock signal is sampled；And microcomputer, it is configured to generate second clock signal and second clock signal is defeated Sensor is arrived out, and reads sampled data from sensor, wherein sensor corrects the first clock based on second clock signal The frequency of signal.

(supplementary explanation 2) is according to the detection system of supplementary explanation 1, wherein sensor includes: the first I/O unit (the first input/output interface) is configured to execute the data communication with microcomputer；Detector is configured to defeated The result detected out is as analog signal；Oscillator, is configured to export the first clock signal, and frequency has been based on supply Control signal correct；Frequency corrector is configured to be based on to connect via the first input/output interface from microcomputer The second clock signal received, output control signal；Analog/digital converter is configured to based on the first clock signal pair Analog signal is sampled, analog/digital conversion is executed to sampled analog signal and exports sampled data；And storage Device is configured to store sampled data, and microcomputer includes: clock-signal generator, is configured to generate Two clock signals；And second I/O unit (the second input/output interface), it is configured to execute and sensor Data communication.

(supplementary explanation 3) is according to the detection system of supplementary explanation 2, wherein microcomputer is adopted when it from memory reading Second clock signal is exported when sample data.

(supplementary explanation 4) is according to the detection system of supplementary explanation 2, wherein frequency corrector includes: frequency divider, is matched It is set to and the frequency of second clock signal is divided；First frequency/electric pressure converter, when being configured to export instruction first First signal of the frequency of clock signal；Second frequency/electric pressure converter is configured to export the letter that instruction is divided by frequency divider Number frequency second signal；Difference amplifier is configured to export the difference between the first signal of instruction and second signal The signal of voltage；Comparator is configured to compare second signal with the signal with predetermined value and exports instruction ratio Compared with result switching signal；Voltage hold circuit is configured to be kept exporting from difference amplifier according to switching signal The voltage of signal；Switch is configured to the output of the output of difference amplifier and voltage hold circuit according to switching signal In one connect with oscillator, oscillator is connected to the output of difference amplifier, make from difference amplifier export The voltage of signal is input into oscillator as control signal, and oscillator is connected to the output of voltage hold circuit, So that being input into oscillator as control signal by the voltage that voltage hold circuit is kept.

(supplementary explanation 5) is according to the detection system of supplementary explanation 4, wherein switch works as second clock signal from miniature calculating Oscillator is connected with the output of difference amplifier when machine is entered, and is switched when second clock signal is not from microcomputer Oscillator is connected with the output of voltage hold circuit when being entered.

(supplementary explanation 6) is according to the detection system of supplementary explanation 2, wherein microcomputer can export reset signal To sensor, according to the read requests from microcomputer, the number after reset signal is had been received in instruction by memory According to the serial data of number of sampling be output to microcomputer together with corresponding sampled data, and microcomputer also wraps Computing circuit is included, is configured to based on the reference time when reset signal is exported, the sampling period in sensor With the serial data received, the sampling time of the sampled data received is calculated.

(supplementary explanation 7) is according to the detection system of supplementary explanation 6, wherein computing circuit will be by serial by what is received The value of data is added to the reference time multiplied by sampling period value obtained to calculate the sampling time.

(supplementary explanation 8) is according to the detection system of supplementary explanation 7, wherein computing circuit is also added from when computing circuit is defeated Out when reset signal to the delay time when serial data is reset to calculate the sampling time.

(supplementary explanation 9) is according to the detection system of supplementary explanation 7, wherein computing circuit is also added to be believed based on the first clock Delay time needed for number converting analog signals into sampled data is to calculate the sampling time.

(supplementary explanation 10) is according to the detection system of supplementary explanation 6, wherein requested from microcomputer whenever reading When, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 11) is according to the detection system of supplementary explanation 6, wherein requested pre- from microcomputer whenever reading When determining number, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 12) is according to the detection system of supplementary explanation 6, including multiple sensors, wherein detection system is based on Sampling time calculated will be associated with each other by the sampled data of multiple sensor samples simultaneously.

A kind of (supplementary explanation 13) sensor, is configured to output sampled data, is by detecting to instruction As a result analog signal executes analog/digital conversion digital signal generated, and analog signal is based on the first clock signal and is adopted Sample, wherein sensor based on the frequency for correcting the first clock signal by microcomputer second clock signal generated, with And sampled data is read by microcomputer.

(supplementary explanation 14) is according to the sensor of supplementary explanation 13, comprising: the first input/output interface is configured to Execute the data communication with microcomputer；Detector is configured to export the result of detection as analog signal；Oscillation Device, is configured to export the first clock signal, and frequency has been based on the control signal of supply to correct；Frequency corrector, It is configured to based on the second clock signal received via the first input/output interface from microcomputer, output control Signal；Analog/digital converter is configured to sample analog signal, based on the first clock signal to sampled Analog signal executes analog/digital conversion and exports sampled data；And memory, it is configured to store sampled data.

(supplementary explanation 15) is according to the sensor of supplementary explanation 14, wherein microcomputer includes: clock signal Device is configured to generate second clock signal: and the second input/output interface, it is configured to execute and sensor Data communication.

(supplementary explanation 16) is according to the sensor of supplementary explanation 14, wherein microcomputer is adopted when it from memory reading Second clock signal is exported when sample data.

(supplementary explanation 17) is according to the sensor of supplementary explanation 14, wherein frequency corrector includes: frequency divider, is matched It is set to and the frequency of second clock signal is divided；First frequency/electric pressure converter, when being configured to export instruction first First signal of the frequency of clock signal；Second frequency/electric pressure converter is configured to export the letter that instruction is divided by frequency divider Number frequency second signal；Difference amplifier is configured to export the difference between the first signal of instruction and second signal The signal of voltage；Comparator is configured to compare second signal with the signal with predetermined value and exports instruction ratio Compared with result switching signal；Voltage hold circuit is configured to be kept exporting from difference amplifier according to switching signal The voltage of signal；Switch is configured to the output of the output of difference amplifier and voltage hold circuit according to switching signal In one connect with oscillator, wherein oscillator is connected to the output of difference amplifier, makes defeated from difference amplifier The voltage of signal out is input into oscillator as control signal, and oscillator is connected to the defeated of voltage hold circuit Out, the voltage kept by voltage hold circuit is made to be input into oscillator as control signal.

(supplementary explanation 18) is according to the sensor of supplementary explanation 17, wherein switch works as second clock signal from miniature calculating Oscillator is connected with the output of difference amplifier when machine is entered, and is switched when second clock signal is not from microcomputer Oscillator is connected with the output of voltage hold circuit when being entered.

(supplementary explanation 19) is according to the sensor of supplementary explanation 14, wherein microcomputer can export reset signal To sensor, according to the read requests from microcomputer, the number after reset signal is had been received in instruction by memory According to the serial data of number of sampling be output to microcomputer together with corresponding sampled data, and microcomputer also wraps Computing circuit is included, is configured to based on the reference time when reset signal is exported, the sampling period in sensor With the serial data received, the sampling time of the sampled data received is calculated.

(supplementary explanation 20) is according to the sensor of supplementary explanation 19, wherein computing circuit will be by serial by what is received The value of data is added to the reference time multiplied by sampling period value obtained to calculate the sampling time.

(supplementary explanation 21) is according to the sensor of supplementary explanation 20, wherein computing circuit is also added from when computing circuit is defeated Out when the reset signal to the delay time when serial data is reset to calculate the sampling time.

(supplementary explanation 22) is according to the sensor of supplementary explanation 20, wherein computing circuit is also added to be believed based on the first clock Delay time needed for number converting analog signals into sampled data is to calculate the sampling time.

(supplementary explanation 23) is according to the sensor of supplementary explanation 19, wherein when reading is requested from microcomputer, Serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 24) is according to the sensor of supplementary explanation 19, wherein requested pre- from microcomputer whenever reading When determining number, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 25) is according to the sensor of supplementary explanation 19, wherein sensor is based on the sampling time calculated, will It is associated with each other simultaneously by the sampled data of multiple sensor samples.

A kind of (supplementary explanation 26) microcomputer, is configured to generate second clock signal and believes second clock It number it is output to sensor, is configured to output sampled data, is held by the analog signal to instruction testing result Row analog/digital conversion digital signal generated, analog signal be based on the first clock signal sampled, microcomputer also by It is configured to read sampled data from sensor, wherein the frequency of the first clock signal is based on second clock signal by sensing Device corrects.

(supplementary explanation 27) is according to the microcomputer of supplementary explanation 26, comprising: clock-signal generator is configured to Generate second clock signal；And second input/output interface, it is configured to execute the data communication with sensor.

(supplementary explanation 28) is according to the microcomputer of supplementary explanation 26, wherein sensor includes: the first input/output Interface is configured to execute the data communication with microcomputer；Detector is configured to export the result conduct of detection Analog signal；Oscillator, is configured to export the first clock signal, and the control signal that frequency has been based on supply comes school Just；Frequency corrector is configured to based on the second clock received via the first input/output interface from microcomputer Signal, output control signal；Analog/digital converter is configured to adopt analog signal based on the first clock signal Sample executes analog/digital conversion to sampled analog signal and exports sampled data；And memory, it is configured to Store sampled data.

(supplementary explanation 29) is according to the microcomputer of supplementary explanation 28, wherein microcomputer is read when it from memory Second clock signal is exported when sampled data out.

(supplementary explanation 30) is according to the sensor of supplementary explanation 28, wherein frequency corrector includes: frequency divider, is matched It is set to and the frequency of second clock signal is divided；First frequency/electric pressure converter, when being configured to export instruction first First signal of the frequency of clock signal；Second frequency/electric pressure converter is configured to export the letter that instruction is divided by frequency divider Number frequency second signal；Difference amplifier is configured to export the difference between the first signal of instruction and second signal The signal of voltage；Comparator is configured to compare second signal with the signal with predetermined value and exports instruction ratio Compared with result switching signal；Voltage hold circuit is configured to be kept exporting from difference amplifier according to switching signal The voltage of signal；Switch is configured to the output of the output of difference amplifier and voltage hold circuit according to switching signal In one connect with oscillator, wherein oscillator is connected to the output of difference amplifier, makes defeated from difference amplifier The voltage of signal out is input into oscillator as control signal, and oscillator is connected to the defeated of voltage hold circuit Out, the voltage kept by voltage hold circuit is made to be input into oscillator as control signal.

(supplementary explanation 31) is according to the microcomputer of supplementary explanation 30, wherein switch is when second clock signal is from miniature Oscillator is connected with the output of difference amplifier when computer is entered, and is switched when second clock signal is not from microcomputer Oscillator is connected with the output of voltage hold circuit when calculation machine is entered.

(supplementary explanation 32) is according to the microcomputer of supplementary explanation 28, wherein microcomputer can be by reset signal It is output to sensor, according to the read requests from microcomputer, memory instruction is had been received after reset signal The serial datas of number of sampling of data be output to microcomputer, and microcomputer together with corresponding sampled data Further include computing circuit, is configured to based on the reference time when reset signal is exported, the sampling in sensor Period and the serial data received, calculate the sampling time of the sampled data received.

(supplementary explanation 33) is according to the microcomputer of supplementary explanation 7, wherein computing circuit will pass through the string that will be received The value of row data is added to the reference time multiplied by sampling period value obtained to calculate the sampling time.

(supplementary explanation 34) is according to the microcomputer of supplementary explanation 33, wherein computing circuit is also added from when operation electricity To the delay time when serial data is reset to calculate the sampling time when road exports the reset signal.

(supplementary explanation 35) is according to the microcomputer of supplementary explanation 33, wherein when computing circuit is also added based on first Delay time needed for clock signal converts analog signals into sampled data is to calculate the sampling time.

(supplementary explanation 36) is according to the microcomputer of supplementary explanation 32, wherein is asked whenever reading from microcomputer When asking, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 37) is according to the microcomputer of supplementary explanation 32, wherein is asked whenever reading from microcomputer When seeking pre-determined number, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 38) is according to the microcomputer of supplementary explanation 32, including multiple sensors, wherein microcomputer Based on the sampling time calculated, will be associated with each other simultaneously by the sampled data of multiple sensor samples.

(supplementary explanation 39) is according to the microcomputer of supplementary explanation 28, wherein microcomputer is read when it from sensor Second clock signal is exported when sampled data out.

(supplementary explanation 40) is according to the microcomputer of supplementary explanation 28, wherein microcomputer can be defeated by reset signal Sensor is arrived out, and according to the read requests from microcomputer, sensor instruction is had been received after reset signal The serial data of the number of the sampling of data is output to microcomputer together with corresponding sampled data, and microcomputer is also Including computing circuit, it is configured to based on the reference time when reset signal is exported, the week of the sampling in sensor Phase and the serial data received, calculate the sampling time of the sampled data received.

A kind of (supplementary explanation 41) method for correcting detection system, comprising: generate second clock signal；Second clock is believed Number from from sensor read sampled data microcomputer be output to be configured to output sampled data sensor, It is that analog/digital conversion digital signal generated is executed by the analog signal to instruction testing result, analog signal is based on First clock signal is sampled, and makes sensor and correct based on second clock signal the frequency of the first clock signal.

(supplementary explanation 42) is according to the method for the correction detection system of supplementary explanation 41, wherein sensor includes: first defeated Enter/output interface, is configured to execute the data communication with microcomputer；Detector is configured to export detection As a result it is used as analog signal；Oscillator, is configured to export the first clock signal, and frequency has been based on the control letter of supply It number corrects；Frequency corrector is configured to based on received via the first input/output interface from microcomputer Two clock signals, output control signal；Analog/digital converter is configured to based on the first clock signal to analog signal It is sampled, analog/digital conversion is executed to sampled analog signal and exports sampled data；And memory, quilt It is configured to storage sampled data, wherein microcomputer includes: clock-signal generator, is configured to generate second clock Signal；And second input/output interface, it is configured to execute the data communication with sensor.

(supplementary explanation 43) is according to the method for the correction detection system of supplementary explanation 42, including microcomputer is made to work as it Second clock signal is exported when reading sampled data from memory.

(supplementary explanation 44) is according to the method for the correction detection system of supplementary explanation 42, wherein frequency corrector includes: point Frequency device is configured to divide the frequency of second clock signal；First frequency/electric pressure converter is configured to defeated The first signal of the frequency of the first clock signal is indicated out；Second frequency/electric pressure converter is configured to export instruction by dividing The second signal of the frequency of the signal of frequency device frequency dividing；Difference amplifier is configured to export the first signal of instruction and the second letter The signal of differential voltage between number；Comparator is configured to the signal with predetermined value compare second signal simultaneously And the switching signal of output instruction comparison result；Voltage hold circuit is configured to be kept according to switching signal from difference The voltage of the signal of amplifier output；Switch is configured to be protected the output of difference amplifier and voltage according to switching signal One in the output of circuit is held to connect with oscillator, wherein oscillator is connected to the output of difference amplifier, make from The voltage of the signal of difference amplifier output is input into oscillator as control signal, and oscillator is connected to voltage guarantor The output for holding circuit makes the voltage kept by voltage hold circuit be input into oscillator as control signal.

(supplementary explanation 45) is according to the method for the correction detection system of supplementary explanation 44, including to switch and work as second clock Oscillator is connected with the output of difference amplifier when signal is entered from microcomputer, and switch is made to work as second clock Oscillator is connected with the output of voltage hold circuit when signal is not entered from microcomputer.

(supplementary explanation 46) is according to the method for the correction detection system of supplementary explanation 44, wherein microcomputer being capable of general Reset signal is output to sensor, and method makes according to the read requests from microcomputer, and memory has connect instruction The serial data for receiving the number of the data sampling after reset signal is output to microcomputer together with corresponding sampled data, And method makes microcomputer based on the reference time when reset signal is exported, the sampling period in sensor With the serial data received, the sampling time of the sampled data received is calculated.

(supplementary explanation 47) according to the method for the correction detection system of supplementary explanation 46, including will be by the string that will receive The value of row data is added to the reference time multiplied by sampling period value obtained to calculate the sampling time.

(supplementary explanation 48) further includes adding from working as reset signal according to the method for the correction detection system of supplementary explanation 47 To the delay time when serial data is reset to calculate the sampling time when being exported.

(supplementary explanation 49) further includes addition based on the first clock according to the method for the correction detection system of supplementary explanation 47 Delay time needed for signal converts analog signals into sampled data is to calculate the sampling time.

(supplementary explanation 50) is according to the method for the correction detection system of supplementary explanation 46, wherein whenever reading is from microcomputer When calculation machine is requested, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 51) is according to the method for the correction detection system of supplementary explanation 46, wherein whenever reading is from microcomputer When calculation machine is requested pre-determined number, serial data is output to microcomputer together with corresponding sampled data.

(supplementary explanation 52) is according to the method for the correction detection system of supplementary explanation 46, wherein multiple sensors are provided And it is based on the sampling time calculated, will be associated with each other simultaneously by the sampled data of multiple sensor samples.

Although describing the present invention according to several embodiments, those skilled in the art will recognize that, this hair Various modifications in the bright spirit and scope that can use claims are practiced and the present invention is not limited to described above Example.

Further, the scope of the claims is not limited by embodiments described above.

Furthermore, it should be noted that arriving, it is intended that being also covered by all authority even if being modified later in course of the review and wanting Seek the equivalent of element.

Claims

1. a kind of detection system, comprising:

Sensor, the sensor are configured to output sampled data, and the sampled data is by instruction detection knot The digital signal that the analog signal of fruit executes analog/digital conversion to generate, the analog signal are based on the first clock signal quilt Sampling；And

Microcomputer, the microcomputer are configured to generate the second clock signal and second clock signal is defeated The sensor is arrived out, and reads the sampled data from the sensor,

Wherein, the sensor corrects the frequency of first clock signal based on the second clock signal.

2. detection system according to claim 1, wherein

The sensor includes:

First input/output interface, first input/output interface are configured to execute the data with the microcomputer Communication；

Detector, the detector are configured to export the result of detection as the analog signal；

Oscillator, the oscillator are configured to export first clock signal, and the frequency of first clock signal is Control signal based on supply is corrected；

Frequency corrector, the frequency corrector be configured to based on via first input/output interface from described miniature The second clock signal that computer receives, exports the control signal；

Analog/digital converter, the analog/digital converter are configured to based on first clock signal to the simulation Signal is sampled, and executes analog/digital conversion to the analog signal sampled, and export the sampled data；With And

Memory, the memory are configured to store the sampled data, and

The microcomputer includes:

Clock-signal generator, the clock-signal generator are configured to generate the second clock signal；And

Second input/output interface, second input/output interface are configured to execute logical with the data of the sensor Letter.

3. detection system according to claim 2, wherein when the microcomputer from the memory read described in adopt When sample data, the microcomputer exports the second clock signal.

4. detection system according to claim 2, wherein

The frequency corrector includes:

Frequency divider, the frequency divider are configured to divide the frequency of the second clock signal；

First frequency/electric pressure converter, the first frequency/electric pressure converter are configured to export the first signal, and described first The frequency of first clock signal described in signal designation；

Second frequency/electric pressure converter, the second frequency/electric pressure converter are configured to export second signal, and described second The frequency for the signal that signal designation is divided by the frequency divider；

Difference amplifier, the difference amplifier, which is configured to export, to be indicated between first signal and the second signal The signal of differential voltage；

Comparator, the comparator is configured to compare the second signal with the signal with predetermined value, and exports Indicate the switching signal of comparison result；

Voltage hold circuit, the voltage hold circuit are configured to be kept according to the switching signal from the difference amplifier The voltage of the signal of output；And

Switch, the switch are configured to be kept the output of the difference amplifier and the voltage according to the switching signal One in the output of circuit connect with the oscillator,

The oscillator is connected to the output of the difference amplifier, this makes the signal exported from the difference amplifier Voltage is input into the oscillator as the control signal, and

The oscillator is connected to the output of the voltage hold circuit, this makes the electricity kept by the voltage hold circuit Pressure is input into the oscillator as the control signal.

5. detection system according to claim 4, wherein

It is described to switch the output of the difference amplifier when the second clock signal is entered from the microcomputer It is connect with the oscillator, and

It is described to switch the voltage hold circuit when the second clock signal is not entered from the microcomputer Output is connect with the oscillator.

6. detection system according to claim 2, wherein

Reset signal can be output to the sensor by the microcomputer,

According to the read requests from the microcomputer, the memory by instruction have been received the reset signal it The serial data of the number of the sampling of the data afterwards is output to the microcomputer together with corresponding sampled data, and

The microcomputer further includes computing circuit, the computing circuit be configured to based on when the reset signal by Reference time when output, the sampling period in the sensor and the serial data received, calculate the institute received State the sampling time of sampled data.

7. detection system according to claim 6, wherein following values are added to the reference time by the computing circuit To calculate the sampling time, described value is by obtaining the value of the serial data received multiplied by the sampling period 's.

8. detection system according to claim 7, wherein the computing circuit is also added from when the computing circuit exports To the delay time when the serial data is reset when the reset signal, to calculate the sampling time.

9. detection system according to claim 7, wherein the computing circuit is also added based on first clock signal Delay time needed for the analog signal is converted to the sampled data, to calculate the sampling time.

10. detection system according to claim 6, wherein whenever requesting to read from the microcomputer, the string Row data are output to the microcomputer together with corresponding sampled data.

11. detection system according to claim 6, wherein predetermined time whenever requesting to read from the microcomputer When number, the serial data is output to the microcomputer together with corresponding sampled data.

12. detection system according to claim 6, including multiple sensors, wherein the detection system is based on calculating The sampling time will be associated with each other by the sampled data of the multiple sensor sample simultaneously.

13. a kind of sensor, the sensor is configured to output sampled data, and the sampled data is by instruction The digital signal that the analog signal of testing result executes analog/digital conversion to generate, the analog signal are based on the first clock Signal is sampled, wherein

The sensor corrects the frequency of first clock signal based on the second clock signal generated by microcomputer, And

The sampled data is read by the microcomputer.

14. sensor according to claim 13, comprising:

Frequency corrector, the frequency corrector be configured to based on via first input/output interface from described miniature The second clock signal that computer receives, to export the control signal；

Memory, the memory are configured to store the sampled data.

15. sensor according to claim 14, wherein

The frequency corrector includes:

Switch, the switch are configured to be kept the output of the difference amplifier and the voltage according to the switching signal One in the output of circuit connect with the oscillator, wherein

16. sensor according to claim 15, wherein

17. a kind of microcomputer, the microcomputer is configured to generate second clock signal and when by described second Clock signal is output to sensor, and the sensor is configured to output sampled data, and the sampled data is by finger Show the digital signal that the analog signal of testing result executes analog/digital conversion to generate, when the analog signal is based on first Clock signal is sampled, and the microcomputer is further configured to that the sampled data can be read from the sensor,

Wherein, the frequency of first clock signal is corrected by the sensor based on the second clock signal.

18. microcomputer according to claim 17, comprising:

19. microcomputer according to claim 18, wherein when the microcomputer reads institute from the sensor When stating sampled data, the microcomputer exports the second clock signal.

20. microcomputer according to claim 18, wherein

Reset signal can be output to the sensor by the microcomputer,

According to the read requests from the microcomputer, the sensor by instruction have been received the reset signal it The serial data of the number of the sampling of the data afterwards is output to the microcomputer together with corresponding sampled data, and