CN109067210B

CN109067210B - Self-adaptive time delay compensation active rectifier circuit

Info

Publication number: CN109067210B
Application number: CN201811209212.5A
Authority: CN
Inventors: 马彦昭; 崔楷; 樊晓桠
Original assignee: Northwestern Polytechnical University
Current assignee: Shenzhen Aixiesheng Technology Co Ltd
Priority date: 2018-10-17
Filing date: 2018-10-17
Publication date: 2020-06-16
Anticipated expiration: 2038-10-17
Also published as: CN109067210A

Abstract

Compared with the delay compensation rectifier circuit structure provided in the background technology, the circuit adopts a single loop to simultaneously compensate the on-delay and the off-delay, reduces the number of used sampling capacitors by a half, avoids a voltage-current conversion circuit, reduces the area and the power consumption of a chip, and is beneficial to the low power consumption and the miniaturization of the chip. Since the feedback loop can dynamically adjust the delay, the effects of temperature, process and supply voltage (PVT) variations are avoided.

Description

Self-adaptive time delay compensation active rectifier circuit

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a self-adaptive time delay compensation active rectifier circuit.

Background

The active rectifier is widely applied to low-power-consumption on-chip integrated systems such as an energy collection system, a wireless charging system, a microcontroller and the like. The traditional bridge rectifier is realized by 4 diodes, and extra voltage margin is consumed due to the conduction voltage drop of the diodes. The active rectifier utilizes the active diode to replace the diode in the traditional bridge rectifier, and improves the energy transmission efficiency. However, the delay of the comparator in the active diode changes with the working condition, so that the voltage when the active diode is turned on or off is not equal to zero, the on delay causes the current on time to be shortened, and simultaneously, the peak current is generated, and the off delay causes the reverse current, and these effects can cause the energy transmission efficiency to be reduced.

[ document 1 ] L.Cheng, W.H.Ki, Y.Lu and T.S.Yim, "Adaptive on/off delay-compensated active receivers for wireless power transfer systems," IEEEjournal of Solid-State Circuits, vol.51, No.3, pp.712-723, Mar.2016.

The current research on the delay compensation problem of the active rectifier is mainly shown in document 1, in which a related loop offset current delay compensation circuit can adaptively compensate the delay of the active rectifier. The on-time delay and the off-time delay of the circuit respectively use an independent feedback regulation loop, and the hardware and the power consumption are larger.

Disclosure of Invention

The technical problem solved by the invention is as follows: in order to overcome the defects of the prior art, the invention provides the self-adaptive delay compensation active rectifier circuit, which adopts a single loop to simultaneously compensate the on-delay and the off-delay, and solves the problem of efficiency reduction caused by the on-off of an active diode. The invention does not need a voltage-current conversion circuit and reduces the number of sampling capacitors, thereby reducing the area and the power consumption of a chip. The invention adopts a feedback loop, and can dynamically compensate different time delays under different temperatures, processes and power supply voltages (PVT).

The technical scheme of the invention is as follows: a self-adaptive time delay compensation active rectifier circuit is characterized by comprising an active rectifier main circuit, a sampling circuit, an offset voltage generating circuit and a logic control circuit, wherein the active rectifier main circuit generates a power tube drain terminal voltage Vac1 in the rectifying process, inputs the power tube drain terminal voltage Vac1 into the sampling circuit and the offset voltage generating circuit, and inputs the offset voltage generating circuit after being processed by a sampling circuit Vac 1; amplified by offset voltage generating circuit and connected with drain voltage V of power tube_ac1After the superposition processing, the offset voltage is transmitted to an active rectifier main circuit to feed back and adjust a comparator, so that delay compensation is completed; meanwhile, the main circuit of the active rectifier generates a power tube grid end control signal V_GN1And the input is a logic control circuit, and the input is respectively input into the active rectifier main circuit, the sampling circuit and the offset voltage generating circuit after being processed by the logic control circuit, so as to realize logic control.

The further technical scheme of the invention is as follows: the main circuit of the active rectifier comprises an NMOS power tube M_N1-M_N2PMOS power tube M_P1-M_P2Comparator CMP1-CMP2, AC power supply V_acCapacitor C_OAnd a load resistance R_L(ii) a AC power supply V_acOne end V of_ac1Connecting NMOS power tube M_N1And PMOS power tube M_P1At the drain end and at the other end V_ac2Connecting NMOS power tube M_N2And PMOS power tube M_P2Drain terminal of (1), NMOS power tube M_N1And NMOS power tube M_N2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube M_P1And PMOS power tube M_P2Source terminal of is commonly connected with V_outTerminal PMOS power tube M_P1The grid end of the PMOS power tube M is connected with_P2Drain terminal of (PMOS) power tube M_P2The grid end of the PMOS power tube M is connected with_P1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit 3_offset1A positive input of the comparator CMP1 and an output V of the offset voltage generating circuit 3_offset2Connected to the output V of the comparator CMP1_GN1And NMOS power tube M_N1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply V_acOne end V of_ac2The non-inverting input of the comparator CMP2 is connected to power ground, the output V of the comparator CMP2_GN2And NMOS power tube M_N2The grid ends are connected; load capacitance C_OAnd a load resistance R_LOne end is connected with V_outAnd one end and the other end are connected with a power ground.

The further technical scheme of the invention is as follows: the sampling circuit comprises a capacitor C_off1-C_off2And switches S1-S2, one end of the switch S2 and the output V of the active rectifier main circuit 1_ac1Connected with the other end of the capacitor C_off2Is connected to one terminal of a switch S1, a capacitor C_off2The other end of the connecting rod is connected with the ground; the other end of the switch S1 and the capacitor C_off1Is connected to one terminal of a capacitor C_off1The other end of which is connected to ground.

The further technical scheme of the invention is as follows: the offset voltage generating circuit comprises a transconductance amplifier and a superposition circuit; input positive phase end of transconductance amplifier and output V of sampling circuit_{off_samp}And the input inverting terminal of the transconductance amplifier is connected with the ground. Transconductance amplifier output V_o1And an output V_o2Connected to the superposition circuit input. Simultaneous superposition circuit input and logic control circuit 4 output S_onAnd output S_offAre connected.

The further technical scheme of the invention is as follows: the logic control circuit 4 comprises an R-S latch L1, an inverter INV1-INV5, a two-input OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1; the input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the Q output end of the R-S latch L1 is connected with the input end of the inverter INV1 and the input end of the delay unit DEL 1. The output of inverter INV1 is connected to the input of inverter INV 2. Inverter INV3 input and active rectifier main circuit 1 output V_GN1Connecting; the output is connected to the input of inverter INV 4. The output of the inverter INV4 is connected to one input of the two-input OR gate OR 1. Inverse phaseThe INV5 input is connected to the two input OR gate 1 output. The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit 1_GN1Are connected. The input of the rising edge detection circuit RED1 and the output V of the active rectifier main circuit 1_GN1Are connected. The falling edge detection circuit FED1 has an input coupled to the delay element DEL 1.

Effects of the invention

The invention has the technical effects that: compared with the delay compensation rectifier circuit structure provided in the background technology, the circuit adopts a single loop to simultaneously compensate the on-delay and the off-delay, reduces the number of sampling capacitors by half, reduces the area and the power consumption of a chip, and is beneficial to the low power consumption and the miniaturization of the chip. Since the feedback loop can dynamically adjust the delay, the effects of temperature, process and supply voltage (PVT) variations are avoided. The device solves the problems of reverse current, current spike and the like caused by the change of the time delay of the comparator along with the working condition in the traditional active rectifier. And the feedback loop is used for adaptively compensating the on-off delay, so that the energy transmission efficiency is improved.

Drawings

FIG. 1 is a block diagram of an adaptive delay-compensated active rectifier according to the present invention

FIG. 2 is a schematic diagram of an adaptive delay compensated active rectifier circuit according to the present invention

FIG. 3 is a timing diagram of the operation of the adaptive delay compensated active rectifier according to the present invention

FIG. 4 is a detailed diagram of an offset voltage generation circuit of an adaptive delay compensation active rectifier according to the present invention

FIG. 5 is a detailed diagram of the logic control circuit of the adaptive delay compensating active rectifier according to the present invention

Detailed Description

Referring to fig. 1 to 5, the rectifier circuit includes an active rectifier main circuit 1, a sampling circuit 2, an offset voltage generating circuit 3, and a logic control circuit 4. The active rectifier circuit comprises an active rectifier main circuit, a sampling circuit, an offset voltage generating circuit and a logic control circuitAnd (4) a way. NMOS power tube M generated by main circuit of active rectifier_N1Of the gate control signal V_GN1Sampling circuit to NMOS power tube M_N1Voltage V at the drain terminal_ac1Sampling is carried out, and a sampling signal is input to the input end of the offset voltage generating circuit. Offset voltage generating circuit generates voltage V_offset1And V_offset2The maladjustment of a comparator in the main circuit of the active rectifier is adjusted to ensure that the NMOS power tube M_N1At its drain terminal voltage V_ac1And off or on at 0.

Output V of active rectifier main circuit 1_ac1An output V of the active rectifier main circuit 1 is connected with the input of the sampling circuit 2 and the input of the offset voltage generating circuit 3_GN1Is connected with the input of the logic control circuit 4; output V of sampling circuit 2_{off_samp}Is connected with the input of the offset voltage generating circuit 3; output V of offset voltage generating circuit 3_offset1And an output V_offset2Is connected with the input of the active rectifier main circuit 1; output S of logic control circuit 4_{off_samp}And output S_holdAn output S of the logic control circuit 4 connected to the input of the sampling circuit 2_offAnd output S_onAn output S of the logic control circuit 4 connected to an input of the offset voltage generating circuit 3_blockConnected to the input of the active rectifier main circuit 1. The active rectifier main circuit 1 generates an NMOS power tube M in the rectification process_N1Of the gate control signal V_GN1And NMOS power tube M is caused by the turn-off delay of the active diode_N1Of the gate control signal V_GN1At M_N1Voltage V at drain terminal_ac1And is flipped by Δ V above ground potential, thus generating a positive phase voltage. Sampling circuit 2 sampling NMOS power tube M_N1Voltage V at drain terminal_ac1And fed back to the input end of the offset voltage generating circuit 3. Offset voltage generating circuit 3 generates voltage V_offset1And V_offset2The maladjustment of the comparator CMP1 in the main circuit 1 of the active rectifier is adjusted to make the NMOS power tube M_N1Of the gate control signal V_GN1At node voltage V_ac1And when the potential is equal to the ground potential, the time is reversed, so that the purpose of compensating the time delay is achieved. NMOS power tube M_N1The gate control signal VGN1 is input to the logic control circuit 4,generating switch control signals in other circuits.

The active rectifier main circuit 1 is composed of an NMOS power tube M_N1-M_N2PMOS power tube M_P1-M_P2Comparator CMP1-CMP2, AC power supply V_acCapacitor C_OAnd a load resistance R_LAnd (4) forming. AC power supply V_acOne end V of_ac1Connecting NMOS power tube M_N1And PMOS power tube M_P1At the drain end and at the other end V_ac2Connecting NMOS power tube M_N2And PMOS power tube M_P2Drain terminal of (1), NMOS power tube M_N1And NMOS power tube M_N2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube M_P1And PMOS power tube M_P2Source terminal of is commonly connected with V_outTerminal PMOS power tube M_P1The grid end of the PMOS power tube M is connected with_P2Drain terminal of (PMOS) power tube M_P2The grid end of the PMOS power tube M is connected with_P1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit 3_offset1A positive input of the comparator CMP1 and an output V of the offset voltage generating circuit 3_offset2Connected to the output V of the comparator CMP1_GN1And NMOS power tube M_N1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply V_acOne end V of_ac2The non-inverting input of the comparator CMP2 is connected to power ground, the output V of the comparator CMP2_GN2And NMOS power tube M_N2The grid ends are connected; load capacitance C_OAnd a load resistance R_LOne end is connected with V_outAnd one end and the other end are connected with a power ground.

The sampling circuit 2 is composed of a capacitor C_off1-C_off2And switches S1-S2. One end of switch S2 and output V of active rectifier main circuit 1_ac1Connected with the other end of the capacitor C_off2Is connected to one terminal of a switch S1, a capacitor C_off2The other end of which is connected to ground. The other end of the switch S1 and the capacitor C_off1Is connected to one terminal of a capacitor C_off1The other end of which is connected to ground.

The offset voltage generating circuit 3 is composed of a transconductance amplifier and a superposition circuit. Transconductance amplifier inputThe positive phase input end and the output V of the sampling circuit 2_{off_samp}And the input inverting terminal of the transconductance amplifier is connected with the ground. Transconductance amplifier output V_o1And an output V_o2Connected to the superposition circuit input. Simultaneous superposition circuit input and logic control circuit 4 output S_onAnd output S_offAre connected.

The logic control circuit 4 is composed of an R-S latch L1, an inverter INV1-INV5, a two-input OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1. The input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the Q output end of the R-S latch L1 is connected with the input end of the inverter INV1 and the input end of the delay unit DEL 1. The output of inverter INV1 is connected to the input of inverter INV 2. Inverter INV3 input and active rectifier main circuit 1 output V_GN1Connecting; the output is connected to the input of inverter INV 4. The output of the inverter INV4 is connected to one input of the two-input OR gate OR 1. The inverter INV5 has its input connected to the two-input OR gate OR1 output. The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit 1_GN1Are connected. The input of the rising edge detection circuit RED1 and the output V of the active rectifier main circuit 1_GN1Are connected. The falling edge detection circuit FED1 has an input coupled to the delay element DEL 1.

Reference is made to fig. 2-4. When AC source V_acOne end V_ac1Above 0, the comparator CMP1 output is low, V_GN10, NMOS power tube M_N1Turn off, simultaneously S_{off_samp}＝0，S_off＝1，S_onWhen the output voltage V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is equal to 0, the switch S2, the switch S4, and the switch S5 are turned off, the switch S3 and the switch S6 are turned on, and the output voltage V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is set to zero_o1And V_o2Is connected to node a and node B. Capacitor C due to turn-off delay of comparator CMP1_off2Sampling positive phase voltage, i.e. V_{ac1_off}. When S is_holdWhen the value is 1, the switch S1 is turned on, and the capacitor C is turned on_off2Charge on is shared to the capacitor C_off1To generate a sampling voltage V_{off_samp}And the input is input to the positive end of the input of the transconductance amplifier. Two-way output V of transconductance amplifier_o1And V_o2Is clamped by a node A and a node B of a second-stage superposition circuit to output V_o1And V_o2Injected as currents into node a and node B, respectively. Offset generation circuit 3 output V_offset1And V_offset2Are respectively as

V_offset1＝V_ac1+g_m1,2V_{off_samp}(R_3A+R_4A) (1)

V_offset2＝0+g_m1,2V_{off_samp}R_4B(2)

As shown in formula (1) and formula (2), due to R_3A＝R_3B，R_4A＝R_4B，V_offset1Equivalent to an alternating current source V_acOne terminal voltage V_ac1Source follower signal and transconductance amplifier output V_o1Overlap of (V)_offset2The source equivalent to ground follows the signal. Thus, according to equations (1) and (2), V is measured when zero-voltage switching is performed_offset2Ratio V_offset1High g_m1,2V_{off_samp}R_3BIt is equivalent to increase the positive phase offset voltage at the inverting terminal of the comparator, thereby compensating the conduction delay through feedback.

When AC source V_acOne end V_ac1Below 0, the comparator CMP1 output is high, V _GN11, NMOS power transistor M_N1Conducting while S_{off_samp}＝1，S_off＝0，S_onWhen the output V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is equal to 1, the switch S2, the switch S4, and the switch S5 are turned on, the switch S3, and the switch S6 are turned off_o1And V_o2Connected to node C and node D. Capacitor C due to turn-off delay of comparator CMP1_off2Sampling positive phase voltage, i.e. V_{ac1_off}. When S is_holdWhen the value is 1, the switch S1 is turned on, and the capacitor C is turned on_off2Charge on is shared to the capacitor C_off1To generate a sampling voltage V_{off_samp}And the input is input to the positive end of the input of the transconductance amplifier. Two-way output V of transconductance amplifier_o1And V_o2Is equal and clamped by a node C and a node D of a second-stage superposition circuit to output V_o1And V_o2Injecting into nodes C and C, respectively, in the form of currentsAnd D, a node D. Offset generation circuit 3 output V_offset1And V_offset2Are respectively as

V_offset1＝V_ac1+g_m1,2V_{off_samp}R_4A(3)

V_offset2＝0+g_m1,2V_{off_samp}(R_3B+R_4B) (4)

As shown in formula (3) and formula (4), due to R_3A＝R_3B，R_4A＝R_4B，V_offset1Equivalent to an alternating current source V_acOne terminal voltage V_ac1Source follow signal of, V_offset2Ground-equivalent source-follower signal and transconductance amplifier output V_o1And (3) superposition. According to the expressions (3) and (4), when zero-voltage switching is performed, V_offset1Ratio V_offset2High g_m1,2V_{off_samp}R_3BIt is equivalent to add an inverting offset voltage at the inverting terminal of the comparator, thereby compensating the turn-off delay. Therefore, by the switching circuit, the on and off delays can be compensated at the same time in the same cycle.

The self-adaptive delay compensation active rectifier offset voltage generating circuit of the invention provides the following specific embodiments:

the offset voltage generating circuit 3 is composed of a MOS transistor M₁-M₁₇Resistance R₁-R₂Resistance R_3A-R_3BResistance R_4A-R_4BCapacitor C₁-C₂And switches S3-S6. PMOS tube M₁And PMOS transistor M₂Form a differential pair structure, a PMOS transistor M₁The grid end of the NMOS tube M is connected with the ground, the drain end of the NMOS tube M is connected with the drain end of the NMOS tube₃The drain ends of the two are connected. PMOS tube M₂And the output V of the sampling circuit 2_{off_samp}Connected with drain terminal of NMOS transistor M₅The drain ends of the two are connected. PMOS tube M₁Source terminal and PMOS tube M₂Source end of the PMOS transistor M is connected in parallel₇The drain terminal of (1). NMOS tube M₃NMOS transistor M₄The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the transformer is connected with the ground. NMOS tube M₅NMOS transistor M₁₁NMOS transistor M₁₂The gate terminals of which are connected to form a current mirror structure(ii) a The source end of the transformer is connected with the ground. PMOS tube M₆PMOS transistor M₇The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M₇The drain terminal is a PMOS tube M₁And PMOS transistor M₂The resulting differential pair structure provides a tail current. PMOS tube M₈Drain terminal and NMOS tube M₄The drain ends of the two are connected. PMOS tube M₈PMOS transistor M₉PMOS transistor M₁₀The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M₁₃PMOS transistor M₁₄PMOS transistor M₁₅The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M₁₆And PMOS transistor M₁₇Is a source follower structure. NMOS tube M₁₆Output V of main circuit 1 of gate terminal and active rectifier_ac1Connected with the source end and the resistor R_4AAre connected. NMOS tube M₁₇The grid terminal is connected with the ground, the source terminal is connected with the resistor R_4BAre connected. NMOS tube M₁₆NMOS transistor M₁₇And the source end is connected with the ground. Resistance R₁One terminal and output V of transconductance amplifier_o1Connected with the other end of the capacitor C₁Serially connected to ground, a frequency compensation branch is formed. Resistance R₂One terminal and output V of transconductance amplifier_o2Connected with the other end of the capacitor C₂Serially connected to ground, a frequency compensation branch is formed. The switches S3-S6 are MOS switching devices, and the switches S3 and S6 have their gate terminals connected in parallel with the signal S_off(ii) a A switch S4, a switch S5, a grid end connected with the signal S_on. A switch S3 and a switch S5, one end of which is connected in parallel with the output V of the transconductance amplifier_o1And the other end is connected with a resistor R_3AThe nodes A and C at two ends are connected; a switch S4 and a switch S6, one end of which is connected in parallel with the output V of the transconductance amplifier_o2And the other end is connected with a resistor R_3BNode B and node D are connected at both ends, and output V of the node A-D clamped transconductance amplifier_o1And an output V_o2. PMOS tube M₁₆-M₁₇Resistance R_3A-R_3BAnd the switches S3-S6 form a superposed circuit for alternately compensating the turn-on delay and the turn-off delay of the active rectifier.

Claims

1. A self-adaptive time delay compensation active rectifier circuit is characterized by comprising an active rectifier main circuit (1), a sampling circuit (2), an offset voltage generating circuit (3) and a logic control circuit (4), wherein the active rectifier main circuit (1) generates a power tube drain end voltage Vac1 in a rectifying process, inputs the power tube drain end voltage Vac1 into the sampling circuit (2) and the offset voltage generating circuit (3), and inputs the offset voltage generating circuit (3) after being processed by the sampling circuit (2) through sampling Vac 1; amplified by an offset voltage generating circuit (3) and connected with the drain end voltage V of the power tube_ac1After the superposition processing, the offset voltage is transmitted into an active rectifier main circuit (1) to feed back and adjust a comparator, so that delay compensation is completed; meanwhile, the main circuit (1) of the active rectifier generates a power tube grid end control signal V_GN1The voltage is input into a logic control circuit (4), and is respectively input into an active rectifier main circuit (1), a sampling circuit (2) and an offset voltage generating circuit (3) after being processed by the logic control circuit (4), so that logic control is realized; the active rectifier main circuit (1) comprises an NMOS power tube M_N1-M_N2PMOS power tube M_P1-M_P2Comparator CMP1-CMP2, AC power supply V_acCapacitor C_OAnd a load resistance R_L(ii) a AC power supply V_acOne end V of_ac1Connecting NMOS power tube M_N1And PMOS power tube M_P1At the drain end and at the other end V_ac2Connecting NMOS power tube M_N2And PMOS power tube M_P2Drain terminal of (1), NMOS power tube M_N1And NMOS power tube M_N2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube M_P1And PMOS power tube M_P2Source terminal of is commonly connected with V_outTerminal PMOS power tube M_P1The grid end of the PMOS power tube M is connected with_P2Drain terminal of (PMOS) power tube M_P2The grid end of the PMOS power tube M is connected with_P1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit (3)_offset1Connected to the positive input of the comparator CMP1 and the output V of the offset voltage generating circuit (3)_offset2Connected to the output V of the comparator CMP1_GN1And NMOS power tube M_N1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply V_acOne end V of_ac2Comparator CMP2 with its non-inverting input connected to power ground, output V of comparator CMP2_GN2And NMOS power tube M_N2The grid ends are connected; load capacitance C_OAnd a load resistance R_LOne end is connected with V_outThe other end is connected with a power ground; the offset voltage generating circuit (3) comprises a transconductance amplifier and a superposition circuit; the input positive phase end of the transconductance amplifier and the output V of the sampling circuit (2)_{off_samp}The input inverting end of the transconductance amplifier is connected with the ground; transconductance amplifier output V_o1And an output V_o2Is connected with the input of the superposition circuit; simultaneous superposition circuit input and logic control circuit (4) output S_onAnd output S_offAre connected.

2. An adaptive delay-compensated active rectifier circuit as claimed in claim 1, characterized in that the sampling circuit (2) comprises a capacitor C_off1-C_off2And switches S1-S2, one end of the switch S2 and the output V of the active rectifier main circuit 1_ac1Connected with the other end of the capacitor C_off2Is connected to one terminal of a switch S1, a capacitor C_off2The other end of the connecting rod is connected with the ground; capacitor C_off1As an output port of the sampling circuit 2, and is connected to the other end of the switch S1, and a capacitor C_off1The other end of the connecting rod is connected with the ground; the output voff-samp of the sampling circuit 2 is connected to an input of the offset voltage generating circuit 3.

3. An adaptive delay compensating active rectifier circuit as claimed in claim 1, wherein the logic control circuit (4) comprises an R-S latch L1, an inverter INV1-INV5, a two-input OR gate OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1; the input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the output Q end of the R-S latch L1 is connected with the input of an inverter INV1 and the input of a delay unit DEL 1; the output of the inverter INV1 is connected with the input of the inverter INV 2; inverter INV3 input and active rectifier main circuit 1 output V_GN1Connecting; inverter INV3 output and inverterINV4 input connection; the output of the inverter INV4 is connected with the input of one end of a two-input OR gate 1; the input of the inverter INV5 is connected with the output of a two-input OR gate 1; deriving S from the output of a two-input OR gate 1_offSignal, S is obtained from the output terminal of inverter INV5_onSignal_；The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit (1)_GN1Connecting; the input of the rising edge detection circuit RED1 is connected with the delay unit DEL 1; the input of the falling edge detection circuit FED1 and the output V of the active rectifier main circuit (1)_GN1Are connected.