CN109067210B - Self-adaptive time delay compensation active rectifier circuit - Google Patents
Self-adaptive time delay compensation active rectifier circuit Download PDFInfo
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- CN109067210B CN109067210B CN201811209212.5A CN201811209212A CN109067210B CN 109067210 B CN109067210 B CN 109067210B CN 201811209212 A CN201811209212 A CN 201811209212A CN 109067210 B CN109067210 B CN 109067210B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
Compared with the delay compensation rectifier circuit structure provided in the background technology, the circuit adopts a single loop to simultaneously compensate the on-delay and the off-delay, reduces the number of used sampling capacitors by a half, avoids a voltage-current conversion circuit, reduces the area and the power consumption of a chip, and is beneficial to the low power consumption and the miniaturization of the chip. Since the feedback loop can dynamically adjust the delay, the effects of temperature, process and supply voltage (PVT) variations are avoided.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a self-adaptive time delay compensation active rectifier circuit.
Background
The active rectifier is widely applied to low-power-consumption on-chip integrated systems such as an energy collection system, a wireless charging system, a microcontroller and the like. The traditional bridge rectifier is realized by 4 diodes, and extra voltage margin is consumed due to the conduction voltage drop of the diodes. The active rectifier utilizes the active diode to replace the diode in the traditional bridge rectifier, and improves the energy transmission efficiency. However, the delay of the comparator in the active diode changes with the working condition, so that the voltage when the active diode is turned on or off is not equal to zero, the on delay causes the current on time to be shortened, and simultaneously, the peak current is generated, and the off delay causes the reverse current, and these effects can cause the energy transmission efficiency to be reduced.
[ document 1 ] L.Cheng, W.H.Ki, Y.Lu and T.S.Yim, "Adaptive on/off delay-compensated active receivers for wireless power transfer systems," IEEEjournal of Solid-State Circuits, vol.51, No.3, pp.712-723, Mar.2016.
The current research on the delay compensation problem of the active rectifier is mainly shown in document 1, in which a related loop offset current delay compensation circuit can adaptively compensate the delay of the active rectifier. The on-time delay and the off-time delay of the circuit respectively use an independent feedback regulation loop, and the hardware and the power consumption are larger.
Disclosure of Invention
The technical problem solved by the invention is as follows: in order to overcome the defects of the prior art, the invention provides the self-adaptive delay compensation active rectifier circuit, which adopts a single loop to simultaneously compensate the on-delay and the off-delay, and solves the problem of efficiency reduction caused by the on-off of an active diode. The invention does not need a voltage-current conversion circuit and reduces the number of sampling capacitors, thereby reducing the area and the power consumption of a chip. The invention adopts a feedback loop, and can dynamically compensate different time delays under different temperatures, processes and power supply voltages (PVT).
The technical scheme of the invention is as follows: a self-adaptive time delay compensation active rectifier circuit is characterized by comprising an active rectifier main circuit, a sampling circuit, an offset voltage generating circuit and a logic control circuit, wherein the active rectifier main circuit generates a power tube drain terminal voltage Vac1 in the rectifying process, inputs the power tube drain terminal voltage Vac1 into the sampling circuit and the offset voltage generating circuit, and inputs the offset voltage generating circuit after being processed by a sampling circuit Vac 1; amplified by offset voltage generating circuit and connected with drain voltage V of power tubeac1After the superposition processing, the offset voltage is transmitted to an active rectifier main circuit to feed back and adjust a comparator, so that delay compensation is completed; meanwhile, the main circuit of the active rectifier generates a power tube grid end control signal VGN1And the input is a logic control circuit, and the input is respectively input into the active rectifier main circuit, the sampling circuit and the offset voltage generating circuit after being processed by the logic control circuit, so as to realize logic control.
The further technical scheme of the invention is as follows: the main circuit of the active rectifier comprises an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparator CMP1-CMP2, AC power supply VacCapacitor COAnd a load resistance RL(ii) a AC power supply VacOne end V ofac1Connecting NMOS power tube MN1And PMOS power tube MP1At the drain end and at the other end Vac2Connecting NMOS power tube MN2And PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1And NMOS power tube MN2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube MP1And PMOS power tube MP2Source terminal of is commonly connected with VoutTerminal PMOS power tube MP1The grid end of the PMOS power tube M is connected withP2Drain terminal of (PMOS) power tube MP2The grid end of the PMOS power tube M is connected withP1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit 3offset1A positive input of the comparator CMP1 and an output V of the offset voltage generating circuit 3offset2Connected to the output V of the comparator CMP1GN1And NMOS power tube MN1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply VacOne end V ofac2The non-inverting input of the comparator CMP2 is connected to power ground, the output V of the comparator CMP2GN2And NMOS power tube MN2The grid ends are connected; load capacitance COAnd a load resistance RLOne end is connected with VoutAnd one end and the other end are connected with a power ground.
The further technical scheme of the invention is as follows: the sampling circuit comprises a capacitor Coff1-Coff2And switches S1-S2, one end of the switch S2 and the output V of the active rectifier main circuit 1ac1Connected with the other end of the capacitor Coff2Is connected to one terminal of a switch S1, a capacitor Coff2The other end of the connecting rod is connected with the ground; the other end of the switch S1 and the capacitor Coff1Is connected to one terminal of a capacitor Coff1The other end of which is connected to ground.
The further technical scheme of the invention is as follows: the offset voltage generating circuit comprises a transconductance amplifier and a superposition circuit; input positive phase end of transconductance amplifier and output V of sampling circuitoff_sampAnd the input inverting terminal of the transconductance amplifier is connected with the ground. Transconductance amplifier output Vo1And an output Vo2Connected to the superposition circuit input. Simultaneous superposition circuit input and logic control circuit 4 output SonAnd output SoffAre connected.
The further technical scheme of the invention is as follows: the logic control circuit 4 comprises an R-S latch L1, an inverter INV1-INV5, a two-input OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1; the input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the Q output end of the R-S latch L1 is connected with the input end of the inverter INV1 and the input end of the delay unit DEL 1. The output of inverter INV1 is connected to the input of inverter INV 2. Inverter INV3 input and active rectifier main circuit 1 output VGN1Connecting; the output is connected to the input of inverter INV 4. The output of the inverter INV4 is connected to one input of the two-input OR gate OR 1. Inverse phaseThe INV5 input is connected to the two input OR gate 1 output. The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit 1GN1Are connected. The input of the rising edge detection circuit RED1 and the output V of the active rectifier main circuit 1GN1Are connected. The falling edge detection circuit FED1 has an input coupled to the delay element DEL 1.
Effects of the invention
The invention has the technical effects that: compared with the delay compensation rectifier circuit structure provided in the background technology, the circuit adopts a single loop to simultaneously compensate the on-delay and the off-delay, reduces the number of sampling capacitors by half, reduces the area and the power consumption of a chip, and is beneficial to the low power consumption and the miniaturization of the chip. Since the feedback loop can dynamically adjust the delay, the effects of temperature, process and supply voltage (PVT) variations are avoided. The device solves the problems of reverse current, current spike and the like caused by the change of the time delay of the comparator along with the working condition in the traditional active rectifier. And the feedback loop is used for adaptively compensating the on-off delay, so that the energy transmission efficiency is improved.
Drawings
FIG. 1 is a block diagram of an adaptive delay-compensated active rectifier according to the present invention
FIG. 2 is a schematic diagram of an adaptive delay compensated active rectifier circuit according to the present invention
FIG. 3 is a timing diagram of the operation of the adaptive delay compensated active rectifier according to the present invention
FIG. 4 is a detailed diagram of an offset voltage generation circuit of an adaptive delay compensation active rectifier according to the present invention
FIG. 5 is a detailed diagram of the logic control circuit of the adaptive delay compensating active rectifier according to the present invention
Detailed Description
Referring to fig. 1 to 5, the rectifier circuit includes an active rectifier main circuit 1, a sampling circuit 2, an offset voltage generating circuit 3, and a logic control circuit 4. The active rectifier circuit comprises an active rectifier main circuit, a sampling circuit, an offset voltage generating circuit and a logic control circuitAnd (4) a way. NMOS power tube M generated by main circuit of active rectifierN1Of the gate control signal VGN1Sampling circuit to NMOS power tube MN1Voltage V at the drain terminalac1Sampling is carried out, and a sampling signal is input to the input end of the offset voltage generating circuit. Offset voltage generating circuit generates voltage Voffset1And Voffset2The maladjustment of a comparator in the main circuit of the active rectifier is adjusted to ensure that the NMOS power tube MN1At its drain terminal voltage Vac1And off or on at 0.
Output V of active rectifier main circuit 1ac1An output V of the active rectifier main circuit 1 is connected with the input of the sampling circuit 2 and the input of the offset voltage generating circuit 3GN1Is connected with the input of the logic control circuit 4; output V of sampling circuit 2off_sampIs connected with the input of the offset voltage generating circuit 3; output V of offset voltage generating circuit 3offset1And an output Voffset2Is connected with the input of the active rectifier main circuit 1; output S of logic control circuit 4off_sampAnd output SholdAn output S of the logic control circuit 4 connected to the input of the sampling circuit 2offAnd output SonAn output S of the logic control circuit 4 connected to an input of the offset voltage generating circuit 3blockConnected to the input of the active rectifier main circuit 1. The active rectifier main circuit 1 generates an NMOS power tube M in the rectification processN1Of the gate control signal VGN1And NMOS power tube M is caused by the turn-off delay of the active diodeN1Of the gate control signal VGN1At MN1Voltage V at drain terminalac1And is flipped by Δ V above ground potential, thus generating a positive phase voltage. Sampling circuit 2 sampling NMOS power tube MN1Voltage V at drain terminalac1And fed back to the input end of the offset voltage generating circuit 3. Offset voltage generating circuit 3 generates voltage Voffset1And Voffset2The maladjustment of the comparator CMP1 in the main circuit 1 of the active rectifier is adjusted to make the NMOS power tube MN1Of the gate control signal VGN1At node voltage Vac1And when the potential is equal to the ground potential, the time is reversed, so that the purpose of compensating the time delay is achieved. NMOS power tube MN1The gate control signal VGN1 is input to the logic control circuit 4,generating switch control signals in other circuits.
The active rectifier main circuit 1 is composed of an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparator CMP1-CMP2, AC power supply VacCapacitor COAnd a load resistance RLAnd (4) forming. AC power supply VacOne end V ofac1Connecting NMOS power tube MN1And PMOS power tube MP1At the drain end and at the other end Vac2Connecting NMOS power tube MN2And PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1And NMOS power tube MN2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube MP1And PMOS power tube MP2Source terminal of is commonly connected with VoutTerminal PMOS power tube MP1The grid end of the PMOS power tube M is connected withP2Drain terminal of (PMOS) power tube MP2The grid end of the PMOS power tube M is connected withP1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit 3offset1A positive input of the comparator CMP1 and an output V of the offset voltage generating circuit 3offset2Connected to the output V of the comparator CMP1GN1And NMOS power tube MN1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply VacOne end V ofac2The non-inverting input of the comparator CMP2 is connected to power ground, the output V of the comparator CMP2GN2And NMOS power tube MN2The grid ends are connected; load capacitance COAnd a load resistance RLOne end is connected with VoutAnd one end and the other end are connected with a power ground.
The sampling circuit 2 is composed of a capacitor Coff1-Coff2And switches S1-S2. One end of switch S2 and output V of active rectifier main circuit 1ac1Connected with the other end of the capacitor Coff2Is connected to one terminal of a switch S1, a capacitor Coff2The other end of which is connected to ground. The other end of the switch S1 and the capacitor Coff1Is connected to one terminal of a capacitor Coff1The other end of which is connected to ground.
The offset voltage generating circuit 3 is composed of a transconductance amplifier and a superposition circuit. Transconductance amplifier inputThe positive phase input end and the output V of the sampling circuit 2off_sampAnd the input inverting terminal of the transconductance amplifier is connected with the ground. Transconductance amplifier output Vo1And an output Vo2Connected to the superposition circuit input. Simultaneous superposition circuit input and logic control circuit 4 output SonAnd output SoffAre connected.
The logic control circuit 4 is composed of an R-S latch L1, an inverter INV1-INV5, a two-input OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1. The input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the Q output end of the R-S latch L1 is connected with the input end of the inverter INV1 and the input end of the delay unit DEL 1. The output of inverter INV1 is connected to the input of inverter INV 2. Inverter INV3 input and active rectifier main circuit 1 output VGN1Connecting; the output is connected to the input of inverter INV 4. The output of the inverter INV4 is connected to one input of the two-input OR gate OR 1. The inverter INV5 has its input connected to the two-input OR gate OR1 output. The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit 1GN1Are connected. The input of the rising edge detection circuit RED1 and the output V of the active rectifier main circuit 1GN1Are connected. The falling edge detection circuit FED1 has an input coupled to the delay element DEL 1.
Reference is made to fig. 2-4. When AC source VacOne end Vac1Above 0, the comparator CMP1 output is low, VGN10, NMOS power tube MN1Turn off, simultaneously Soff_samp=0,Soff=1,SonWhen the output voltage V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is equal to 0, the switch S2, the switch S4, and the switch S5 are turned off, the switch S3 and the switch S6 are turned on, and the output voltage V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is set to zeroo1And Vo2Is connected to node a and node B. Capacitor C due to turn-off delay of comparator CMP1off2Sampling positive phase voltage, i.e. Vac1_off. When S isholdWhen the value is 1, the switch S1 is turned on, and the capacitor C is turned onoff2Charge on is shared to the capacitor Coff1To generate a sampling voltage Voff_sampAnd the input is input to the positive end of the input of the transconductance amplifier. Two-way output V of transconductance amplifiero1And Vo2Is clamped by a node A and a node B of a second-stage superposition circuit to output Vo1And Vo2Injected as currents into node a and node B, respectively. Offset generation circuit 3 output Voffset1And Voffset2Are respectively as
Voffset1=Vac1+gm1,2Voff_samp(R3A+R4A) (1)
Voffset2=0+gm1,2Voff_sampR4B(2)
As shown in formula (1) and formula (2), due to R3A=R3B,R4A=R4B,Voffset1Equivalent to an alternating current source VacOne terminal voltage Vac1Source follower signal and transconductance amplifier output Vo1Overlap of (V)offset2The source equivalent to ground follows the signal. Thus, according to equations (1) and (2), V is measured when zero-voltage switching is performedoffset2Ratio Voffset1High gm1,2Voff_sampR3BIt is equivalent to increase the positive phase offset voltage at the inverting terminal of the comparator, thereby compensating the conduction delay through feedback.
When AC source VacOne end Vac1Below 0, the comparator CMP1 output is high, V GN11, NMOS power transistor MN1Conducting while Soff_samp=1,Soff=0,SonWhen the output V of the first stage transconductance amplifier of the offset voltage generating circuit 3 is equal to 1, the switch S2, the switch S4, and the switch S5 are turned on, the switch S3, and the switch S6 are turned offo1And Vo2Connected to node C and node D. Capacitor C due to turn-off delay of comparator CMP1off2Sampling positive phase voltage, i.e. Vac1_off. When S isholdWhen the value is 1, the switch S1 is turned on, and the capacitor C is turned onoff2Charge on is shared to the capacitor Coff1To generate a sampling voltage Voff_sampAnd the input is input to the positive end of the input of the transconductance amplifier. Two-way output V of transconductance amplifiero1And Vo2Is equal and clamped by a node C and a node D of a second-stage superposition circuit to output Vo1And Vo2Injecting into nodes C and C, respectively, in the form of currentsAnd D, a node D. Offset generation circuit 3 output Voffset1And Voffset2Are respectively as
Voffset1=Vac1+gm1,2Voff_sampR4A(3)
Voffset2=0+gm1,2Voff_samp(R3B+R4B) (4)
As shown in formula (3) and formula (4), due to R3A=R3B,R4A=R4B,Voffset1Equivalent to an alternating current source VacOne terminal voltage Vac1Source follow signal of, Voffset2Ground-equivalent source-follower signal and transconductance amplifier output Vo1And (3) superposition. According to the expressions (3) and (4), when zero-voltage switching is performed, Voffset1Ratio Voffset2High gm1,2Voff_sampR3BIt is equivalent to add an inverting offset voltage at the inverting terminal of the comparator, thereby compensating the turn-off delay. Therefore, by the switching circuit, the on and off delays can be compensated at the same time in the same cycle.
The self-adaptive delay compensation active rectifier offset voltage generating circuit of the invention provides the following specific embodiments:
the offset voltage generating circuit 3 is composed of a MOS transistor M1-M17Resistance R1-R2Resistance R3A-R3BResistance R4A-R4BCapacitor C1-C2And switches S3-S6. PMOS tube M1And PMOS transistor M2Form a differential pair structure, a PMOS transistor M1The grid end of the NMOS tube M is connected with the ground, the drain end of the NMOS tube M is connected with the drain end of the NMOS tube3The drain ends of the two are connected. PMOS tube M2And the output V of the sampling circuit 2off_sampConnected with drain terminal of NMOS transistor M5The drain ends of the two are connected. PMOS tube M1Source terminal and PMOS tube M2Source end of the PMOS transistor M is connected in parallel7The drain terminal of (1). NMOS tube M3NMOS transistor M4The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the transformer is connected with the ground. NMOS tube M5NMOS transistor M11NMOS transistor M12The gate terminals of which are connected to form a current mirror structure(ii) a The source end of the transformer is connected with the ground. PMOS tube M6PMOS transistor M7The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M7The drain terminal is a PMOS tube M1And PMOS transistor M2The resulting differential pair structure provides a tail current. PMOS tube M8Drain terminal and NMOS tube M4The drain ends of the two are connected. PMOS tube M8PMOS transistor M9PMOS transistor M10The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M13PMOS transistor M14PMOS transistor M15The grid ends of the two electrodes are connected to form a current mirror structure; the source end of the power supply is connected with the power supply. PMOS tube M16And PMOS transistor M17Is a source follower structure. NMOS tube M16Output V of main circuit 1 of gate terminal and active rectifierac1Connected with the source end and the resistor R4AAre connected. NMOS tube M17The grid terminal is connected with the ground, the source terminal is connected with the resistor R4BAre connected. NMOS tube M16NMOS transistor M17And the source end is connected with the ground. Resistance R1One terminal and output V of transconductance amplifiero1Connected with the other end of the capacitor C1Serially connected to ground, a frequency compensation branch is formed. Resistance R2One terminal and output V of transconductance amplifiero2Connected with the other end of the capacitor C2Serially connected to ground, a frequency compensation branch is formed. The switches S3-S6 are MOS switching devices, and the switches S3 and S6 have their gate terminals connected in parallel with the signal Soff(ii) a A switch S4, a switch S5, a grid end connected with the signal Son. A switch S3 and a switch S5, one end of which is connected in parallel with the output V of the transconductance amplifiero1And the other end is connected with a resistor R3AThe nodes A and C at two ends are connected; a switch S4 and a switch S6, one end of which is connected in parallel with the output V of the transconductance amplifiero2And the other end is connected with a resistor R3BNode B and node D are connected at both ends, and output V of the node A-D clamped transconductance amplifiero1And an output Vo2. PMOS tube M16-M17Resistance R3A-R3BAnd the switches S3-S6 form a superposed circuit for alternately compensating the turn-on delay and the turn-off delay of the active rectifier.
Claims (3)
1. A self-adaptive time delay compensation active rectifier circuit is characterized by comprising an active rectifier main circuit (1), a sampling circuit (2), an offset voltage generating circuit (3) and a logic control circuit (4), wherein the active rectifier main circuit (1) generates a power tube drain end voltage Vac1 in a rectifying process, inputs the power tube drain end voltage Vac1 into the sampling circuit (2) and the offset voltage generating circuit (3), and inputs the offset voltage generating circuit (3) after being processed by the sampling circuit (2) through sampling Vac 1; amplified by an offset voltage generating circuit (3) and connected with the drain end voltage V of the power tubeac1After the superposition processing, the offset voltage is transmitted into an active rectifier main circuit (1) to feed back and adjust a comparator, so that delay compensation is completed; meanwhile, the main circuit (1) of the active rectifier generates a power tube grid end control signal VGN1The voltage is input into a logic control circuit (4), and is respectively input into an active rectifier main circuit (1), a sampling circuit (2) and an offset voltage generating circuit (3) after being processed by the logic control circuit (4), so that logic control is realized; the active rectifier main circuit (1) comprises an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparator CMP1-CMP2, AC power supply VacCapacitor COAnd a load resistance RL(ii) a AC power supply VacOne end V ofac1Connecting NMOS power tube MN1And PMOS power tube MP1At the drain end and at the other end Vac2Connecting NMOS power tube MN2And PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1And NMOS power tube MN2The source ends of the power amplifiers are connected to the power ground in common; PMOS power tube MP1And PMOS power tube MP2Source terminal of is commonly connected with VoutTerminal PMOS power tube MP1The grid end of the PMOS power tube M is connected withP2Drain terminal of (PMOS) power tube MP2The grid end of the PMOS power tube M is connected withP1The drain terminal of (1); inverting input of comparator CMP1 and output V of offset voltage generating circuit (3)offset1Connected to the positive input of the comparator CMP1 and the output V of the offset voltage generating circuit (3)offset2Connected to the output V of the comparator CMP1GN1And NMOS power tube MN1The grid ends are connected; the inverting input of the comparator CMP2 is connected to the AC supply VacOne end V ofac2Comparator CMP2 with its non-inverting input connected to power ground, output V of comparator CMP2GN2And NMOS power tube MN2The grid ends are connected; load capacitance COAnd a load resistance RLOne end is connected with VoutThe other end is connected with a power ground; the offset voltage generating circuit (3) comprises a transconductance amplifier and a superposition circuit; the input positive phase end of the transconductance amplifier and the output V of the sampling circuit (2)off_sampThe input inverting end of the transconductance amplifier is connected with the ground; transconductance amplifier output Vo1And an output Vo2Is connected with the input of the superposition circuit; simultaneous superposition circuit input and logic control circuit (4) output SonAnd output SoffAre connected.
2. An adaptive delay-compensated active rectifier circuit as claimed in claim 1, characterized in that the sampling circuit (2) comprises a capacitor Coff1-Coff2And switches S1-S2, one end of the switch S2 and the output V of the active rectifier main circuit 1ac1Connected with the other end of the capacitor Coff2Is connected to one terminal of a switch S1, a capacitor Coff2The other end of the connecting rod is connected with the ground; capacitor Coff1As an output port of the sampling circuit 2, and is connected to the other end of the switch S1, and a capacitor Coff1The other end of the connecting rod is connected with the ground; the output voff-samp of the sampling circuit 2 is connected to an input of the offset voltage generating circuit 3.
3. An adaptive delay compensating active rectifier circuit as claimed in claim 1, wherein the logic control circuit (4) comprises an R-S latch L1, an inverter INV1-INV5, a two-input OR gate OR1, a rising edge detection circuit RED1, a falling edge detection circuit FED1 and a delay unit DEL 1; the input S end of the R-S latch L1 is connected with the output of a rising edge detection circuit RED 1; the input end R of the R-S latch L1 is connected with the output end of a falling edge detection circuit FED 1; the output Q end of the R-S latch L1 is connected with the input of an inverter INV1 and the input of a delay unit DEL 1; the output of the inverter INV1 is connected with the input of the inverter INV 2; inverter INV3 input and active rectifier main circuit 1 output VGN1Connecting; inverter INV3 output and inverterINV4 input connection; the output of the inverter INV4 is connected with the input of one end of a two-input OR gate 1; the input of the inverter INV5 is connected with the output of a two-input OR gate 1; deriving S from the output of a two-input OR gate 1offSignal, S is obtained from the output terminal of inverter INV5onSignal;The other end of the two-input OR gate OR1 is connected with the output V of the active rectifier main circuit (1)GN1Connecting; the input of the rising edge detection circuit RED1 is connected with the delay unit DEL 1; the input of the falling edge detection circuit FED1 and the output V of the active rectifier main circuit (1)GN1Are connected.
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CN110161432A (en) * | 2019-05-09 | 2019-08-23 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of aviation AC supply voltage Acquisition Circuit |
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CN102969894B (en) * | 2012-11-19 | 2015-04-08 | 西安三馀半导体有限公司 | Mode automatic converting circuit for DC-DC (Direct Current to Direct Current) converter |
KR102120955B1 (en) * | 2013-11-22 | 2020-06-10 | 삼성전자주식회사 | Active rectifier and circuit compensating reverse leakage current with time delay technique for zero reverse leakage current |
WO2017050290A1 (en) * | 2015-09-25 | 2017-03-30 | The Hong Kong University Of Science And Technology | Wireless charging receiver |
CN107124166B (en) * | 2017-05-25 | 2019-07-23 | 西安交通大学 | A kind of low-power consumption high speed Zero Current Switch |
CN107040152B (en) * | 2017-05-25 | 2019-05-03 | 西安交通大学 | Active rectifier based on delay controller |
CN107896062B (en) * | 2017-10-27 | 2019-09-20 | 浙江大学 | A kind of soft switch conversion device based on flyback converter |
CN108512422B (en) * | 2018-05-18 | 2020-09-25 | 西北工业大学 | Fixed on-time controlled step-down DC-DC converter |
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