CN109065629A - A kind of slot grid superjunction devices - Google Patents
A kind of slot grid superjunction devices Download PDFInfo
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- CN109065629A CN109065629A CN201810970740.6A CN201810970740A CN109065629A CN 109065629 A CN109065629 A CN 109065629A CN 201810970740 A CN201810970740 A CN 201810970740A CN 109065629 A CN109065629 A CN 109065629A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 125
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 claims description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000001939 inductive effect Effects 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000024241 parasitism Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
Design power semiconductor technology of the present invention, in particular to a kind of slot grid DMOS device.The present invention is characterized in that: it is based on traditional slot grid super junction device structure, it is introduced in the first conductive type semiconductor column area and uses the first conductive type semiconductor of low energy gap area, and close to lateral leadin broad stopband the first conductive type semiconductor area in the second conductive type semiconductor column area in the first conductive type semiconductor of low energy gap area, pass through above-mentioned measure, avalanche breakdown current path when avalanche breakdown occurs for slot grid superjunction devices can effectively be changed, make avalanche breakdown electric current far from the second conductive type semiconductor body area below heavy doping the first conductive type semiconductor source region, to effectively avoid the unlatching of parasitic BJT, improve reliability (i.e. anti-UIS failure ability) of the slot grid superjunction devices in non-clamp inductive load application.
Description
Technical field
The present invention relates to power semiconductor technologies, in particular to a kind of slot grid superjunction devices.
Background technique
Power MOSFET is excellent because its switching speed is fast, loss is small, input impedance is high, driving power is small, frequency characteristic is good etc.
Point plays an important role in power conversion field.The system performance requirements power MOSFET of continuous improvement is with lower power
While loss, should also have higher reliability under high electric stress.When in system circuit there are when non-clamp inductive load,
The energy being stored in inductance under on state can all be discharged by MOSFET when off, and high voltage and high current will be applied simultaneously
It is added on power MOSFET, easily causes component failure.Therefore, the switching process (Unclamped under non-clamp inductive load
Inductive Switching, UIS) the most extreme electricity that is typically considered power MOSFET and can face in the application answers
Power situation.Therefore the anti-UIS failure ability of device is commonly used for evaluating the reliability of power superjunction, and UIS tolerance is to measure function
The important parameter of the anti-UIS failure ability of rate superjunction.
The unlatching of parasitic BJT (Bipolar Junction Transistor, bipolar junction transistor) is to cause UIS failure
One of the major reasons.The failure of UIS is typically considered device " active " mode, this is because the parasitic BJT between source and drain
Conducting in UIS snowslide, intracorporal high current will be flowed through after conducting so that device is brought rapidly up, and damage device.Power MOSFET
Emitter region of the N+ source region as parasitism BJT, the drift region N- constitutes the collector area of parasitism BJT, and the area P-body is as base area.
When avalanche breakdown occurs for above-mentioned power superjunction devices, avalanche current reaches P+ via the area P-body below N+ source region and contacts
Area, and when avalanche current flows through the base area of parasitic BJT, since area P-body itself will necessarily generate forward voltage drop there are resistance,
When pressure drop is greater than the forward conduction voltage drop of parasitism BJT, the emitter positively biased of parasitic BJT amplifies workspace, amplification into forward direction
Avalanche current causes the heat of device to burn.
VDMOS device with super-junction structure is a kind of important power device occurred in recent years, its basic principle
It is charge balance concept, by introducing the super-junction structure of the P column and N column that are spaced each other in the drift region of common VDMOS, changes significantly
The tradeoff being apt between the conducting resistance and breakdown voltage of common VDMOS, therefore obtained extensively in the field of power device
General use.
Currently, the method for the anti-UIS failure ability to improve superjunction devices is mainly to pass through to reduce parasitism BJT's in the industry
Base resistance inhibits its unlatching.However, this method can not prevent the unlatching of parasitic BJT, it just not can avoid snowslide yet and hit
Wear caused device UIS active failure mode；In addition, by the injection of the boron of high-energy or deep diffusion come can only be certain
Reduce base resistance in limit, can not infinitely reduce the base resistance of parasitic BJT, otherwise will increase the threshold voltage of device.
Summary of the invention
In view of the above-mentioned problems, problem to be solved by this invention is: providing one kind can effectively prevent parasitic BJT to open,
Improve the slot grid superjunction devices of UIS tolerance.
Design of the invention is specific as follows: traditional slot grid super junction device structure is based on, in the first conductive type semiconductor column
It is introduced in area and uses the first conductive type semiconductor of low energy gap area, and close to the in the first conductive type semiconductor of low energy gap area
Lateral leadin broad stopband the first conductive type semiconductor area in two conductive type semiconductor column areas, passes through above-mentioned measure, Neng Gouyou
Effect changes avalanche breakdown current path when avalanche breakdown occurs for slot grid superjunction devices, makes avalanche breakdown electric current far from heavy doping the
The second conductive type semiconductor body area below one conductive type semiconductor source region mentions to effectively avoid the unlatching of parasitic BJT
Reliability (i.e. anti-UIS failure ability) of the high slot grid superjunction devices in non-clamp inductive load application.
For achieving the above object, technical solution of the present invention is as follows:
A kind of slot grid superjunction devices, including metalized drain 1, the first conduction type half being cascading from bottom to up
Conductor substrate 2, drift region, metallizing source 10；The lower surface of the first conductive type semiconductor substrate 2 and metalized drain
1 upper surface contact, the lower surface of the drift region are contacted with the upper surface of the first conductive type semiconductor substrate 2, the drift
The top for moving area has groove profile gate electrode 5, and the side and bottom of the groove profile gate electrode 5 are surrounded by gate oxide 6, the groove profile
The two sides of gate electrode 5 are respectively provided with a second conductive type semiconductor body area 8, the second conductive type semiconductor body area 8
It is isolated with groove profile gate electrode 5 by gate oxide 6, in the second conductive type semiconductor body area 8 there is heavy doping first to lead
Electric type semiconductor source region 7 and the first conductive type semiconductor of heavy doping contact zone 9, the metallizing source 10 is located at heavy doping
The top of first conductive type semiconductor source region 7 is simultaneously in contact, and the both ends of the metallizing source 10 extend down into second
Conductive type semiconductor body area 8 forms groove profile metallizing source structure, first conductive type semiconductor of heavy doping contact zone 9
Positioned at 10 both ends groove profile of metallizing source bottom and be in contact, the middle part of drift region has the second conductive type semiconductor column area
3 and the first conductive type semiconductor column area 4, the second conductive type semiconductor column area 3 be located at groove profile gate electrode 5 just under
Side, the length of of length no more than groove profile gate electrode 5 in the second conductive type semiconductor column area 3, it is characterised in that: described the
There is the first conductive type semiconductor of low energy gap area 41 and the first conduction type of broad stopband half in one conductive type semiconductor column area 4
Conductor region 42, first conductive type semiconductor of broad stopband area 42 are located at the lower surface in the second conductive type semiconductor body area 8
Between the second conductive type semiconductor column area 3, and the length in broad stopband the first conductive type semiconductor area 42 is not less than heavily doped
The length of miscellaneous first conductive type semiconductor source region 7, a side and bottom surface in broad stopband the first conductive type semiconductor area 42
It is contacted with the first conductive type semiconductor of low energy gap area 41.
Further, first conductive type semiconductor of low energy gap area 41 and broad stopband the first conductive type semiconductor area
42 doping concentrations having the same；
Further, the forbidden bandwidth Eg1 in first conductive type semiconductor of low energy gap area 41 is less than broad stopband first
The forbidden bandwidth Eg2 in conductive type semiconductor area 42；
Further, the material that first conductive type semiconductor of low energy gap area 41 uses is indium arsenide or gallium antimonide etc.
Low-gap semiconductor material, the material that first conductive type semiconductor of broad stopband area 42 uses is gallium nitride or silicon carbide etc.
Semiconductor material with wide forbidden band；
Further, the first conduction type is N-type, and the second conduction type is p-type；Or first conduction type be p-type, the
Two conduction types are N-type.
Compared with prior art, the beneficial effects of the present invention are: slot grid superjunction devices provided by the invention can be effectively prevent
The unlatching of parasitic BJT improves the UIS tolerance of slot grid superjunction devices.
Detailed description of the invention
Fig. 1 is the schematic diagram of regular troughs grid super junction device structure and its avalanche breakdown current path；
Fig. 2 is a kind of slot grid super junction device structure schematic diagram that present example 1 provides；
Fig. 3 is a kind of schematic diagram of the avalanche breakdown current path for slot grid super junction device structure that present example 1 provides；
Fig. 4 is a kind of slot grid super junction device structure schematic diagram that present example 2 provides；
Wherein, 1 is metalized drain, and 2 be the first conductive type semiconductor substrate, and 3 float for the first conductive type semiconductor
Area is moved, 4 be the first conductive type semiconductor column area, and 41 be the first conductive type semiconductor of low energy gap area, and 42 be broad stopband first
Conductive type semiconductor area, 5 be groove profile gate electrode, and 6 be gate oxide, and 7 be the first conductive type semiconductor of heavy doping source region, 8
It is the first conductive type semiconductor of heavy doping contact zone for the second conductive type semiconductor body area, 9,10 be metallizing source.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
A kind of slot grid superjunction devices, as shown in Fig. 2, including the metalized drain 1, first being cascading from bottom to up
Conductive type semiconductor substrate 2, drift region, metallizing source 10；The lower surface of the first conductive type semiconductor substrate 2 with
The upper surface of metalized drain 1 contacts, and the lower surface of the drift region and the upper surface of the first conductive type semiconductor substrate 2 connect
The top of touching, the drift region has groove profile gate electrode 5, and the side and bottom of the groove profile gate electrode 5 are wrapped by gate oxide 6
It encloses, the two sides of the groove profile gate electrode 5 are respectively provided with a second conductive type semiconductor body area 8, second conduction type
Semiconductor body 8 is isolated with groove profile gate electrode 5 by gate oxide 6, has weight in the second conductive type semiconductor body area 8
Adulterate the first conductive type semiconductor source region 7 and the first conductive type semiconductor of heavy doping contact zone 9, the metallizing source 10
Positioned at the first conductive type semiconductor of heavy doping source region 7 top and be in contact, the both ends of the metallizing source 10 are to downward
It extends into the second conductive type semiconductor body area 8 and forms groove profile metallizing source structure, first conduction type of heavy doping half
Conductor contact zone 9 is located at the bottom of 10 both ends groove profile of metallizing source and is in contact, and the middle part of drift region has the second conductive-type
Type semiconductor column area 3 and the first conductive type semiconductor column area 4, the second conductive type semiconductor column area 3 are located at groove profile grid
The underface of electrode 5, the length of of length no more than groove profile gate electrode 5 in the second conductive type semiconductor column area 3, feature
It is: there is the first conductive type semiconductor of low energy gap area 41 and broad stopband the in the first conductive type semiconductor column area 4
One conductive type semiconductor area 42, first conductive type semiconductor of broad stopband area 42 are located at the second conductive type semiconductor body
Between the lower surface in area 8 and the second conductive type semiconductor column area 3, and the length in broad stopband the first conductive type semiconductor area 42
Not less than the length of the first conductive type semiconductor of heavy doping source region 7, one of broad stopband the first conductive type semiconductor area 42
Side is contacted with bottom surface and the first conductive type semiconductor of low energy gap area 41.
The working principle of the invention is specifically described below with reference to the embodiment of the present invention 1.
Under forward conduction mode, the electrode connection mode of device in embodiment 1 are as follows: metallizing source 10 connects low potential, gold
Categoryization drain electrode 1 connects high potential, and groove profile gate electrode 5 connects high potential.When the positive bias-voltage for being applied to groove profile gate electrode 5 reaches threshold value electricity
When pressure, inversion channel is formed close to the side wall of groove profile gate electrode 5 in the second conductive type semiconductor body area 8, how sub- electronics is from again
The first conductive type semiconductor source region 7 is adulterated to lead via the inversion channel injection first in the second conductive type semiconductor body area 8
In electric type semiconductor drift region 3, forward conduction electric current is formed；
Under reverse blocking mode, the electrode connection mode of device in embodiment 1 are as follows: metallizing source 10 connects low potential, gold
Categoryization drain electrode 1 connects high potential, and groove profile gate electrode 5 connects low potential, the current potential in the second conductive type semiconductor body area 8 and metallization source
The current potential of pole 10 is identical.When device is in blocking state, the PN junction in the second conductive type semiconductor body area 8 and drift region formation
It exhausts, reverse withstand voltage is mainly undertaken by drift region.
The slot grid superjunction devices that the present embodiment 1 provides, during UIS, due in the first conductive type semiconductor column area
Middle introduce uses the first conductive type semiconductor of low energy gap area, and close to second in the first conductive type semiconductor of low energy gap area
Lateral leadin broad stopband the first conductive type semiconductor area in conductive type semiconductor column area, by above-mentioned measure, if device
Avalanche breakdown occurs, can effectively change avalanche breakdown current path when avalanche breakdown occurs for slot grid superjunction devices, make snowslide
Breakdown current avoids broad stopband the first conductive type semiconductor area, flows into and metallizes from low energy gap the first conductive type semiconductor area
Source electrode, far from the second conductive type semiconductor body area below the first conductive type semiconductor source region, as shown in figure 3, therefore shutting out
The unlatching of parasitic BJT absolutely, improves the anti-UIS failure ability of device.
Embodiment 2
As shown in figure 4, the structure of this example is on the basis of embodiment 1, to be provided with three kind of first conductive type semiconductor
Body area, wherein the forbidden bandwidth in the first conductive type semiconductor body area 43 is greater than the taboo in the first conductive type semiconductor body area 42
Bandwidth, the forbidden band that the forbidden bandwidth in the first conductive type semiconductor body area 43 is greater than the first conductive type semiconductor body area 41 are wide
Degree, the working principle of this example are same as Example 1, thus it is possible to vary the path of avalanche current promotes the UIS tolerance of device.
Claims (5)
1. a kind of slot grid superjunction devices, including metalized drain (1), the first conduction type half being cascading from bottom to up
Conductor substrate (2), drift region, metallizing source (10)；The top of the drift region has groove profile gate electrode (5), the groove profile
The side and bottom of gate electrode (5) are surrounded by gate oxide (6), and the two sides of the groove profile gate electrode (5) are respectively provided with one the
Two conductive type semiconductor body areas (8), the second conductive type semiconductor body area (8) and groove profile gate electrode (5) pass through grid oxygen
Change layer (6) isolation, there is the first conductive type semiconductor of heavy doping source region in the second conductive type semiconductor body area (8)
, and the first conductive type semiconductor source region (7) and gate oxide (7) and the first conductive type semiconductor of heavy doping contact zone (9)
(6) it contacts；The both ends of the metallizing source (10) extend down into the second conductive type semiconductor body area (8) and form groove profile
Metallizing source structure, first conductive type semiconductor of heavy doping contact zone (9) are located at (10) two end slot of metallizing source
The bottom of type is simultaneously in contact；There is the second conductive type semiconductor column area (3) and the first conduction type partly to lead at the middle part of drift region
Scapus area (4), the first conductive type semiconductor column area (4) are located at the two sides in the second conductive type semiconductor column area (3), and described
Second conductive type semiconductor column area (3) is located at the underface of groove profile gate electrode (5), the second conductive type semiconductor column area
(3) transverse width is no more than the transverse width of groove profile gate electrode (5), it is characterised in that: first conductive type semiconductor
There is the first conductive type semiconductor of low energy gap area (41) and broad stopband the first conductive type semiconductor area (42) in column area (4),
First conductive type semiconductor of broad stopband area (42) is located at the lower surface and second in the second conductive type semiconductor body area (8)
Between conductive type semiconductor column area (3), and the transverse width in broad stopband the first conductive type semiconductor area (42) is not less than weight
Adulterate the transverse width of the first conductive type semiconductor source region (7), one of broad stopband the first conductive type semiconductor area (42)
Side is contacted with bottom surface and the first conductive type semiconductor of low energy gap area (41).
2. a kind of slot grid superjunction devices according to claim 1, it is characterised in that: first conduction type of low energy gap half
Conductor region (41) and broad stopband the first conductive type semiconductor area (42) doping concentration having the same.
3. a kind of slot grid superjunction devices according to claim 1, it is characterised in that: first conduction type of low energy gap half
The forbidden bandwidth Eg1 of conductor region (41) is less than the forbidden bandwidth Eg2 in the first conductive type semiconductor of broad stopband area (42).
4. a kind of slot grid superjunction devices according to claim 1, it is characterised in that: first conduction type of low energy gap half
The material that conductor region (41) uses for indium arsenide or gallium antimonide, first conductive type semiconductor of broad stopband area (42) use
Material is gallium nitride or silicon carbide.
5. a kind of slot grid superjunction devices according to claim 1, it is characterised in that: the first conduction type is N-type, and second leads
Electric type is p-type；Or first conduction type be p-type, the second conduction type be N-type.
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| CN201810970740.6A CN109065629B (en) | 2018-08-24 | 2018-08-24 | Trench gate surpasses knot device |
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| CN201810970740.6A CN109065629B (en) | 2018-08-24 | 2018-08-24 | Trench gate surpasses knot device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112802903A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Groove gate VDMOS device with improved gate structure |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802903A (en) * | 2021-04-15 | 2021-05-14 | 成都蓉矽半导体有限公司 | Groove gate VDMOS device with improved gate structure |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
| CN113224164B (en) * | 2021-04-21 | 2022-03-29 | 电子科技大学 | Super junction MOS device |
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| CN109065629B (en) | 2021-02-23 |
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