CN109065510B - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
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- CN109065510B CN109065510B CN201810915010.6A CN201810915010A CN109065510B CN 109065510 B CN109065510 B CN 109065510B CN 201810915010 A CN201810915010 A CN 201810915010A CN 109065510 B CN109065510 B CN 109065510B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
Abstract
The invention provides a chip packaging structure which comprises a substrate, wherein step surfaces are respectively formed on two sides of the upper surface of the substrate, the chip packaging structure comprises an epitaxial layer formed on the upper surface of the substrate, a waterproof layer filled on the upper surface and the step surfaces, a first metal layer formed on the back surface and the side surface of the substrate, which are not covered by the waterproof layer and the epitaxial layer, and a second metal layer formed on the first metal layer. In addition, the invention also relates to a preparation method of the chip packaging structure. The chip packaging structure and the preparation method thereof have better thermal stability and lower resistance.
Description
Technical Field
The invention relates to a power semiconductor chip packaging technology, in particular to a chip packaging structure and a preparation method thereof.
Background
With the wide application of semiconductor technology in industrial production automation, computer technology and communication technology and the increasing complexity of electronic equipment, the reliability requirement of power devices is higher and higher. Microelectronic packaging is the protection of microelectronic chips or components, providing energy and cooling, and electrically, thermally, and mechanically connecting the microelectronic components to the external environment.
For power devices, their packaging has its particularity: firstly, the package body needs to have good heat dissipation capability, and good thermal stability of the device package body needs to be ensured, which is a core problem in power device packaging; secondly, the size of a chip of the power device is generally large, and the stress during welding and the thermal stress generated during use must be considered; thirdly, with the development of power MOS field effect transistors, the resistance of wire bonding and the package of the case thereof is comparable to the internal resistance of the chip, and it becomes very important to improve the external resistance of the package.
Since a large number of new power devices are applied to portable electronic products, power device packages are also developed in the directions of miniaturization, high integration, and the like, and thus, requirements for good heat dissipation and resistance reduction are required for packaging technologies.
Disclosure of Invention
The invention aims to provide a packaging structure with better thermal stability and lower resistance and a preparation method thereof.
In order to solve the technical problems, the invention adopts the following technical scheme: a chip packaging structure comprises a substrate, step surfaces are formed on two sides of the upper surface of the substrate respectively, the chip packaging structure comprises an epitaxial layer formed on the upper surface of the substrate, a waterproof layer filled on the upper surface and the step surfaces, a first metal layer formed on the back and the side surface of the substrate, which is not covered by the waterproof layer and the epitaxial layer, and a second metal layer formed on the first metal layer.
According to the design concept of the invention, the chip packaging structure further comprises a passivation layer formed on the upper surface of the waterproof layer and the upper surface of the epitaxial layer, and the passivation layer is a silicon oxide protection layer.
According to the design concept of the invention, the filling material used for the waterproof layer is polyimide.
According to the design concept of the invention, the first metal layer is a metal silicide layer.
According to the design concept of the invention, the metal silicide layer is formed by reacting metal titanium, tungsten, nickel and aluminum with the substrate.
According to the design concept of the invention, the second metal layer is an electroplated metal layer.
In addition, the invention claims a preparation method of the packaging structure, which comprises the following steps:
(1) providing a wafer, wherein the wafer comprises a plurality of chips and scribing channels positioned among the chips, and the chips comprise substrates and epitaxial layers formed on the substrates;
(2) a first groove extending to the substrate is formed in the scribing way, a second groove is formed in the epitaxial layer, the width of the second groove is larger than that of the first groove, and the first groove and the second groove are communicated to form a scribing groove;
(3) forming a waterproof layer in the epitaxial layer and the scribing groove;
(4) removing the waterproof layer which is arranged on the epitaxial layer and protrudes out of the upper surface of the epitaxial layer above the scribing groove, and preparing a passivation layer at the position where the waterproof layer is removed;
(5) scribing the scribing groove, and dividing the chip;
(6) preparing a first metal layer on the periphery of the divided chip, covering the whole chip, heating to a certain temperature, keeping for enough time, slowly cooling to enable the metal to react with the contact part of the substrate to generate a metal silicide layer, and removing unreacted metal on the surfaces of the passivation layer and the waterproof layer;
(7) and preparing a metal layer on the metal silicide layer.
According to the design concept of the present invention, the trench in step (2) of the present invention is etched by using a dry method.
According to the design concept of the present invention, the sidewalls of the scribe line in step (2) of the present invention may be repaired using a sacrificial oxidation method, which includes the steps of:
placing the etched chip into a high-temperature furnace tube, raising the temperature, then introducing oxygen, and forming a silicon dioxide oxide layer on the side wall of the scribing groove;
and removing the silicon dioxide oxide layer by using silicon oxide etching liquid.
According to the design concept of the present invention, the metal layer in the step (7) of the present invention is an electroplated metal layer, and is gold, copper, aluminum, silver, titanium or an alloy.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a cross-sectional view of a package structure of the present invention;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a package structure according to an embodiment of the invention;
fig. 3 to fig. 11 are schematic cross-sectional views illustrating a process of forming a package structure according to an embodiment of the invention;
in the figure:
10. a substrate; 20. an epitaxial layer; 30. a polyimide layer; 40. passivating the protective layer; 50. a first metal layer; 60. a second metal layer.
Detailed Description
In order to make the objects, technical solutions and advantageous technical effects of the present invention more clearly and completely apparent, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention will be further described with reference to the accompanying drawings and the detailed description below:
as shown in fig. 1, the chip package structure includes a substrate 10, stepped surfaces are respectively formed on two sides of an upper surface of the substrate 10, and the chip package structure includes an epitaxial layer 20 formed on the upper surface of the substrate 10, a water-repellent layer 30 filled on the upper surface and the stepped surfaces, a first metal layer 50 formed on a back surface and a side surface of the substrate 10 not covered by the water-repellent layer 30 and the epitaxial layer 20, and a second metal layer 60 formed on the first metal layer 50. In addition, the invention also relates to a preparation method of the chip packaging structure. The chip packaging structure and the preparation method thereof have better thermal stability and lower resistance.
Preferably, the chip packaging structure further includes a passivation layer formed on the upper surface of the waterproof layer and the upper surface of the epitaxial layer, and the passivation layer is a silicon oxide protection layer.
Preferably, the filling material used for the waterproof layer 30 of the present invention is polyimide.
Preferably, the first metal layer 50 of the present invention is a metal silicide layer.
Preferably, the metal silicide layer of the invention is formed by reacting metal titanium, tungsten, nickel and aluminum with the substrate.
Preferably, the second metal layer 60 of the present invention is an electroplated metal layer.
As described above, the substrate 10 of the present invention serves as the physical foundation for the chip, as well as the support and electrodes; because the substrate 10 is of a convex structure, the heat dissipation area of the substrate 10 is increased, the protective layer 30 can reduce mechanical stress, protect the chip and improve the reliability of the chip; the first metal layer 50 is formed on the back and side of the substrate 10 not covered by the epitaxial layer 20 and the waterproof layer 40, so that the impurity concentration of the surface layer of the substrate 10 is increased, the ohmic contact resistance between the substrate 10 and the back metal is reduced, the second metal layer 60 is electroplated on the first metal layer 50, the metal covering area is increased, the heat dissipation can be improved while the contact resistance is reduced, and the performance and reliability of the packaging structure are greatly improved.
As shown in fig. 2 to 11, the present invention provides a method for manufacturing a package structure, comprising the following steps:
step S1: providing a wafer, wherein the wafer comprises a plurality of chips and scribing streets among the chips, and the chips comprise a substrate 10 and an epitaxial layer 20 formed on the substrate 10;
step S2: forming a first trench extending to the substrate 10 on the scribe line, forming a second trench on the epitaxial layer 20, wherein the width of the second trench is greater than that of the first trench, and the first trench and the second trench are communicated to form a scribe line;
step S3: forming a waterproof layer 30 in the epitaxial layer 20 and the scribing groove;
step S4: removing the waterproof layer 30 which is arranged on the epitaxial layer 20 and protrudes out of the upper surface of the epitaxial layer 20 above the scribing groove, and preparing a passivation layer at the position where the waterproof layer 30 is removed;
step S5: scribing the scribing groove, and dividing the chip;
step S6: preparing a first metal layer 50 on the periphery of the divided chip, covering the whole chip, heating to a certain temperature, keeping for a sufficient time, slowly cooling to enable the metal to react with the contact part of the substrate 10 to generate the first metal layer 50, and removing the unreacted metal on the surfaces of the passivation layer 40 and the waterproof layer 30;
step S7: a second metal layer 60 is prepared on the first metal layer 50.
In detail, in step S1, the substrate 10 is provided, and the epitaxial layer 20 is formed on the surface of the substrate 10, wherein the epitaxial layer 20 can be prepared by using vapor phase epitaxy, molecular beam epitaxy and liquid phase epitaxy.
The substrate 10 and the epitaxial layer 20 form a wafer, and in the present invention, several hundreds to thousands of chips are usually connected together on one wafer, and a gap of 80um to 150um is left between them, which is called a scribe region.
In step S2, trenches are etched on the substrate 10 and the epitaxial layer 20 in two steps to form a first trench and a second trench, respectively, and the first trench and the second trench are communicated with each other to form a scribe line of the package structure, as shown in fig. 4, the bottom of the first trench is in the substrate 10, as shown in fig. 5, the bottom of the second trench is at the bottom of the epitaxial layer 20, and the width of the second trench is greater than the width of the first trench.
The first trench and the second trench in the present invention can be etched by dry etching technique, and the plasma generated in the gas is used to etch away the unwanted surface material on the substrate 10 and the epitaxial layer 20 through the physical and chemical reaction between the mask layer window opened by photolithography and the substrate 10 and the epitaxial layer 20 exposed to the plasma. Meanwhile, the electric field can be used for guiding and accelerating the plasma, so that the plasma has certain energy, when the plasma bombards the surfaces of the substrate 10 and the epitaxial layer 20, the atomic foundation of the materials of the substrate 10 and the epitaxial layer 20 can be damaged, and the etching precision and efficiency can be improved. Specifically, a photoresist is laid on the epitaxial layer 20, the photoresist is used as a mask, deep trench etching is carried out on the epitaxial layer 20 and the substrate 10, and then all the photoresist is removed to form a first trench; and spreading photoresist on the substrate 10 and the epitaxial layer 20, etching the trenches of the epitaxial layer 20 and the substrate 10 by taking the photoresist as a mask, and removing all the photoresist to form a second trench.
In detail, the dry etching may damage the surfaces of the first trench and the second trench to some extent, but repair them. The method adopts a sacrificial oxidation method to repair the damage, the whole chip is placed in a high-temperature furnace tube, the temperature is raised, then oxygen is introduced, silicon crystals on the surfaces of the first groove and the second groove react with the oxygen at high temperature to form a silicon oxide layer, then silicon oxide etching liquid is used for removing the silicon oxide layer, the damage can be repaired, the top and the bottom of the repaired groove are smooth in appearance, and the quality and the uniformity of a subsequent grid oxide layer can be guaranteed.
In step S3, as shown in fig. 6, preferably, the dicing groove is filled with polyimide, and the filled chip package structure has high temperature resistance, low temperature resistance, corrosion resistance, self-lubrication, low wear, excellent mechanical properties, good dimensional stability, small thermal expansion coefficient, low thermal conductivity, no rusting, and can effectively retard electromigration, increase the mechanical properties of the device, and also effectively increase the moisture resistance of the device.
In step S4, as shown in fig. 7, the waterproof layer 30 protruding from the epitaxial layer 20 above the epitaxial layer 20 and above the scribe line is removed, and the passivation layer 30 is prepared at the position where the waterproof layer 30 is removed, where the passivation layer 40 can enhance the sealing performance of the device, shield external impurities and ionic charges, enhance the stability and reliability of the device, and provide mechanical protection for the surface of the device for the subsequent processes such as scribing, mounting, and bonding, and the passivation film 40 can be made of inorganic glass or organic polymer, specifically, oxide, silicate, nitride, cyanide, synthetic resin, synthetic rubber, and the like. Preferably, silicon oxide may be selected as a material for preparing the passivation layer 40, and may be prepared using a thermal oxidation method, a thermal decomposition deposition, a sputtering, a vacuum evaporation, an anodic oxidation, an epitaxial deposition, and the like.
In step S5, the chip is diced as shown in fig. 8, and the wafer with several chip units is cut into single chip unit package structures. On the wafer of the present invention, there are usually several hundreds to thousands of chips connected together, with a gap of 80um to 150um left between them, and it is necessary to separate each chip having independent electrical properties by dicing. The invention can use mechanical diamond cutting, the diamond blade cuts the scribing area of the wafer at a high rotating speed of 3 to 4 thousands of revolutions per minute, meanwhile, the workbench which bears the wafer linearly moves along the tangential direction of the contact point of the blade and the wafer at a certain speed, silicon chips generated by cutting the wafer can be washed away by deionized water, and a plurality of chip units on the wafer can be divided into single chip unit packaging structures.
In step S6, as shown in fig. 9-10, the first metal layer 50 is prepared on the periphery of the divided chip. The whole chip is covered with metal, the whole chip is slowly heated to a certain temperature, the temperature is kept for enough time, the part of the metal, which is in contact with the substrate 10, can react to form metal silicide, and then the metal silicide is cooled at a proper speed, and the metal silicide can not react with the metal etching liquid because the covering position of the waterproof layer 30 and the passivation layer 40 can not react with the metal, as shown in figure 9, the metal etching liquid is used, so that the metal on the passivation layer 40 and the waterproof layer 30 can be removed, and the first metal layer 50 is formed. The first metal layer 50 increases the concentration of impurities on the surface of the substrate 10, and can reduce the contact resistance between the substrate 10 and the second metal layer 60, thereby reducing the dissipation power of the device.
In step S7, as shown in fig. 11, electroplating is performed on the first metal layer 50, and a second metal layer 60 is formed as a bottom electrode. The second metal layer 60 is formed on the first metal layer 50, so that the resistance of the equivalent resistor of the drain electrode of the chip can be reduced, the heat dissipation effect of the chip is greatly improved, and the power consumption during conduction is reduced.
As described above, in the method for manufacturing the package structure of the present invention, the first trench and the second trench are formed by etching the substrate 10 and the epitaxial layer 20 twice, so that the heat dissipation area of the package structure is increased, and the first trench and the second trench are communicated with each other to form the scribing groove, which can be jointly completed by combining with the conventional scribing process without adding other steps and cost; meanwhile, the whole chip is covered with a layer of metal, then the metal reacts with the surface of the substrate 10 to generate alloy under the condition of high-temperature thermal annealing, and then the metal etching liquid is used for removing the metal which does not react to form the first metal layer 50.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A preparation method of a chip packaging structure comprises a substrate, and is characterized in that: step surfaces are respectively formed on two sides of the upper surface of the substrate, and the packaging structure of the chip comprises an epitaxial layer formed on the upper surface of the substrate, a waterproof layer filled on the upper surface and the step surfaces, a first metal layer formed on the back and the side surfaces of the substrate, which are not covered by the waterproof layer and the epitaxial layer, and a second metal layer formed on the first metal layer;
the method comprises the following steps:
step S1: providing a wafer, wherein the wafer comprises a plurality of chips and scribing channels positioned among the chips, and the chips comprise substrates and epitaxial layers formed on the substrates;
step S2: a first groove extending to the substrate is formed in the scribing way, a second groove is formed in the epitaxial layer, the width of the second groove is larger than that of the first groove, and the first groove and the second groove are communicated to form a scribing groove;
step S3: forming a waterproof layer in the epitaxial layer and the scribing groove;
step S4: removing the waterproof layer which is arranged on the epitaxial layer and protrudes out of the upper surface of the epitaxial layer above the scribing groove, and preparing a passivation layer at the position where the waterproof layer is removed;
step S5: scribing the scribing groove, and dividing the chip;
step S6: preparing a first metal layer on the periphery of the divided chip, covering the whole chip, heating to a certain temperature, keeping for enough time, slowly cooling to enable the metal to react with the contact part of the substrate to generate a metal silicide layer, and removing unreacted metal on the surfaces of the passivation layer and the waterproof layer;
step S7: and preparing a metal layer on the metal silicide layer.
2. The method for manufacturing the chip package structure according to claim 1, wherein the chip package structure further comprises a passivation layer formed on the upper surfaces of the water-proof layer and the epitaxial layer, and the passivation layer is a silicon oxide protection layer.
3. The method of claim 1, wherein the filling material for the waterproof layer is polyimide.
4. The method of claim 1, wherein the first metal layer is a metal silicide layer.
5. The method as claimed in claim 4, wherein the metal silicide layer is formed by reacting titanium, tungsten, nickel, aluminum with the substrate.
6. The method of claim 1, wherein the second metal layer is a plated metal layer.
7. The method of claim 1, wherein the trench is etched in step S2 by dry etching.
8. The method for manufacturing the packaging structure of the chip according to claim 1, wherein the scribe line sidewalls are repaired by using a sacrificial oxidation method in step S2, the sacrificial oxidation method comprising the following steps:
placing the etched chip into a high-temperature furnace tube, raising the temperature, then introducing oxygen, and forming a silicon dioxide oxide layer on the side wall of the scribing groove;
and removing the silicon dioxide oxide layer by using silicon oxide etching liquid.
9. The method of claim 1, wherein the metal layer in step S7 is an electroplated metal layer, and is gold, copper, aluminum, silver, titanium, or alloy.
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| CN112349703B (en) * | 2020-10-29 | 2023-03-28 | 广州宝创集成电路设计有限公司 | Voltage stabilizing chip of test circuit and preparation method thereof |
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| CN102067335A (en) * | 2008-08-22 | 2011-05-18 | 晶能光电（江西）有限公司 | Method for fabricating InGaAlN light-emitting device on a combined substrate |
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| JP2861991B2 (en) * | 1997-10-20 | 1999-02-24 | 日亜化学工業株式会社 | Method of manufacturing gallium nitride based compound semiconductor chip |
| US6603191B2 (en) * | 2000-05-18 | 2003-08-05 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2005191485A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device |
| US8153464B2 (en) * | 2005-10-18 | 2012-04-10 | International Rectifier Corporation | Wafer singulation process |
| CN104752571A (en) * | 2013-12-31 | 2015-07-01 | 晶能光电（江西）有限公司 | Cutting method of wafer grade white-light LED chip |
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| CN102067335A (en) * | 2008-08-22 | 2011-05-18 | 晶能光电（江西）有限公司 | Method for fabricating InGaAlN light-emitting device on a combined substrate |
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