CN109041349B - Automatic address compiling device and system based on LED decoding circuit - Google Patents
Automatic address compiling device and system based on LED decoding circuit Download PDFInfo
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- CN109041349B CN109041349B CN201811020845.1A CN201811020845A CN109041349B CN 109041349 B CN109041349 B CN 109041349B CN 201811020845 A CN201811020845 A CN 201811020845A CN 109041349 B CN109041349 B CN 109041349B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention relates to the field of DMX512 control systems, in particular to an automatic address compiling device based on an LED decoding circuit, which comprises a signal receiving module, a byte counter, an address trigger, an address comparator and a trigger judging module, wherein the signal receiving module is used for receiving a signal; the signal receiving module receives external data and sends the external data to the address comparator; the byte counter counts and accumulates according to the bytes of the data received by the signal receiving module; the address trigger sends the count value of the byte counter to the address comparator; the address comparator receives data subsequently received by the signal receiving module; and when the data received by the address comparator meets the preset condition, sending a trigger signal through a next-stage writing address line. According to the invention, the LED decoding circuit completes the address setting per se without depending on the DMX512 controller, so that the freedom of selection of a user on the DMX512 controller is improved; meanwhile, the addressing speed is increased, and the addressing time is reduced from minute level to millisecond level.
Description
Technical Field
The invention relates to the field of DMX512 control systems, in particular to an automatic address compiling device and system based on an LED decoding circuit.
Background
With the increasing popularity of the demand for urban landscape lighting, the DMX512 control system and DMX512 control lamp, which are commonly used for landscape lighting, are continuously upgraded, wherein the DMX512 protocol was first developed by USITT (american theater technology association) into a method for controlling a dimmer from a console by using a standard digital interface. DMX512 is beyond analog systems, but cannot completely replace analog systems. The simplicity, reliability and flexibility of DMX512 make it a rapidly financially viable protocol of choice, as evidenced by a growing array of control devices in addition to dimmers. DMX512 is still a new field of science with various wonderful techniques generated on a regular basis.
Because the lamp controlled by the DMX512 needs to set an address, the address writing method is improved every time of upgrading and updating, so that the production of lamp manufacturers and the construction of engineering projects are facilitated.
However, the previous upgrades make the combination of the DMX512 controller and the DMX512 lamp more compact, so that the user has limitation on the selection of the DMX512 controller and can not freely select the DMX512 controller with higher cost.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an automatic address programming device based on an LED decoding circuit, aiming at the above-mentioned defects in the prior art, so as to solve the problems that a user has limitations on the selection of a DMX512 controller and cannot freely select a DMX512 controller with a higher cost.
The technical problem to be solved by the present invention is to provide an automatic address programming system based on an LED decoding circuit, aiming at the above-mentioned defects in the prior art, so as to solve the problems that a user has limitations on the selection of a DMX512 controller and cannot freely select a DMX512 controller with a higher cost.
The technical scheme adopted by the invention for solving the technical problems is as follows: the automatic address programming device based on the LED decoding circuit comprises a signal receiving module, a byte counter, an address trigger, an address comparator and a trigger judging module; the signal receiving module is respectively connected with the byte counter and the address comparator, receives external data and sends the external data to the address comparator; the byte counter is respectively connected with the address trigger and the address comparator, counts and accumulates according to the bytes of the data received by the signal receiving module, and sends the count value to the address comparator; the address trigger is connected with the address chip and connected with the upper-level writing address line or suspended, the address chip is connected with the address comparator, and when the upper-level writing address line has a trigger signal input or suspended and the byte counter starts counting, the counting value of the byte counter is sent to the address comparator through the address chip; the address comparator is connected with the trigger judgment module, and receives the data subsequently received by the signal receiving module when the count value sent by the byte counter is greater than or equal to the count value sent by the address chip; the trigger judging module is connected with the next-stage writing address line, and the data received by the address comparator meets the preset condition and then sends a trigger signal through the next-stage writing address line.
Wherein, the preferred scheme is: the automatic address compiling device also comprises a mark signal identification module connected with the signal receiving module, the mark signal identification module is also respectively connected with the byte counter and the trigger judgment module, and when the signal receiving module receives the mark signal, the mark signal identification module identifies the mark signal, controls the byte counter to be reset and clears the data of the trigger judgment module; the byte counter counts and accumulates according to the bytes of the serial data received by the signal receiving module.
Wherein, the preferred scheme is: the signal receiving module comprises an RS-485 interface and a UART communication interface, the UART communication interface is respectively connected with the RS-485 interface, the byte counter and the address comparator, the RS-485 interface receives external data and sends the external data to the UART communication interface, and the UART communication interface decodes the data and sends the decoded data to the address comparator.
Wherein, the preferred scheme is: the RS-485 interface acquires data sent by an external DMX512 controller, and the UART communication interface decodes the received data according to a standard DMX protocol or an extended DMX protocol.
Wherein, the preferred scheme is: the trigger judging module comprises a buffer byte counter and a count value comparator, wherein the buffer byte counter is respectively connected with the address comparator and the mark signal identification module; the buffer byte counter counts after the address comparator receives the serial data, the count value comparator comprises a preset count value, and when the count value of the buffer byte counter is larger than or equal to the preset count value, a trigger signal is sent through a next-stage write address line; the flag signal identification module identifies the flag signal and controls the buffer byte counter to be cleared.
Wherein, the preferred scheme is: the trigger judgment module comprises a PWM cache register group and a PWM cache register judgment module, wherein the PWM cache register group is respectively connected with the address comparator and the mark signal identification module, and the PWM cache register judgment module is respectively connected with a next-level write address line and the PWM cache register group; the PWM cache register group comprises a plurality of PWM cache registers, the address comparator receives serial data and sends the serial data to the PWM cache registers, each PWM cache register stores a section of serial data, and when all the PWM cache registers store the serial data, the PWM cache register judgment module sends a trigger signal through a next-level addressing line; the flag signal identification module identifies the flag signal and clears the PWM buffer register.
Wherein, the preferred scheme is: the address trigger is also connected with a mark signal identification module, the mark signal identification module identifies mark signals and controls the address trigger to trigger, and the address trigger can be triggered only once in a period of receiving serial data.
Wherein, the preferred scheme is: the automatic address compiling device also comprises an address chip, an address locking switch and an address same time counter; the address chip is respectively connected with an address locking switch, an address same-time counter, an address comparator and an address trigger, the address trigger sends the count value of the byte counter to the address chip, and the address chip sends the count value to the address comparator; the address same time counter counts and accumulates according to the same comparison of the address comparator, and triggers the address locking switch when the count value of the address same time counter reaches a threshold value; the address locking switch locks the address chip after being triggered, the address chip cannot be modified, and the address locking switch controls the address chip to unlock after receiving power-on unlocking information and special instruction unlocking information.
Wherein, the preferred scheme is: the automatic address programming device also comprises an address buffer register which is respectively connected with the address chip and the counter with the same address times, receives the old data sent by the address chip and is used for comparing the counter with the same address times.
The technical scheme adopted by the invention for solving the technical problems is as follows: providing an automatic address programming system based on an LED decoding circuit, wherein the automatic address programming system comprises a plurality of automatic address programming devices according to claims 1-8 and a DMX512 controller, an address trigger of the first automatic address programming device is suspended, and an address trigger of the next automatic address programming device is connected with a trigger judgment module of the last automatic address programming device; and the signal receiving module of each automatic address programming device is connected with the DMX512 controller and receives data sent by the DMX512 controller.
Compared with the prior art, the invention has the beneficial effects that the LED decoding circuit can set the address by designing the automatic address compiling device and system based on the LED decoding circuit, the DMX512 controller is not relied on any more, and the freedom of selection of a user on the DMX512 controller is improved; meanwhile, the addressing speed is increased, and the addressing time is reduced from minute level to millisecond level.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic structural diagram of a first embodiment of an automatic address programming apparatus according to the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of an automatic address programming apparatus according to the present invention;
FIG. 3 is a schematic structural diagram of an automatic address programming apparatus based on a buffer byte counter according to the present invention;
FIG. 4 is a schematic structural diagram of an automatic address programming device based on a PWM cache register set according to the present invention;
FIG. 5 is a schematic structural diagram of an automatic address programming device based on an address chip according to the present invention;
FIG. 6 is a schematic structural diagram of an address buffer register-based automatic address programming apparatus according to the present invention;
FIG. 7 is a block diagram of an auto-programming address system of the present invention.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
As shown in fig. 1 and 2, the present invention provides a preferred embodiment of an automatic address programming apparatus based on an LED decoding circuit.
An automatic address programming device based on an LED decoding circuit 1 comprises a signal receiving module 11, a byte counter 12, an address trigger 13, an address chip 191, an address comparator 14 and a trigger judging module 15; the signal receiving module 11 is respectively connected to the byte counter 12 and the address comparator 14, receives external data, and sends the external data to the address comparator 14; the byte counter 12 is respectively connected with the address trigger 13 and the address comparator 14, counts and accumulates according to the bytes of the data received by the signal receiving module 11, and sends the count value to the address comparator 14; the address trigger 13 is connected with the address chip 191, and is connected with the upper-level address writing line 16 or is suspended, the address chip 191 is connected with the address comparator 14, and when the upper-level address writing line 16 has a trigger signal input or is suspended and the byte counter 12 starts counting and accumulating, the counting value of the byte counter 12 is sent to the address comparator 14 through the address chip 191; the address comparator 14 is connected to the trigger judging module 15, and receives the data subsequently received by the signal receiving module 11 when the count value sent by the byte counter 12 is greater than or equal to the count value sent by the address trigger 13; the trigger judging module 15 is connected to the next-stage address line 17, and sends a trigger signal through the next-stage address line 17 when the data received by the address comparator 14 satisfies a preset condition.
The count value sent by the address flip-flop 13 is the address of the address flip-flop 13.
The byte counter 12 increments by 1 each time the signal receiving module 11 receives a byte.
Further, the LED decoding circuit 1 is preferably a DMX decoding circuit, the DMX control lamp is composed of a DMX decoding circuit portion, a driving circuit portion and an LED, an external DMX controller controls the DMX control lamp to work, that is, sends a control signal to the DMX decoding circuit portion to realize signal decoding, and the DMX controller is preferably a DMX512 controller 2.
As shown in fig. 3 and 4, the present invention provides a preferred embodiment of an automatic address programming apparatus.
In this embodiment, the data includes a flag signal and serial data, the automatic address compiling apparatus further includes a flag signal identification module 18 connected to the signal receiving module 11, the flag signal identification module 18 is further connected to the byte counter 12 and the trigger judgment module 15, respectively, and when the signal receiving module 11 receives the flag signal, the flag signal identification module 18 identifies the flag signal and controls the byte counter 12 to clear, and clears the data of the trigger judgment module 15; the byte counter 12 counts and accumulates bytes according to the serial data received by the signal receiving module 11. The mark signal is a SPACE mark signal, and the mark signal identification module 18 is a SPACE mark signal identification module 18.
Further, the address flip-flop 13 is also connected to a flag signal identification module 18, the flag signal identification module 18 identifies the flag signal and controls the address flip-flop 13 to trigger, and the address flip-flop 13 can only trigger once in the period of receiving serial data. The address interception trigger is triggered only once in a frame data period, and the next trigger can not be carried out until next frame data arrives and a mark signal is identified.
In this embodiment, the signal receiving module 11 includes an RS-485 interface 111 and a UART communication interface 112, the UART communication interface 112 is respectively connected to the RS-485 interface 111, the byte counter 12 and the address comparator 14, the RS-485 interface 111 receives external data and sends the external data to the UART communication interface 112, and the UART communication interface 112 decodes the external data and sends the decoded data to the address comparator 14.
The intelligent instrument is developed along with the maturity of the single chip microcomputer technology in the early 80 s, and the world instrument market is basically monopolized by the intelligent instrument at present, which is attributed to the requirement of enterprise informatization, and one of the necessary conditions of the enterprise in instrument model selection is to have a networking communication interface. The simple process quantity of data analog signal output is the first, and the instrument interface is the RS232 interface later, and the interface can realize a point-to-point communication mode, but the networking function cannot be realized in the mode, and the RS485 appearing later solves the problem. A Universal Asynchronous Receiver/Transmitter (UART), commonly referred to as UART, is an Asynchronous Receiver/Transmitter that is part of the computer hardware. It converts data to be transmitted between serial communication and parallel communication. As a chip for converting a parallel input signal into a serial output signal, the UART is usually integrated into a connection of other communication interfaces.
Further, the RS-485 interface 111 obtains data sent by the external DMX512 controller 2, and the UART communication interface 112 decodes the received data according to the standard DMX protocol or the extended DMX protocol.
Specifically, the RS-485 interface 111 also includes corresponding RS-485 interface 111 circuitry for receiving electrical signals that conform to the RS-485 specification. The UART communication interface 112 is a DMX protocol receiving circuit, and is composed of a UART (universal asynchronous receiver transmitter) for serial decoding of data transmitted from the data interface circuit, and the module has the SPACE mark recognition capability of the DMX protocol. The signals of the DMX512 controller 2, preferably DMX512-1990, DMX512-1990 are sent to the UART communication interface 112 via the RS-485 interface 111 and decoded.
When the UART communication interface 112 receives a SPACE (generally 88 microsecond low level) signal of the DMX512-1990 signal, a SPACE identification mark signal is output, and the SPACE identification mark signal triggers a zero clearing circuit of the byte counter 12 to clear the count value of the byte counter 12; meanwhile, the trigger judging module 15 is triggered to perform emptying operation.
When the standard DMX512-1990 signal follows SPACE, 513 bytes of serial data are immediately followed, the serial data (8 bits) is received by 2 pairs, the byte counter 12 counts every time a byte trigger 5 is received, and sends the data to the address comparator 14, and the trigger judgment module 15 is sent after the address comparator 14 is turned on.
The present embodiment provides two preferred schemes for triggering the determining module 15.
Scheme I,
The trigger judging module 15 includes a buffer byte counter 151 and a count value comparator 152, the buffer byte counter 151 is connected to the address comparator 14 and the flag signal identifying module 18 respectively; the buffer byte counter 151 counts after the address comparator 14 receives the serial data, the count value comparator 152 includes a preset count value, and when the count value of the buffer byte counter 151 is greater than or equal to the preset count value, a trigger signal is sent through the next-stage write address line 17; the flag signal identification module 18 identifies the flag signal and controls the buffer byte counter 151 to be cleared.
Scheme II,
The trigger judging module 15 includes a PWM cache register group 153 and a PWM cache register judging module 154, the PWM cache register group 153 is respectively connected to the address comparator 14 and the flag signal identifying module 18, and the PWM cache register judging module 154 is respectively connected to the next-level address writing line 17 and the PWM cache register group 153; the PWM buffer register group 153 includes a plurality of PWM buffer registers, the address comparator 14 receives serial data and sends the serial data to the PWM buffer registers, each PWM buffer register stores a section of serial data, and when all PWM buffer registers store serial data, the PWM buffer register determination module 154 sends a trigger signal through the next-stage addressing line 17; the flag signal identification module 18 identifies the flag signal and clears the PWM buffer register.
Specifically, assuming that the preset value is 3, the 2 nd to 4 th bytes after the SPACE flag signal will be counted by the buffer byte counter 12, when the 4 th byte is received, the value of the buffer byte counter 151 is 3, and the count value comparator 152 compares the value of the buffer byte counter 151 with the preset value to control the next-stage write address line 17 to output the level signal; and the value of the byte counter 12 of all automatic address programming devices on the bus is 4 at this time, after the second automatic address programming device receives the trigger level sent by the first chip, the count value of the byte counter 12 is sent to the address chip 191, the address comparator 14 of the second automatic address programming device compares the count value of the byte counter 12 with the value of the address trigger 13, the address comparator 14 is turned on, and the subsequent received data enables the buffer byte counter 151 of the second automatic address programming device to work; after the address comparator 14 of the second automatic address programming device is turned on, the 5 th byte to the 7 th byte after the SPACE mark is counted and recorded by the buffer byte counter 151 of the second automatic address programming device, that is, the counting is accumulated to 3, at this time, assuming that the preset value of the count value comparator 152 of the second automatic address programming device is 3, when the 7 th byte is received, the count value of the buffer byte counter 151 is also 3, and the next-stage address writing line 17 of the count value comparator 152 sends a trigger signal; and analogizing in turn, finishing the addressing of all the automatic address programming devices on the bus.
Or, assuming that the PWM buffer register group 153 is three PWM buffer registers, the 2 nd to 4 th bytes after the SPACE flag signal are respectively stored in the corresponding PWM buffer registers, and when the 4 th byte is received, all PWM buffer registers of the PWM buffer register group 153 are already full, and the PWM buffer register determination module 154 controls the next-level write address line 17 to output a level signal; the operation is identical to that described above and will not be described here.
As shown in fig. 5 and 6, the present invention provides a preferred embodiment of an address chip.
The auto-programming address device also includes an address lock switch 192 and an address same number counter 193; the address chip 191 is connected to the address lock switch 192, the address same-time counter 193, the address comparator 14 and the address flip-flop 13, respectively, the address flip-flop 13 sends the count value of the byte counter 12 to the address chip 191, and the address chip 191 sends the count value to the address comparator 14; the address same number counter 193 counts and accumulates according to the same comparison of the address comparator 14, and triggers the address lock switch 192 when the count value of the address same number counter 193 reaches a threshold value; the address lock switch 192 locks the address chip 191 after being triggered, the address chip 191 cannot be modified, and the address lock switch 192 controls the address chip 191 to unlock after receiving the power-on unlocking information and the special instruction unlocking information. The flexibility of the chip is increased.
The address same time counter 193 is used to prevent the address comparator 14 or the automatic address programming device which tends to be in a stable state from receiving external interference, and to count and accumulate or judge errors, so as to realize address locking.
Further, the address buffer 194 is connected to the address chip 191 and the address parity number counter 193, and receives the old data sent by the address chip 191 for comparison by the address parity number counter 193. And the anti-interference capability of automatic addressing is enhanced.
The special instruction unlocking information is transmitted through the RS-485 interface 111, and is triggered in the address locking switch 192 to control the address chip 191 to perform the unlocking operation.
Further, in order to prevent the address comparator 14 from being turned on early, after the power-on or addressing is triggered, the value of the address comparator 14 is the maximum value that can be set, and the operation cannot be performed again.
As shown in FIG. 7, the present invention provides a preferred embodiment of an automatic programming address system based on LED decoding circuitry.
An automatic address programming system based on an LED decoding circuit 1, comprising a plurality of automatic address programming devices according to claims 1-8 and a DMX512 controller 2, wherein an address trigger 13 of the first automatic address programming device is suspended, and an address trigger 13 of the next automatic address programming device is connected with a trigger judgment module 15 of the last automatic address programming device; the signal receiving module 11 of each automatic address programming device is connected with the DMX512 controller 2 and receives data sent by the DMX512 controller 2.
Further, the address trigger 13 does not trigger when receiving a low level signal, and triggers when receiving a high level signal; alternatively, the address flip-flop 13 does not trigger when receiving a high level signal, and triggers when receiving a low level signal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, but rather as embodying the invention in a wide variety of equivalent variations and modifications within the scope of the appended claims.
Claims (10)
1. An automatic address programming device based on an LED decoding circuit is characterized in that: the automatic address compiling device comprises a signal receiving module, a byte counter, an address trigger, an address chip, an address comparator and a trigger judging module; wherein the content of the first and second substances,
the signal receiving module is respectively connected with the byte counter and the address comparator, receives external data and sends the external data to the address comparator; the byte counter is respectively connected with the address trigger and the address comparator, counts and accumulates according to the bytes of the data received by the signal receiving module, and sends the count value to the address comparator; the address trigger is connected with the address chip and connected with the upper-level writing address line or suspended, the address chip is connected with the address comparator, and when the upper-level writing address line has a trigger signal input or suspended and the byte counter starts counting, the counting value of the byte counter is sent to the address comparator through the address chip; the address comparator is connected with the trigger judgment module, and receives the data subsequently received by the signal receiving module when the count value sent by the byte counter is greater than or equal to the count value sent by the address chip; the trigger judging module is connected with the next-stage writing address line, and the data received by the address comparator meets the preset condition and then sends a trigger signal through the next-stage writing address line.
2. The automatic programming address device of claim 1, wherein: the automatic address compiling device also comprises a mark signal identification module connected with the signal receiving module, the mark signal identification module is also respectively connected with the byte counter and the trigger judgment module, and when the signal receiving module receives the mark signal, the mark signal identification module identifies the mark signal, controls the byte counter to be reset and clears the data of the trigger judgment module; the byte counter counts and accumulates the bytes of the serial data received by the signal receiving module.
3. The automatic programming address device according to claim 1 or 2, characterized in that: the signal receiving module comprises an RS-485 interface and a UART communication interface, the UART communication interface is respectively connected with the RS-485 interface, the byte counter and the address comparator, the RS-485 interface receives external data and sends the external data to the UART communication interface, and the UART communication interface decodes the data and sends the decoded data to the address comparator.
4. The automatic programming address device of claim 3, wherein: the RS-485 interface acquires data sent by an external DMX512 controller, and the UART communication interface decodes the received data according to a standard DMX protocol or an extended DMX protocol.
5. The automatic programming address device of claim 2, wherein: the trigger judging module comprises a buffer byte counter and a count value comparator, wherein the buffer byte counter is respectively connected with the address comparator and the mark signal identification module; the buffer byte counter counts after the address comparator receives the serial data, the count value comparator comprises a preset count value, and when the count value of the buffer byte counter is larger than or equal to the preset count value, a trigger signal is sent through a next-stage write address line; the flag signal identification module identifies the flag signal and controls the buffer byte counter to be cleared.
6. The automatic programming address device of claim 2, wherein: the trigger judgment module comprises a PWM cache register group and a PWM cache register judgment module, wherein the PWM cache register group is respectively connected with the address comparator and the mark signal identification module, and the PWM cache register judgment module is respectively connected with a next-level write address line and the PWM cache register group; wherein the content of the first and second substances,
the PWM cache register group comprises a plurality of PWM cache registers, the address comparator receives serial data and then sends the serial data to the PWM cache registers, each PWM cache register stores a section of serial data, and when all the PWM cache registers store the serial data, the PWM cache register judgment module sends a trigger signal through a next-level write address line; the flag signal identification module identifies the flag signal and clears the PWM buffer register.
7. The automatic programming address device of claim 2, wherein: the address trigger is also connected with a mark signal identification module, the mark signal identification module identifies mark signals and controls the address trigger to trigger, and the address trigger can be triggered only once in a period of receiving serial data.
8. The automatic programming address device according to claim 1 or 2, characterized in that: the automatic address compiling device also comprises an address locking switch and an address same time counter; wherein the content of the first and second substances,
the address chip is respectively connected with an address locking switch, an address same-time counter, an address comparator and an address trigger, the address trigger sends the count value of the byte counter to the address chip, and the address chip sends the count value to the address comparator; the address same time counter counts and accumulates according to the same comparison of the address comparator, and triggers the address locking switch when the count value of the address same time counter reaches a threshold value; the address locking switch locks the address chip after being triggered, the address chip cannot be modified, and the address locking switch controls the address chip to unlock after receiving power-on unlocking information or special instruction unlocking information.
9. The automatic programming address device of claim 8, wherein: the automatic address programming device also comprises an address buffer register which is respectively connected with the address chip and the counter with the same address times, receives the old data sent by the address chip and is used for comparing the counter with the same address times.
10. An automatic address compiling system based on an LED decoding circuit is characterized in that: the automatic address programming system comprises a plurality of automatic address programming devices and DMX512 controllers according to claims 1-8, wherein an address trigger of a first automatic address programming device is suspended, and an address trigger of a next automatic address programming device is connected with a trigger judgment module of a previous automatic address programming device; and the signal receiving module of each automatic address programming device is connected with the DMX512 controller and receives data sent by the DMX512 controller.
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| CN115297089B (en) * | 2022-08-01 | 2024-02-27 | 宁波赛耐比光电科技有限公司 | Full-automatic address allocation system and method |
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| CN202652652U (en) * | 2012-06-28 | 2013-01-02 | 四川九洲光电科技股份有限公司 | LED control driving unit capable of automatically writing address via RS-485 bus |
| CN204291487U (en) * | 2014-12-03 | 2015-04-22 | 深圳市健炜创光电科技有限公司 | Based on the LED automatic addressing circuit of DMX512, light fixture and system |
| CN105392228B (en) * | 2015-10-22 | 2017-12-22 | 四川九洲光电科技股份有限公司 | The automatic write address method of light fixture based on DMX512 agreements |
| CN106201964B (en) * | 2016-07-14 | 2019-02-15 | 陕西科技大学 | The on-line automatic addressing of RDM driver and RDM bus short circuit positioning device and method |
| CN107918589B (en) * | 2017-11-15 | 2021-05-04 | 中国计量大学 | High-efficient buffer memory concurrency system of DMX512 signal based on FPGA |
| CN207692091U (en) * | 2017-12-01 | 2018-08-03 | 上海光联照明有限公司 | LED lamp system based on DMX512 agreements |
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2018
- 2018-09-03 CN CN201811020845.1A patent/CN109041349B/en active Active
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