CN109037045B - Ion implantation method, manufacturing method of semiconductor device and semiconductor device - Google Patents
Ion implantation method, manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN109037045B CN109037045B CN201810635332.5A CN201810635332A CN109037045B CN 109037045 B CN109037045 B CN 109037045B CN 201810635332 A CN201810635332 A CN 201810635332A CN 109037045 B CN109037045 B CN 109037045B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000005468 ion implantation Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000011521 glass Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000002513 implantation Methods 0.000 claims abstract description 12
- 239000000203 mixture Substances 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 126
- 229920002120 photoresistant polymer Polymers 0.000 claims description 44
- 238000001312 dry etching Methods 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides an ion implantation method, a semiconductor device manufacturing method and a semiconductor device, wherein the ion implantation method comprises the following steps: step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate; step S2, plating metal on the surface of the gate insulating layer to form a metal film layer; step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein a hollow window is formed on the metal mask at the position corresponding to the two ends of the channel doping region; and step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region at two ends of the channel doping region. The invention can realize that no gas molecules overflow in the ion implantation process, ensure the ion implantation effect and the control of the ion implantation amount, improve the electrical property convergence of the device, and increase the implantation current because no gas overflows.
Description
Technical Field
The present invention relates to the field of semiconductor device technology, and in particular, to an ion implantation method, a semiconductor device manufacturing method, and a semiconductor device.
Background
In the ion implantation process, due to the capacity requirement, a large current is required to be used for carrying out ion implantation on the glass substrate coated with the photoresist, wherein the photoresist is used as a shielding layer for the ion implantation; so that the gas molecules in the photoresist are subjected to the thermal effect after ion bombardment and can volatilize out of the glass substrate (Outgas); the collisions of ions with gas molecules during ion implantation result in electrical neutralization of the doped ions. In particular, the amount of the solvent to be used,
in the glass produced, these neutral ions cause non-uniform doping and cannot be detected by the IMP tool faraday cup, resulting in inaccurate implantation dose counting. In view of the above problems, it is desirable to provide a new ion implantation method, so that neutral ions are not generated during the ion implantation process, thereby improving the ion implantation effect.
Disclosure of Invention
The invention aims to solve the technical problem of providing an ion implantation method, a semiconductor device manufacturing method and a semiconductor device, wherein a metal film is used for replacing photoresist to be used as a shielding layer for ion implantation, so that no gas molecules overflow in the ion implantation process.
The invention provides an ion implantation method for manufacturing a semiconductor device, which comprises the following steps:
step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate;
step S2, plating metal on the surface of the gate insulating layer to form a metal film layer;
step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein the metal mask forms a hollow window at the position corresponding to the two ends of the channel doping region;
and step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region at two ends of the channel doping region.
Wherein, the step S1 specifically includes:
sequentially manufacturing a light shielding layer and a buffer layer on the glass substrate;
and sequentially manufacturing a channel doping region and a gate insulating layer on the buffer layer.
Wherein the metal is one of molybdenum, aluminum or titanium.
Wherein the step S3 includes:
coating a photoresist material on the surface of the metal film layer to form a first photoresist layer;
exposing and developing the first photoresist layer;
dry etching the metal film layer;
and removing the first photoresist layer to form the metal mask.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate;
step S2, plating metal on the surface of the gate insulating layer to form a metal film layer;
step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein a hollow window is formed on the metal mask at the position corresponding to the two ends of the channel doping region;
and step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region at two ends of the channel doping region.
Step S5, carrying out composition process treatment on the metal mask to manufacture and form a grid;
step S6, forming an interlayer insulating layer, a source electrode and a drain electrode on the gate electrode.
Wherein, the step S1 specifically includes:
sequentially forming a light shielding layer and a buffer layer on the glass substrate;
and sequentially forming a channel doping region and a gate insulating layer on the buffer layer.
Wherein the metal is one of molybdenum, aluminum or titanium.
Wherein, the step S5 specifically includes:
coating a photoresist material on the metal mask to form a second photoresist layer;
exposing and developing the second photoresist layer;
dry etching the metal mask;
and removing the second photoresist layer to form a gate above the channel doping region.
The present invention also provides a semiconductor device comprising:
a glass substrate;
a light shielding layer, a buffer layer, a channel doping region and a gate insulating layer which are sequentially formed on the surface of the glass substrate; forming an active doping area and a drain doping area on two sides of the channel doping area of the gate insulating layer by the ion implantation method;
the metal mask is manufactured into a grid electrode by adopting a drawing process;
an interlayer insulating layer, a source electrode and a drain electrode formed on the gate electrode.
Wherein the metal is one of molybdenum, aluminum or titanium.
The invention uses the metal film to replace the photoresist to be used as the ion implantation shielding layer, achieves the effect of no gas molecule overflow in the ion implantation process, ensures the ion implantation effect and the control of the ion implantation amount, improves the electrical property convergence of the device, and can increase the implantation current because of no gas overflow, especially for the manufacture of high implantation dosage, through the method, the implantation current is at least improved by 50 percent, so that the production time of a single product is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flow chart of an ion implantation method of the present invention.
Fig. 2 is a flow chart of a method of fabricating a semiconductor device of the present invention.
Fig. 3 is a schematic structural view of the gate insulating layer before a metal mask is formed.
Fig. 4 is a schematic structural view after a metal mask is formed in fig. 3.
Fig. 5 is a schematic structural diagram after P-type heavy doping is carried out on fig. 4.
FIG. 6 is a schematic diagram of the structure of FIG. 5 after coating with photoresist.
Fig. 7 is a schematic view of the structure of fig. 6 after exposure and development.
Fig. 8 is a schematic view of the structure of fig. 7 after dry etching.
FIG. 9 is a schematic diagram of the structure of FIG. 7 after removing the photoresist layer.
Fig. 10 is a graph showing the results of electrical simulations of the semiconductor device obtained by the present invention and the semiconductor device obtained by the prior art.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the invention may be practiced.
Referring to fig. 1, an embodiment of the present invention provides an ion implantation method, including:
and step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate.
Specifically, a light shielding layer and a gate insulating layer are sequentially manufactured on the glass substrate, and a channel doping region and a gate insulating layer are sequentially manufactured on the gate insulating layer.
Wherein, a light shielding layer, a buffer layer, a channel doping region and a gate insulating layer may be sequentially formed on the surface of the glass substrate using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
And step S2, plating metal on the surface of the gate insulating layer to form a metal film layer.
Wherein the metal is one of molybdenum, aluminum or titanium.
Specifically, a metal film layer may be formed on the surface of the gate insulating layer by means of Physical Vapor Deposition (PVD).
And step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein the metal mask is provided with hollow windows at the corresponding positions on the two sides of the channel doping region.
The metal film layer is subjected to composition process treatment, and the method specifically comprises the following steps:
coating a photoresist material on the surface layer of the metal film layer to form a first photoresist layer,
exposing and developing the first photoresist layer to form hollow windows at the positions corresponding to the two sides of the channel doping region on the metal film layer,
dry-etching the metal film layer,
and removing the first photoresist layer to form the metal mask.
And step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region on two sides of the channel doping region.
Based on the first embodiment of the present invention, the second embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method includes the following steps:
steps S1-S4 in this embodiment are identical to steps S1-S4 in the first embodiment, and thus will not be described again.
And step S5, carrying out composition process treatment on the metal mask to manufacture and form a grid.
The metal mask layer is subjected to a composition process, and the manufacturing and forming of the grid specifically comprises the following steps:
coating a photoresist material on the metal mask to form a second photoresist layer, carrying out photomask exposure on the second photoresist layer, adding a developing solution for development to form an expected pattern on the second photoresist layer, carrying out dry etching on the metal mask, and removing the second photoresist layer after the dry etching is finished, thereby forming the grid electrode positioned above the channel doping area.
Step S6, forming an interlayer insulating layer, a source electrode and a drain electrode on the gate electrode.
Specifically, an interlayer insulating layer is formed over the gate electrode, a via hole is formed between the gate insulating layer and the interlayer insulating layer, and a source electrode and a drain electrode are formed in the via hole such that the source electrode is connected to the source doped region and the drain electrode is connected to the drain doped region.
Accordingly, a third embodiment of the present invention further provides a semiconductor device, which includes:
a glass substrate;
a light shielding layer, a buffer layer, a channel doping region and a gate insulating layer which are sequentially formed on the surface of the glass substrate; forming an active doping area and a drain doping area on two sides of the channel doping area of the gate insulating layer by the ion implantation method;
the metal mask is manufactured into a grid electrode by adopting a drawing process;
an interlayer insulating layer, a source electrode and a drain electrode formed on the gate electrode.
The above method is specifically described below with reference to fig. 3 to 9.
As shown in fig. 3, a glass substrate 1 is provided, and a light shielding layer 2, a buffer layer, a channel doping region 5 and a gate insulating layer 6 are sequentially formed on the glass substrate 1 by a plasma enhanced chemical deposition (PECVD) method, wherein the buffer layer includes a silicon nitride layer 3 and a silicon oxide layer 4 sequentially deposited on the glass substrate.
As shown in fig. 4, a metal film is first formed on the surface of the gate insulating layer 6 by plating. Wherein the metal may be one of molybdenum, aluminum or titanium. Specifically, a metal film layer may be formed on the surface of the gate insulating layer by using a physical vapor deposition method.
Then, coating a photoresist material on the surface of the metal film layer to form a first photoresist layer, carrying out photomask exposure on the first photoresist layer, dripping a developing solution, and developing the first photoresist layer to form a patterned area, wherein the patterned area forms hollow windows at the corresponding positions of the two sides of the doped area. And etching the metal film layer by an etching process, specifically, dry-etching the metal film layer, and removing the first photoresist layer to form a metal mask 7, wherein the metal mask 7 forms hollow windows at positions corresponding to two sides of the channel doping region.
As shown in fig. 5, the front-end device is subjected to P + ion implantation, and since the metal mask layer 7 is formed over most of the surface of the gate insulating layer, in the ion implantation process, the doped regions 9 are formed only on two sides of the channel doped region below the gate insulating layer where the metal mask layer 7 is not formed, and the two doped regions 9 are the source region and the drain region, so that the original channel doped region is composed of the doped regions 9 at two ends and the doped region 8 in the middle.
The ion implantation system includes an ion implantation system with a mass analyzer, an ion cloud implantation system without an ion implanter, a plasma implantation system, or a solid diffusion implantation system.
As shown in fig. 6, a photoresist material is applied to the surface of the metal mask 7 to form a second photoresist layer 10, and the second photoresist layer 10 is exposed and developed to obtain a second photoresist 11 in the patterned area shown in fig. 7.
As shown in fig. 8-9, the metal mask layer 7 is dry etched to form a gate island, and the second photoresist layer is removed, so as to obtain a gate 12 located above the channel doping region.
As shown in fig. 10, which is a graph of simulation results of the resistance of the P-type heavily doped device obtained by the method of the present invention and the resistance of the P-type heavily doped device in the prior art (i.e. using photoresist as the blocking layer for ion implantation), as shown in the figure, the resistance corresponding to the doped region in the prior art is 5518.46, and the standard deviation is 932.7; the metal mask is used as the blocking layer for ion implantation, and the resistance value corresponding to the doped region is 3701.66, and the standard deviation is 314.4. According to the comparison result, the resistance value and the standard deviation value of the P-type heavily doped device can be reduced by adopting the method provided by the invention.
The invention uses the metal film to replace the photoresist to be used as the ion implantation shielding layer, achieves the effect of no gas molecule overflow in the ion implantation process, ensures the ion implantation effect and the control of the ion implantation amount, improves the electrical property convergence of the device, and can increase the implantation current because of no gas overflow, especially for the manufacture of high implantation dosage, through the method, the implantation current is at least improved by 50 percent, so that the production time of a single product is shortened.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (8)
1. An ion implantation method, comprising the steps of:
step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate;
step S2, plating metal on the surface of the gate insulating layer to form a metal film layer;
step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein a hollow window is formed on the metal mask at the position corresponding to the two ends of the channel doping region;
step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region at two ends of the channel doping region;
wherein, the step S1 specifically includes:
sequentially manufacturing a light shielding layer and a buffer layer on the glass substrate;
and sequentially manufacturing a channel doping region and a gate insulating layer on the buffer layer.
2. The implantation method of claim 1, wherein the metal is one of molybdenum, aluminum, or titanium.
3. The injection method according to claim 1, wherein the step S3 specifically includes:
coating a photoresist material on the surface of the metal film layer to form a first photoresist layer;
exposing and developing the first photoresist layer to form a patterned region with a hollow window at the position corresponding to the two ends of the channel doping region;
dry etching the metal film layer;
and removing the first photoresist layer to form the metal mask.
4. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
step S1, providing a glass substrate, and at least sequentially manufacturing a channel doping area and a gate insulating layer on the glass substrate;
step S2, plating metal on the surface of the gate insulating layer to form a metal film layer;
step S3, carrying out composition process treatment on the metal film layer to form a metal mask, wherein a hollow window is formed on the metal mask at the position corresponding to the two ends of the channel doping region;
step S4, performing ion implantation by taking the metal mask as a mask plate, and forming a source doping region and a drain doping region at two ends of the channel doping region;
step S5, carrying out composition process treatment on the metal mask to manufacture and form a grid;
step S6, forming an interlayer insulating layer, a source electrode and a drain electrode on the gate electrode;
wherein, the step S1 specifically includes:
sequentially forming a light shielding layer and a buffer layer on the glass substrate;
and sequentially forming a channel doping region and a gate insulating layer on the buffer layer.
5. The method of claim 4, wherein the metal is one of molybdenum, aluminum, or titanium.
6. The manufacturing method according to claim 4, wherein the step S5 specifically includes:
coating a photoresist material on the metal mask to form a second photoresist layer;
exposing and developing the second photoresist layer;
dry etching the metal mask;
and removing the second photoresist layer to form a gate above the channel doping region.
7. A semiconductor device, comprising:
a glass substrate;
a light shielding layer, a buffer layer, a channel doping region and a gate insulating layer which are sequentially formed on the surface of the glass substrate; wherein an active doping region and a drain doping region are formed on both sides of a channel doping region of the gate insulating layer by the ion implantation method of claim 1;
the metal mask is manufactured into a grid electrode by adopting a drawing process;
an interlayer insulating layer, a source electrode and a drain electrode formed on the gate electrode.
8. The semiconductor device according to claim 7, wherein:
the metal is one of molybdenum, aluminum or titanium.
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| CN201810635332.5A CN109037045B (en) | 2018-06-20 | 2018-06-20 | Ion implantation method, manufacturing method of semiconductor device and semiconductor device |
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| CN201810635332.5A CN109037045B (en) | 2018-06-20 | 2018-06-20 | Ion implantation method, manufacturing method of semiconductor device and semiconductor device |
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| CN109037045B true CN109037045B (en) | 2020-11-20 |
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| CN103985637B (en) * | 2014-04-30 | 2017-02-01 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display device |
| KR102442615B1 (en) * | 2015-07-09 | 2022-09-14 | 삼성디스플레이 주식회사 | Method of fabricating thin film transistor substrate |
| CN105428244A (en) * | 2016-01-14 | 2016-03-23 | 信利（惠州）智能显示有限公司 | Thin film transistor and preparation method |
| CN105810573A (en) * | 2016-03-15 | 2016-07-27 | 深圳市华星光电技术有限公司 | Manufacturing method of thin-film transistor |
| CN105742240B (en) * | 2016-04-05 | 2019-09-13 | 武汉华星光电技术有限公司 | A kind of manufacturing method of LTPS array substrate |
| CN106340457A (en) * | 2016-09-30 | 2017-01-18 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method and display panel |
| CN107968124A (en) * | 2016-10-18 | 2018-04-27 | 上海和辉光电有限公司 | A kind of semiconductor device structure and preparation method thereof |
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