CN109032230B - Low dropout voltage regulator - Google Patents
Low dropout voltage regulator Download PDFInfo
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- CN109032230B CN109032230B CN201710445119.3A CN201710445119A CN109032230B CN 109032230 B CN109032230 B CN 109032230B CN 201710445119 A CN201710445119 A CN 201710445119A CN 109032230 B CN109032230 B CN 109032230B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention provides a low-dropout voltage regulator, which comprises a low-dropout voltage regulator module with a first normal phase end input pipe, and further comprises: the current supply module is used for supplying current when the enabling signal of the low dropout voltage regulator is at a high level; the first end of the second normal phase end input pipe is connected with the first end of the first normal phase end input pipe, and the second end of the second normal phase end input pipe is connected with the second end of the first normal phase end input pipe; and the charge-discharge module is respectively connected with the current supply module and the control end of the second normal phase end input tube, and charges the charge-discharge module when the enabling signal of the low-voltage-difference voltage stabilizer is at a high level, and discharges when the enabling signal of the low-voltage-difference voltage stabilizer is at a low level. When the enabling signal of the low dropout voltage regulator jumps from low level to high level, the invention can prevent the overshoot condition of the output voltage and improve the stability of the output voltage of the low dropout voltage regulator.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a low dropout voltage regulator.
Background
Fig. 1 is a schematic diagram of a conventional low dropout regulator, and fig. 2 is a schematic diagram of signal waveforms of a conventional low dropout regulator. As shown in fig. 2, the conventional low dropout voltage regulator has the following drawbacks: the control terminal voltage v_ref ' of the positive terminal input pipe P6' always exists, and when the enable signal of the low dropout regulator is pulled high, the output voltage v_out ' of the low dropout regulator will also be pulled high, exceeding the voltage required by the low dropout regulator.
Disclosure of Invention
In view of the above problems, an objective of the embodiments of the present invention is to provide a low dropout regulator, which solves the problem of high output voltage when the enable signal of the conventional low dropout regulator is pulled up.
In order to solve the above problems, an embodiment of the present invention discloses a low dropout regulator, which includes a low dropout regulator module, the low dropout regulator module includes a first normal phase input pipe, the low dropout regulator further includes:
a current providing module, which provides current when the enable signal of the low dropout voltage regulator is at a high level;
the first end of the second normal phase end input pipe is connected with the first end of the first normal phase end input pipe, and the second end of the second normal phase end input pipe is connected with the second end of the first normal phase end input pipe;
and the charge-discharge module is respectively connected with the current supply module and the control end of the second normal phase end input tube, when the enabling signal of the low-voltage-difference voltage stabilizer is in a high level, the current supply module charges the charge-discharge module, and when the enabling signal of the low-voltage-difference voltage stabilizer is in a low level, the charge-discharge module discharges.
Optionally, the current providing module includes:
the source end of the first PMOS tube is connected with the power supply of the low-dropout voltage regulator;
the second PMOS tube is arranged in a mirror image mode with the first PMOS tube, and the drain end of the second PMOS tube is connected with the charge-discharge module and the control end of the second positive-phase end input tube respectively;
the first end of the first switching device is connected with a power supply of the low-dropout voltage regulator, the second end of the first switching device is respectively connected with the control end of the first PMOS tube and the control end of the second PMOS tube, the control end of the first switching device receives an enabling signal of the low-dropout voltage regulator, and when the enabling signal of the low-dropout voltage regulator is in a low level, the first switching device is conducted;
a current source;
the first end of the second switching device is connected with the drain end of the first PMOS tube, the second end of the second switching device is connected with the current source, the second switching device receives the enabling inverse signal of the low-dropout voltage regulator, and when the enabling inverse signal of the low-dropout voltage regulator is in a low level, the second switching device is conducted.
Optionally, the first switching device includes:
the source end of the third PMOS tube is connected with the power supply of the low-dropout voltage regulator, the drain end of the third PMOS tube is respectively connected with the control end of the first PMOS tube and the control end of the second PMOS tube, and the control end of the third PMOS tube receives the enabling signal of the low-dropout voltage regulator.
Optionally, the second switching device includes:
and the source end of the fourth PMOS tube is connected with the drain end of the first PMOS tube, the drain end of the fourth PMOS tube is connected with the first current source, and the control end of the fourth PMOS tube receives the enable inverse signal of the low-dropout voltage regulator.
Optionally, the second positive side input tube includes:
and the source end of the fifth PMOS tube is connected with the first end of the first normal phase end input tube, the drain end of the fifth PMOS tube is connected with the second end of the first normal phase end input tube, and the control end of the fifth PMOS tube is connected with the charge-discharge module.
Optionally, the current of the current source is adjustable in magnitude.
Optionally, the charge-discharge module includes:
one end of the capacitor sub-module is connected with the control ends of the current supply module and the second normal phase end input tube respectively;
and the first end of the third switching device is connected with one end of the capacitor sub-module, the second end of the third switching device is connected with the other end of the capacitor sub-module, the control end of the third switching device receives the enable inverse signal of the low-dropout voltage regulator, when the enable inverse signal of the low-dropout voltage regulator is at a high level, the third switching device is conducted, and when the enable inverse signal of the low-dropout voltage regulator is at a low level, the third switching device is disconnected.
Optionally, the capacitance submodule includes a tunable capacitor.
Optionally, the third switching device includes:
the drain end of the NMOS tube is connected with one end of the capacitor sub-module, the source end of the NMOS tube is connected with the other end of the capacitor sub-module, and the control end of the NMOS tube receives the enable inverse signal of the low-dropout voltage regulator.
The embodiment of the invention has the following advantages: by adding the current providing module, the second normal phase end input tube and the charge-discharge module in the low-voltage differential voltage stabilizer and arranging the first end of the second normal phase end input tube connected with the first end of the first normal phase end input tube in the low-voltage differential voltage stabilizer, the second end of the second normal phase end input tube is connected with the second end of the first normal phase end input tube, the charging and discharging module is connected with the current providing module and the control end of the second normal phase end input tube respectively, when the enabling signal of the low-voltage difference voltage stabilizer is in a high level, the current providing module provides current, the charging and discharging module is charged by the current providing module, and when the enabling signal of the low-voltage difference voltage stabilizer is in a low level, the charging and discharging module discharges to zero voltage. Thus, when the enable signal of the low dropout voltage regulator is at a high level, the current supply module charges the charge/discharge module, and the voltage of the charge/discharge module (i.e., the voltage of the control terminal of the second non-inverting terminal input tube) gradually increases from zero voltage. When the control end voltage of the second normal phase end input tube is smaller than the control end voltage of the first normal phase end input tube, the second normal phase end input tube is conducted, the first normal phase end input tube is in an off state, the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the second normal phase end input tube, namely when the control end voltage of the second normal phase end input tube is larger than the control end voltage of the first normal phase end input tube, the first normal phase end input tube is conducted, the second normal phase end input tube is in an off state, and the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the first normal phase end input tube. The output voltage of the low dropout voltage regulator is gradually increased from zero voltage to required voltage, the overshoot of the output voltage of the low dropout voltage regulator is avoided, and the stability of the output voltage of the low dropout voltage regulator is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional LDO;
FIG. 2 is a schematic diagram of signal waveforms of a conventional LDO;
FIG. 3 is a block diagram of one embodiment of a low dropout regulator of the present invention;
FIG. 4 is a schematic diagram of a low dropout regulator embodiment of the present invention;
fig. 5 is a schematic diagram of signal waveforms of an embodiment of a low dropout regulator according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 3, there is shown a block diagram of an embodiment of a low dropout regulator of the present invention, the low dropout regulator including a low dropout regulator module 1, the low dropout regulator module 1 including a first positive side input pipe 11, the low dropout regulator further comprising: a current providing module 2, when the enable signal of the low dropout voltage regulator is at a high level, the current providing module 2 providing a current; the second normal phase end input pipe 3, the first end of the second normal phase end input pipe 3 is connected with the first end of the first normal phase end input pipe 11, and the second end of the second normal phase end input pipe 3 is connected with the second end of the first normal phase end input pipe 11; the charge-discharge module 4, the charge-discharge module 4 is connected with the control ends of the current providing module 2 and the second normal phase end input tube 3 respectively, when the enabling signal of the low-voltage differential voltage stabilizer is high level, the current providing module 2 charges the charge-discharge module 4, and when the enabling signal of the low-voltage differential voltage stabilizer is low level, the charge-discharge module 4 discharges.
Since the charge-discharge module 4 will discharge to zero voltage when the enable signal of the low dropout regulator is at low level, the current supply module 2 charges the charge-discharge module 4 when the enable signal of the low dropout regulator is at high level, and the voltage of the charge-discharge module 4 (i.e. the voltage of the control terminal of the second non-inverting terminal input tube 3) will gradually increase from zero voltage. Further, when the control terminal voltage of the second normal phase terminal input tube 3 is smaller than the control terminal voltage of the first normal phase terminal input tube 11, the second normal phase terminal input tube 3 is turned on, the first normal phase terminal input tube 11 is in an off state, the output voltage of the low-dropout voltage regulator follows the control terminal voltage of the second normal phase terminal input tube 3, and when the control terminal voltage of the second normal phase terminal input tube 3 is larger than the control terminal voltage of the first normal phase terminal input tube 11, the first normal phase terminal input tube 11 is turned on, the second normal phase terminal input tube 3 is in an off state, and the output voltage of the low-dropout voltage regulator follows the control terminal voltage of the first normal phase terminal input tube 11. The output voltage of the low dropout voltage regulator is gradually increased from zero voltage to required voltage, the overshoot of the output voltage of the low dropout voltage regulator is avoided, and the stability of the output voltage of the low dropout voltage regulator is improved.
Specifically, the low dropout regulator 1 may be configured by any existing low dropout regulator that outputs a high voltage when the enable signal is pulled up, such as the low dropout regulator shown in fig. 1.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the current providing module 2 may include: the source end of the first PMOS tube P1 is connected with a power supply of the low-dropout voltage regulator; the second PMOS tube P2 is arranged in a mirror image manner with the first PMOS tube P1 (the source end of the second PMOS tube P2 is connected with the power supply of the low-dropout voltage regulator, the gate end of the second PMOS tube P2 is connected with the gate end of the first PMOS tube P1), and the drain end of the second PMOS tube P2 is respectively connected with the charge-discharge module 4 and the control end of the second positive-phase end input tube 3; the first end of the first switching device 21 is connected with a power supply of the low-dropout voltage regulator, the second end of the first switching device 21 is respectively connected with the control end of the first PMOS tube P1 and the control end of the second PMOS tube P2, the control end of the first switching device 21 receives an enable signal EN of the low-dropout voltage regulator, when the enable signal EN of the low-dropout voltage regulator is at a low level, the first switching device 21 is turned on, and when the enable signal EN of the low-dropout voltage regulator is at a high level, the first switching device 21 is turned off; a current source I1; the second switching device 22, the first end of the second switching device 22 is connected with the drain end of the first PMOS transistor P1, the second end of the second switching device 22 is connected with the current source I1, the second switching device 22 receives the enable inverse signal ENb of the low dropout voltage regulator, when the enable inverse signal ENb of the low dropout voltage regulator is at a low level, the second switching device 22 is turned on, and when the enable inverse signal ENb of the low dropout voltage regulator is at a high level, the second switching device 22 is turned off.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the first switching device 21 may include: the source end of the third PMOS tube P3 is connected with the power supply of the low-dropout voltage regulator, the drain end of the third PMOS tube P3 is respectively connected with the control end of the first PMOS tube P1 and the control end of the second PMOS tube P2, and the control end of the third PMOS tube P3 receives an enable signal EN of the low-dropout voltage regulator.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the second switching device 22 may include: and the source end of the fourth PMOS tube P4 is connected with the drain end of the first PMOS tube P1, the drain end of the fourth PMOS tube P4 is connected with the first current source I1, and the control end of the fourth PMOS tube P4 receives an enable inverse signal ENb of the low-dropout voltage regulator.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the second normal phase side input pipe 3 may include: the source end of the fifth PMOS tube P5 is connected with the first end of the first positive end input tube 11, the drain end of the fifth PMOS tube P5 is connected with the second end of the first positive end input tube 11, and the control end of the fifth PMOS tube P5 is connected with the charge-discharge module 4. At this time, the first normal-phase input pipe 11 may be the sixth PMOS pipe P6.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the charge and discharge module 4 may include: the capacitor sub-module 41, one end of the capacitor sub-module 41 is connected with the control ends of the current supply module 2 and the second positive end input tube 3 respectively; the third switching device 42, the first end of the third switching device 42 is connected with one end of the capacitor sub-module 41, the second end of the third switching device 42 is connected with the other end of the capacitor sub-module 41, the control end of the third switching device 42 receives the enable inverse signal ENb of the low dropout voltage regulator, when the enable inverse signal ENb of the low dropout voltage regulator is at a high level, the third switching device 42 is turned on, the capacitor sub-module 41 discharges, when the enable inverse signal ENb of the low dropout voltage regulator is at a low level, the third switching device 42 is turned off, and the capacitor sub-module 41 charges with a certain slope. The slope is determined by the current provided by the current providing module 2 and the capacitance value of the capacitance sub-module 41. In fig. 4, the capacitor sub-module 41 may be constituted by a capacitor C.
Alternatively, referring to fig. 4, in one embodiment of the present invention, the third switching device 42 may include:
the drain end of the NMOS tube N1 is connected with one end of the capacitor sub-module 41, the source end of the NMOS tube N1 is connected with the other end of the capacitor sub-module 41, and the control end of the NMOS tube N1 receives an enable inverse signal ENb of the low dropout voltage regulator.
Alternatively, in one embodiment of the invention, referring to fig. 4, the capacitive sub-module 41 may comprise a tunable capacitor. By adjusting the capacitance of the capacitance sub-module 41, the charging speed and the discharging speed of the charging and discharging module 4 can be adjusted, so as to adjust the time when the voltage v_ramp of the control terminal of the second positive terminal input tube 3 rises from zero voltage to the voltage v_ref of the control terminal of the first positive terminal input tube 11, i.e. to adjust the rise time T of the output voltage v_out of the low dropout regulator.
Optionally, in one embodiment of the present invention, the current of the current source I1 is adjustable in magnitude. In this way, the charging speed of the charging and discharging module 4 can be adjusted, so as to adjust the time for the voltage v_ramp of the control terminal of the second positive terminal input tube 3 to rise from zero voltage to the voltage v_ref of the control terminal of the first positive terminal input tube 11, i.e. to adjust the rise time T of the output voltage v_out of the low dropout regulator.
In summary, the working principle of the low dropout regulator in fig. 4 for preventing the output voltage from overshooting is as follows: when the enable signal EN of the low dropout voltage regulator jumps to a high level, the first PMOS tube P1, the second PMOS tube P2 and the fourth PMOS tube P4 are connected, and the third PMOS tube P3 and the NMOS tube N1 are disconnected. At this time, the current flowing through the first PMOS transistor P1 is equal to the current provided by the current providing module 2, the current flowing through the second PMOS transistor P2 is a mirror image of the current flowing through the first PMOS transistor P1, the second PMOS transistor P2 charges the capacitor C, the control terminal voltage v_ramp of the fifth PMOS transistor P5 increases from zero voltage with a certain slope, and when the control terminal voltage v_ramp of the fifth PMOS transistor P5 is smaller than the control terminal voltage v_ref of the sixth PMOS transistor P6, the fifth PMOS transistor P5 is turned on, the sixth PMOS transistor P6 is turned off, and the output voltage v_out of the low dropout regulator follows the control terminal voltage v_ramp of the fifth PMOS transistor P5 as shown in fig. 5. As shown in fig. 5, when the control terminal voltage v_ramp of the fifth PMOS transistor P5 is greater than the control terminal voltage v_ref of the sixth PMOS transistor P6, the fifth PMOS transistor P5 is turned off, the sixth PMOS transistor P6 is turned on, and the output voltage v_out of the low dropout regulator follows the control terminal voltage v_ref of the sixth PMOS transistor P6. The above process eliminates the problem of the output voltage being fluctuated when the enable signal EN is pulled high.
The embodiment of the invention has the following advantages: by adding the current providing module, the second normal phase end input tube and the charge-discharge module in the low-voltage differential voltage stabilizer and arranging the first end of the second normal phase end input tube connected with the first end of the first normal phase end input tube in the low-voltage differential voltage stabilizer, the second end of the second normal phase end input tube is connected with the second end of the first normal phase end input tube, the charging and discharging module is connected with the current providing module and the control end of the second normal phase end input tube respectively, when the enabling signal of the low-voltage difference voltage stabilizer is in a high level, the current providing module provides current, the charging and discharging module is charged by the current providing module, and when the enabling signal of the low-voltage difference voltage stabilizer is in a low level, the charging and discharging module discharges to zero voltage. Thus, when the enable signal of the low dropout voltage regulator is at a high level, the current supply module charges the charge/discharge module, and the voltage of the charge/discharge module (i.e., the voltage of the control terminal of the second non-inverting terminal input tube) gradually increases from zero voltage. When the control end voltage of the second normal phase end input tube is smaller than the control end voltage of the first normal phase end input tube, the second normal phase end input tube is conducted, the first normal phase end input tube is in an off state, the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the second normal phase end input tube, namely when the control end voltage of the second normal phase end input tube is larger than the control end voltage of the first normal phase end input tube, the first normal phase end input tube is conducted, the second normal phase end input tube is in an off state, and the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the first normal phase end input tube. The output voltage of the low dropout voltage regulator is gradually increased from zero voltage to required voltage, the overshoot of the output voltage of the low dropout voltage regulator is avoided, and the stability of the output voltage of the low dropout voltage regulator is improved.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail a low dropout regulator provided by the present invention, and specific examples have been used herein to illustrate the principles and embodiments of the present invention, the above examples being provided only to assist in understanding the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (9)
1. The utility model provides a low dropout voltage regulator, its characterized in that, low dropout voltage regulator includes low dropout voltage regulator module, low dropout voltage regulator module includes first normal phase end input tube, low dropout voltage regulator still includes:
a current providing module, which provides current when the enable signal of the low dropout voltage regulator is at a high level;
the first end of the second normal phase end input pipe is connected with the first end of the first normal phase end input pipe, and the second end of the second normal phase end input pipe is connected with the second end of the first normal phase end input pipe; when the control end voltage of the second normal phase end input tube is smaller than the control end voltage of the first normal phase end input tube, the second normal phase end input tube is conducted, the first normal phase end input tube is in an off state, the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the second normal phase end input tube, namely when the control end voltage of the second normal phase end input tube is larger than the control end voltage of the first normal phase end input tube, the first normal phase end input tube is conducted, the second normal phase end input tube is in an off state, and the output voltage of the low-voltage differential voltage stabilizer follows the control end voltage of the first normal phase end input tube;
and the charge-discharge module is respectively connected with the current supply module and the control end of the second normal phase end input tube, when the enabling signal of the low-voltage-difference voltage stabilizer is in a high level, the current supply module charges the charge-discharge module, and when the enabling signal of the low-voltage-difference voltage stabilizer is in a low level, the charge-discharge module discharges.
2. The low dropout voltage regulator according to claim 1, wherein said current supply module includes:
the source end of the first PMOS tube is connected with the power supply of the low-dropout voltage regulator;
the second PMOS tube is arranged in a mirror image mode with the first PMOS tube, and the drain end of the second PMOS tube is connected with the charge-discharge module and the control end of the second positive-phase end input tube respectively;
the first end of the first switching device is connected with a power supply of the low-dropout voltage regulator, the second end of the first switching device is respectively connected with the control end of the first PMOS tube and the control end of the second PMOS tube, the control end of the first switching device receives an enabling signal of the low-dropout voltage regulator, and when the enabling signal of the low-dropout voltage regulator is in a low level, the first switching device is conducted;
a current source;
the first end of the second switching device is connected with the drain end of the first PMOS tube, the second end of the second switching device is connected with the current source, the second switching device receives the enabling inverse signal of the low-dropout voltage regulator, and when the enabling inverse signal of the low-dropout voltage regulator is in a low level, the second switching device is conducted.
3. The low dropout regulator according to claim 2, wherein said first switching device comprises:
the source end of the third PMOS tube is connected with the power supply of the low-dropout voltage regulator, the drain end of the third PMOS tube is respectively connected with the control end of the first PMOS tube and the control end of the second PMOS tube, and the control end of the third PMOS tube receives the enabling signal of the low-dropout voltage regulator.
4. The low dropout regulator according to claim 2, wherein said second switching device includes:
and the source end of the fourth PMOS tube is connected with the drain end of the first PMOS tube, the drain end of the fourth PMOS tube is connected with the current source, and the control end of the fourth PMOS tube receives the enable inverse signal of the low-dropout voltage regulator.
5. The low dropout regulator according to claim 2, wherein said second normal phase side input pipe comprises:
and the source end of the fifth PMOS tube is connected with the first end of the first normal phase end input tube, the drain end of the fifth PMOS tube is connected with the second end of the first normal phase end input tube, and the control end of the fifth PMOS tube is connected with the charge-discharge module.
6. The low dropout regulator according to claim 2, wherein a current of the current source is adjustable in magnitude.
7. The low dropout regulator according to claim 1, wherein said charge and discharge module includes:
one end of the capacitor sub-module is connected with the control ends of the current supply module and the second normal phase end input tube respectively;
and the first end of the third switching device is connected with one end of the capacitor sub-module, the second end of the third switching device is connected with the other end of the capacitor sub-module, the control end of the third switching device receives the enable inverse signal of the low-dropout voltage regulator, when the enable inverse signal of the low-dropout voltage regulator is at a high level, the third switching device is conducted, and when the enable inverse signal of the low-dropout voltage regulator is at a low level, the third switching device is disconnected.
8. The low dropout voltage regulator according to claim 7, wherein said capacitance submodule includes an adjustable capacitor.
9. The low dropout regulator according to claim 7, wherein said third switching device comprises:
the drain end of the NMOS tube is connected with one end of the capacitor sub-module, the source end of the NMOS tube is connected with the other end of the capacitor sub-module, and the control end of the NMOS tube receives the enable inverse signal of the low-dropout voltage regulator.
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| TWI300170B (en) * | 2005-09-13 | 2008-08-21 | Ind Tech Res Inst | Low-dropout voltage regulator |
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