CN109002257B - Data distribution optimization method based on variable scratch pad memory - Google Patents
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention relates to a data distribution optimization method based on a variable scratch pad memory, and belongs to the technical field of computer storage. The method comprises the following steps: s1: dividing the program into a plurality of program segments according to the access characteristics of the application program, and then counting the variable access information of each program segment by utilizing the profiling technology; s2: dynamically adjusting the number of units of a single-layer storage mode and a multi-layer storage mode in the variable scratch pad memory according to variable access information of the program fragment, and searching the optimal configuration of the size of the SLC/MLC in the variable scratch pad memory; s3: based on the size configuration of the given SLC/MLC, an optimal storage address is allocated to each variable in the program segment by using a data distribution optimization algorithm; s4: and adding a corresponding data distribution optimization program before each program segment, and running the program in the system. The invention realizes the variable scratch pad memory and reduces the access energy consumption of the embedded system.
Description
Technical Field
The invention belongs to the technical field of computer storage, and relates to a data distribution optimization method based on a variable scratch pad memory.
Background
A Scratch Pad Memory (SPM) is a software-controlled on-chip Memory intended to replace hardware-controlled caches in embedded systems. Due to its outstanding advantages in low latency, low power consumption and small volume, scratchpad memory is widely used in embedded system designs, such as Altera Nios II and Xilinx MicroBlaze processors. However, the conventional SPM consists of SRAM, where leakage power consumption occupies 30% -50% of the total memory energy on average, increasing the consumption of limited energy of the embedded system. Therefore, a new type of nonvolatile memory is needed to replace the SRAM in the SPM, so as to reduce the power consumption and improve the performance of the embedded system.
The new generation of non-volatile memory technology has moved from the prototype design stage to the production stage, such as Phase Change Memory (PCM), spin torque transfer memory (STT-RAM), resistive random access memory (ReRAM), and memristor, due to the advantages of high speed processing capability of the memory, large capacity of the external memory, persistent storage, ultra-low static power consumption, etc. Wherein the storage mode of typical NVM, such as STT-RAM and PCM, can be dynamically switched between SLC mode and MLC mode. NVM cells in MLC mode can store multiple bits of data to facilitate high density memory chips in limited resource embedded systems. Nevertheless, its latency is higher and the access energy overhead is larger compared to SLC mode. Therefore, a scratch pad memory based on a variable NVM needs to be constructed by combining the advantages of two storage modes in the NVM to optimize the performance and power consumption of the embedded system.
Although there have been many studies to make use of the complementary advantages of the non-volatile memory SLC/MLC in access performance and storage density to break through the storage bottleneck. With the help of hardware technology, a hardware monitor is first proposed to collect the memory requirement and dynamically adjust the number of bits in the memory unit. Meanwhile, in order to determine the optimal SLC/MLC size configuration, various software techniques are proposed to periodically track access information of programs or memory pages. Combining the advantages of SLC mode and MLC mode, these prior art techniques dynamically adjust the storage mode of NVM cells according to different workloads in the system to achieve a balance between capacity and access latency. However, all the above operations are proposed at the level of system memory to replace the conventional DRAM, and cannot be effectively applied to the SPM. Therefore, the invention provides a corresponding optimization scheme based on the variable SPM, so as to fully utilize the advantages of different storage modes of the NVM to improve the system performance and reduce the energy consumption of the NVM.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a data distribution optimization method based on a variable scratch pad memory, which dynamically changes the size configuration of the SLC/MLC SPM according to different workloads in a program, and generates corresponding data allocation for the corresponding configuration, so as to improve the performance of an embedded system and reduce the energy consumption thereof. This process is like the theory of thermal expansion and contraction, i.e., the volume of a substance (i.e., the size of the SPM) changes with changes in temperature (workload).
In order to achieve the purpose, the invention provides the following technical scheme:
a data distribution optimization method based on a variable scratch pad Memory is characterized in that the variable Scratch Pad Memory (SPM) based on the variable non-volatile Memory is constructed by means of the characteristic that the variable non-volatile Memory can be dynamically adjusted between a single-layer storage mode and a multi-layer storage mode, and then a corresponding data distribution optimization method is proposed, and the method specifically comprises the following steps:
s1: dividing the program into a plurality of program segments according to the access characteristics of the application program, and then counting the variable access information of each program segment by utilizing the profiling technology;
s2: before each program segment is executed, dynamically adjusting the number of units in a single-layer storage mode and a multi-layer storage mode in the variable scratch pad memory according to variable access information of the program segment, and searching the optimal configuration of the size of the SLC/MLC in the variable scratch pad memory;
s3: based on the size configuration of the given SLC/MLC, an optimal storage address is allocated to each variable in a program segment by using a data distribution optimization algorithm, and the minimization of the system access energy consumption is realized;
s4: in the process of program compiling, a corresponding data distribution optimization program is added before each program segment, and the program is operated in the system so as to reduce the energy consumption of system access.
Further, in the step S2, the searching for the optimal configuration of SLC/MLC size in the variable scratch pad specifically includes the following steps:
s21: assume that the number of variable scratch pad SPM units is NspmIf the initial state of all the cells is single-level cell SLC, then the initial size of SLC SPM is SS-NspmThe initial size of MLC SPM is SM ═ 0;
s22: calling the data distribution optimization algorithm in the step S3 to obtain a data distribution scheme with the minimum access and storage energy overhead and the energy overhead thereof, and recording;
s23: converting one SLC unit into MLC unit, the size of SLC SPM is SS-1, then calculating the size SM of MLC SPM according to the number of SLC unitsspm-SS) × d, where d is the number of bits of one MLC cell, repeating steps S22 and S23 until the size of the variable scratch pad cell SLC is equal to zero;
s24: and selecting the SLC/MLC size configuration with the minimum access energy overhead as the optimal SLC/MLC configuration of the program segment.
Further, in step S3, the data distribution optimization algorithm specifically includes the following steps:
s31: establishing a ternary array E [ i, SS, SM ], and recording the minimum energy consumption overhead after the ith variable is stored when the residual space size of the SLC SPM and the MLC SPM is SS and SM;
s32: assuming that all variables of a program fragment are first stored in a Dynamic Random Access Memory (DRAM), then: e [ i, ss, sm]=∑i=1ed(di)+EcWherein e isd(di) Represents the variable diAccess energy stored in memory, EcRepresenting the SLC/MLC size configuration based on the previous program segment, and the conversion energy consumption generated under the configuration condition of the SLC/MLC of the program segment;
s33: a recursive relationship of the data allocation is established,
E[i,ss,sm]=min(E[i-1,ss,sm]+edm(di),
E[i-1,ss-size(i),sm]+es(di)+esm(di)-ed(di),
E[i-1,ss,sm-size(i)]+em(di)+emm(di)-ed(di))
wherein size (i) is the size of variable i, ed(di) Storing access energy in DRAM for data i, edm(di) For migration energy of data i into DRAM, es(di) Storing access energy in SLC SPM for data i, esm(di) For migration energy of data i into SLC SPM, em(di) Access energy, em, stored in MLC SPM for data im(di) Migration energy of data i into MLC SPM;
s34: the optimal data distribution scheme and its energy consumption overhead are obtained by program recursion.
The invention has the beneficial effects that: the invention combines the advantages of the novel nonvolatile memory in scalability, realizes the variable scratch pad memory, dynamically configures the size of the SLC/MLC in the memory according to the access characteristics of the program, and allocates the optimal memory address for each variable by combining the access information of the program variable, so as to fully exert the advantages of the SLC/MLC in access performance and memory density and reduce the access energy consumption of the embedded system.
Drawings
In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
FIG. 1 is a hardware model of the variable scratch pad memory of the present invention;
FIG. 2 is a flow chart of SLC/MLC size configuration in variable scratch pad according to the present invention;
FIG. 3 is a flow chart of data distribution optimization of the program segments according to the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The invention discloses a data distribution optimization method based on a variable scratch pad memory, which specifically comprises the following steps:
s1: dividing the program into a plurality of program segments according to the access characteristics of the application program, and then counting the variable access information of each program segment by utilizing the profiling technology;
s2: before each program segment is executed, dynamically adjusting the number of units in a single-layer storage mode and a multi-layer storage mode in the variable scratch pad memory according to variable access information of the program segment, and searching the optimal configuration of the size of the SLC/MLC in the variable scratch pad memory;
s3: based on the size configuration of the given SLC/MLC, an optimal storage address is allocated to each variable in a program segment by using a data distribution optimization algorithm, and the minimization of the system access energy consumption is realized;
s4: in the process of program compiling, a corresponding data distribution optimization program is added before each program segment, and the program is operated in the system so as to reduce the energy consumption of system access.
FIG. 1 is a hardware model of the variable scratchpad memory, as shown in FIG. 1, a conventional hardware-controlled cache is replaced by a variable SPM, and then a corresponding data distribution optimization method is proposed under the architecture. First, the program is divided into a plurality of program fragments as shown in table 1. The division of the program fragments may be according to program points: 1) the beginning and end of each internal program; 2) the beginning and end of each cycle. Then, according to the divided program segments, the number and the size of variables in each program segment are counted by using a static analysis technology (profiling) of the program, and the number of times of read-write operations of each variable is recorded. Secondly, the variable scratch pad memory SLC size and MLC size are dynamically configured according to the information of the respective clip variables of the program. And finally, dynamically allocating address space for the variables of each program segment, and minimizing the access energy overhead of the whole program as much as possible.
TABLE 1 program division into program segments
As shown in fig. 2, before each program segment is executed, the number of cells in the single-layer storage mode and the multi-layer storage mode in the variable scratch pad is dynamically adjusted according to the variable information of the program segment, and the optimal configuration of the SLC/MLC size in the variable scratch pad is searched: the flow starts at step 201.
In step 202, the total number of segments m, the total number of variables N, the size (i) of the variable i, and the total number of SPM units N in a given program are inputspmThe spatial size of an MLC cell is d.
In step 203, two arrays are constructed to respectively record the size ss (h) of the SLC SPM in the segment h, and the distribution condition R (h, i) of the variable i in the segment h, wherein if the variable i in the segment h is in the DRAM, R (h, i) ═ 0; if variable i is in SLC SPM, then R (h, i) is 1, if variable i is in MLC SPM, then R (h, i) is 2;
in step 204, it is determined whether there is a next program fragment h (h < m), if so, step 205 is executed, otherwise, step 212 is executed.
In step 205, switch to the next program segment h ═ h +1, and then initialize all SPM units to SLC modeOf the formula, i.e. SS ═ Nspm,SM=(Nspm-SS). times.d. Where SS represents the size of SLC SPM and SM represents the size of MLC SPM.
In step 206, the lowest energy cost OE is initialized to a maximum inf (OE ═ inf). Where OE stores program segment h, looping to the energy overhead of the known optimal allocation scheme under this SLC/MLC size configuration.
In step 207, the local data distribution optimization algorithm in step S3 is called, SS, SM, R (h, i), n, size (i) is inputted, and the variable allocation mode with the lowest energy cost of program segment h under the SLC/MLC size configuration and the lowest energy cost are returned and recorded in temporary variables R (i) and oe, respectively. Where r (i) indicates the program segment h, the allocation location of the variable i in this SLC/MLC size configuration, and when the variable i is in the DRAM, r (i) is 0; if the variable i is in SLC SPM, then r (i) is 1; if the variable i is in MLC SPM, then r (i) ═ 2, oe denotes the program segment h, with the lowest energy overhead at this SLC/MLC size configuration.
In step 208, it is determined whether the energy OE is smaller than the stored minimum energy OE (OE < OE), if yes, step 209 is performed, otherwise, step 211 is performed.
In step 209, the lowest energy cost OE is recorded as OE, OE ═ OE, SLC/MLC size allocation SS is recorded, (h) ═ SS, and the data allocation pattern R (h, i) ═ R (i) of the program segment h is recorded, i ∈ [1, n ].
In step 210, the next SLC/MLC size configuration is switched, SS-1 and SM (N)spm-SS)×d。
In step 211, it is determined whether the SLC/MLC size configuration is legal, i.e. determined (SS > -0), if yes, step 207 is executed, otherwise, step 204 is executed.
In step 212, the optimal configuration of SLC/MLC size in each program segment, the assignment R (h, i) of each variable in each program segment is output.
In step 213, the flow ends.
As shown in fig. 3, in the above step S3, based on the given SLC/MLC size configuration, an optimal memory address is allocated to each variable in the program segment to achieve minimization of system access energy consumption, this time, the solution is named as a local data distribution optimization algorithm, and the local data distribution optimization algorithm is further described with reference to fig. 3:
the flow begins at step 301;
in step 302, for a given program segment, the total number n of data, the size (i) of data i, and the energy e for interconversion between SLC and MLC are inputcThe number of MLC SPMs is SM, the number of SLC SPMs is SS, and R;
in step 303, a ternary array E [ i, ss, sm ] is established to record the minimum energy consumption overhead after the ith variable is stored when the size of the remaining space of the SLC SPM and MLC SPM is ss, sm;
assuming that all variables of the program fragment are first stored in a Dynamic Random Access Memory (DRAM), in step 304: e [ i, ss, sm]=∑i=1de(id)+cE, wherein Ed(di) Represents the variable diAccess energy stored in memory, EcRepresenting the SLC/MLC size configuration based on the previous program segment, and the conversion energy consumption generated under the configuration condition of the SLC/MLC of the program segment;
in step 305, the ternary array values are corrected using the dynamic programming concept, a recurrence relation of data allocation is established,
E[i,ss,sm]=min(E[i-1,ss,sm]+edm(di),
E[i-1,ss-size(i),sm]+es(di)+esm(di)-ed(di),
E[i-1,ss,sm-size(i)]+em(di)+emm(di)-ed(di))
wherein e isd(di) Storing access energy in DRAM for data i, edm(di) For migration energy of data i into DRAM, es(di) Storing access energy in SLC SPM for data i, esm(di) For migration energy of data i into SLC SPM, em(di) Access energy, em, stored in MLC SPM for data im(di) Migration energy from the data i to the MLC SPM is obtained (specific migration energy consumption can be obtained by comparing original storage positions of the variables (storage information of the variables is stored in an array R);
in step 306, selecting the minimum energy consumption of the ternary array under the condition that i is equal to n, recording the data distribution condition, and outputting;
at step 307, the algorithm ends.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (2)
1. A data distribution optimization method based on a variable scratch pad memory is characterized by specifically comprising the following steps of:
s1: dividing the program into a plurality of program segments according to the access characteristics of the application program, and then counting the variable access information of each program segment by utilizing the profiling technology;
s2: before each program segment is executed, dynamically adjusting the number of units of a Single-layer storage mode and a Multi-layer storage mode in a variable scratch pad memory according to variable access information of the program segment, and searching the optimal configuration of the sizes of Single-layer cells (SLC)/Multi-layer cells (MLC) in the variable scratch pad memory;
s3: based on the size configuration of the given SLC/MLC, an optimal storage address is allocated to each variable in a program segment by using a data distribution optimization algorithm, and the minimization of the system access energy consumption is realized;
s4: in the process of program compiling, adding a corresponding data distribution optimization program before each program segment, and running the program in the system to reduce the energy consumption of system access;
in step S2, the step of searching for the optimal SLC/MLC size configuration in the variable scratch pad memory for each program fragment specifically includes the steps of:
s21: assume that the number of variable scratch pad SPM units is NspmIf the initial state of all the cells is single-level cell SLC, then the initial size of SLC SPM is SS-NspmThe initial size of MLC SPM is SM ═ 0;
s22: calling the data distribution optimization algorithm in the step S3 to obtain a data distribution scheme with the minimum access and storage energy overhead and the energy overhead thereof, and recording;
s23: converting one SLC unit into MLC unit, the size of SLC SPM is SS-1, then calculating the size SM of MLC SPM according to the number of SLC unitsspm-SS) × d, where d is the number of bits of one MLC cell, repeating steps S22 and S23 until the size of the variable scratch pad cell SLC is equal to zero;
s24: and selecting the SLC/MLC size configuration with the minimum access energy overhead as the optimal SLC/MLC configuration of the program segment.
2. The variable scratchpad-memory-based data distribution optimization method as claimed in claim 1, wherein in step S3, the data distribution optimization algorithm specifically comprises the following steps:
s31: establishing a ternary array E [ i, ss, sm ], and recording the minimum energy consumption overhead after the ith variable is stored when the residual space size of the SLC SPM and the MLC SPM is ss and sm;
s32: assuming that all variables of a program fragment are first stored in a Dynamic Random Access Memory (DRAM), then: e [ i, ss, sm]=∑i=1ed(di)+EcWherein e isd(di) Represents the variable diAccess energy stored in memory, EcRepresenting the SLC/MLC size configuration based on the previous program segment, and the conversion energy consumption generated under the configuration condition of the SLC/MLC of the program segment;
s33: a recursive relationship of the data allocation is established,
E[i,ss,sm]=min(E[i-1,ss,sm]+edm(di),
E[i-1,ss-size(i),sm]+es(di)+esm(di)-ed(di),
E[i-1,ss,sm-size(i)]+em(di)+emm(di)-ed(di))
wherein size (i) is the size of variable i, ed(di) Storing access energy in DRAM for data i, edm(di) For migration energy of data i into DRAM, es(di) Storing access energy in SLC SPM for data i, esm(di) For migration energy of data i into SLC SPM, em(di) Access energy, em, stored in MLC SPM for data im(di) Migration energy of data i into MLC SPM;
s34: the optimal data distribution scheme and its energy consumption overhead are obtained by program recursion.
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《便笺存储嵌入式系统中多层存储上的数据分配算法研究》;张骏;《中国优秀硕士学位论文全文数据库》;20140715(第7期);I137-22 * |
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