CN111290706A - Double-layer read-write wear balancing method based on bloom filter - Google Patents
Double-layer read-write wear balancing method based on bloom filter Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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Abstract
The invention discloses a double-layer read-write wear balancing method based on a bloom filter, and relates to a wear balancing method of a hybrid memory controller. The invention aims to solve the problem that the space overhead of the existing table wear leveling algorithm is large. The invention applies the counting bloom filter to the design of the memory controller, and represents the time locality of the memory access program by dynamically changing the threshold value of the read-write bloom filter. Meanwhile, the reading and writing heat degree of the page is judged by comparing the numerical value in the reading and writing bloom filter with the dynamic threshold value. The highly-worn page and the slightly-worn page of the hybrid memory are exchanged, so that the effect of balanced overall wear of the hybrid memory is achieved, and the overall service life of a hybrid memory system is prolonged. The method is used for the field of wear leveling control of the hybrid memory.
Description
Technical Field
The invention relates to a wear leveling method for a hybrid memory controller.
Background
In order to meet the requirements of modern embedded systems for large capacity and low power consumption of memory, hybrid memories composed of DRAM and non-volatile memory are widely used. Phase change memory pcm (phased change memory) has become a new favorite in the academic and industrial sectors. Compared with the traditional DRAM, the PCM persistent memory has the advantages of low static power, high storage density, capability of addressing by bytes, high data endurance and the like, and the advantages bring huge challenges and opportunities to the high-efficiency performance of the memory. Despite the numerous advantages of PCM, its high write latency and low write endurance limit the service life of PCM. In the hybrid main memory design of PCM and DRAM, how to improve the service life of PCM in the parallel hybrid architecture becomes a current research focus. Wear leveling algorithms are a widely adopted method for improving hybrid memory endurance. The wear leveling technology uniformly writes the unbalanced write access of the upper layer back to the bottom physical unit after remapping, and avoids that some memory lines wear through in advance due to overhigh write times, thereby prolonging the service life of the hybrid memory system. Wear leveling needs to address the lifetime issues of hybrid memory systems under malicious attacks and normal loads. For hybrid memories, current wear leveling algorithms are classified into table-based wear leveling algorithms and algebraic-based wear leveling algorithms. The wear leveling algorithm based on the table uses an address mapping table to record the corresponding relation between the logical address and the physical address, and periodically exchanges areas with higher and lower writing times, so as to achieve the purpose of wear leveling. The algebraic wear leveling algorithm uses an algebraic function to randomly remap the logical addresses to physical space with low space overhead, and can be executed within the memory controller or chip. However, an algebraic wear-leveling algorithm generally faces the problem of inaccurate wear prediction, and the algorithm can only exchange pages in a global rotation mode and does not perform special wear-leveling processing on certain pages with high heat of writing in a targeted mode. Therefore, it is very necessary to provide a hybrid memory wear leveling algorithm with low overhead and high prediction rate.
Disclosure of Invention
The invention aims to solve the problem that the time and space overhead of the existing table wear leveling algorithm is high, and provides a double-layer read-write wear leveling method based on a bloom filter.
A bloom filter-based double-layer read-write wear leveling method comprises the following specific processes:
step 1, adding 1 to a request _ counter when an operation accesses a page P;
if the current operation is a write operation, adding 1 to the corresponding position of the write _ counting _ bloom _ filter through two hash functions, and entering the step 2;
if the current operation is a read operation, adding 1 to the corresponding position of the read _ counting _ bloom _ filter through two hash functions, and entering step 3;
the request _ counter is a memory access request counter;
the write _ counting _ bloom _ filter is a write bloom filter, and the read _ counting _ bloom _ filter is a read bloom filter;
in time T, regarding the page which is subjected to the current write operation and has two hash functions with the value of the corresponding position of the write _ counting _ block _ filter [ i ] and the value of the write _ counting _ block _ filter [ j ] both larger than the PCM _ write _ threshold as the page with more write wear;
in time T, the current reading operation enables the values of the corresponding positions of the two hash function pairs read _ counting _ block _ filter [ i ] and read _ counting _ block _ filter [ j ] to be larger than PCM _ read _ threshold, and the pages of the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], read _ counting _ block _ filter [ j ] and read _ counting _ block _ filter [ j ] are regarded as the pages with less write wear and are read hot pages;
step 2, if the current write operation enables the values of the corresponding positions of the two hash functions to the write _ counting _ bloom _ filter [ i ] and the write _ counting _ bloom _ filter [ j ] to be larger than the PCM _ write _ threshold, exchanging the page with more write wear with the page with less write wear, and entering the step 4; otherwise, entering step 5;
the PCM _ write _ threshold is a phase change memory write threshold;
step 3, if the current read operation causes the values of the corresponding positions of the read _ counting _ block _ filter [ i ] and the read _ counting _ block _ filter [ j ] of the two hash function pairs to be larger than the PCM _ read _ threshold, and the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], the read _ counting _ block _ filter [ j ] > write _ counting _ block _ filter [ j ], the current read operation page is placed in a hot page candidate list, and the step 6 is performed; otherwise, directly entering step 6;
the PCM _ read _ threshold is a phase change memory read threshold;
step 4, taking out the page K stored in the header in the hot page reading candidate list, exchanging the position of the page P and the page K, and entering step 5;
the HRWTH is a maximum write threshold;
step 6, if the PCM _ read _ threshold is greater than HRRTH, halving the PCM _ read _ threshold and halving all record values in the read _ counting _ bloom _ filter, and entering step 8; otherwise, directly entering the step 8;
the HRRTH is a maximum threshold value of the read operation;
step 7, if the request _ counter is an integer multiple of Tupwth, PCM _ write _ threshold + addwrite; otherwise, ending the program;
the Tupwth is a write threshold updating period;
addwrite increases the span for the write threshold;
the Tuprth is a read threshold updating period;
addread increments the span for the read threshold.
The invention has the beneficial effects that:
the invention aims to prolong the service life of a hybrid system memory, designs a memory controller of the hybrid memory, and provides a Double-Layer read-write wear leveling method (DLBF) based on a Bloom Filter, which realizes the wear leveling with proper grain size in a PCM chip under smaller hardware cost and achieves the purpose of wear leveling with smaller space cost.
The experimental result shows that compared with a non-wear equalization algorithm, a random algorithm and a Bloom Filter algorithm, the service life of the hybrid memory system is prolonged to 2.34 times, 1.22 times and 1.02 times of the service life of the hybrid memory system respectively. Meanwhile, the average variance of the write distribution is respectively reduced to 1.04%, 66.27% and 96.97% of a wear-free equalization algorithm, a random algorithm and a Bloom Filter algorithm.
Drawings
FIG. 1 is a diagram of dijkstra load write operation distribution in a wear-free leveling algorithm;
FIG. 2 is a diagram of the distribution of jpeg _ dec load write operations in a wear-free leveling algorithm;
FIG. 3 is a graph of mpeg _ dec load write operation distribution in a no wear leveling algorithm;
FIG. 4 is a diagram of dijkstra load write operation distribution in a DLBF wear leveling algorithm;
FIG. 5 is a graph of the distribution of jpeg _ dec load write operations in a DLBF wear leveling algorithm;
FIG. 6 is a graph of mpeg _ dec load write operation distribution in a DLBF wear leveling algorithm;
FIG. 7 is a graph of the service life of a normalized hybrid memory system in different algorithms, Without WL is a wear-free equalization algorithm, random is a random algorithm, Bloom Filter is a Bloom Filter algorithm, and DLBF is a double-layer Bloom Filter algorithm;
FIG. 8 is a graph of normalized write distribution mean variance.
Detailed Description
The first embodiment is as follows: the method for balancing the double-layer read-write wear based on the bloom filter comprises the following specific processes:
step 1, adding 1 to a request _ counter when an operation accesses a page P;
if the current operation is a write operation, adding 1 to the corresponding position of the write _ counting _ bloom _ filter (the address corresponding to the operation is brought into the hash function, because the hash function is two hash functions, two values i, j are obtained, namely the corresponding position of the bloom filter is determined), and entering step 2;
if the current operation is a read operation, adding 1 to the corresponding position of the read _ counting _ bloom _ filter through two hash functions, and entering step 3;
the request _ counter is a memory access request counter;
the write _ counting _ bloom _ filter is a write bloom filter, and the read _ counting _ bloom _ filter is a read bloom filter;
in time T, regarding the page which is subjected to the current write operation and has two hash functions with the value of the corresponding position of the write _ counting _ block _ filter [ i ] and the value of the write _ counting _ block _ filter [ j ] both larger than the PCM _ write _ threshold as the page with more write wear;
in time T, the current reading operation enables the values of the corresponding positions of the two hash function pairs read _ counting _ block _ filter [ i ] and read _ counting _ block _ filter [ j ] to be larger than PCM _ read _ threshold, and the pages of the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], read _ counting _ block _ filter [ j ] and read _ counting _ block _ filter [ j ] are regarded as the pages with less write wear and are read hot pages;
step 2, if the current write operation enables the values of the corresponding positions of the two hash functions to the write _ counting _ bloom _ filter [ i ] and the write _ counting _ bloom _ filter [ j ] to be larger than the PCM _ write _ threshold, exchanging the page with more write wear with the page with less write wear, and entering the step 4; otherwise (the current page is not a page with much writing wear), the step 5 is carried out;
the PCM _ write _ threshold is a phase change memory write threshold;
step 3, if the current read operation causes the values of the corresponding positions of the read _ counting _ block _ filter [ i ] and the read _ counting _ block _ filter [ j ] of the two hash function pairs to be larger than the PCM _ read _ threshold, and the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], the read _ counting _ block _ filter [ j ] > write _ counting _ block _ filter [ j ], the current read operation page is placed in a hot page candidate list, and the step 6 is performed; otherwise, directly entering step 6;
the PCM _ read _ threshold is a phase change memory read threshold;
step 4, taking out the page K stored in the header in the hot page reading candidate list, exchanging the position of the page P and the page K, and entering step 5;
the HRWTH is a maximum write threshold;
step 6, if the PCM _ read _ threshold is greater than HRRTH, halving the PCM _ read _ threshold and halving all record values in the read _ counting _ bloom _ filter, and entering step 8; otherwise, directly entering the step 8;
the HRRTH is a maximum threshold value of the read operation;
step 7, if the request _ counter is an integer multiple of Tupwth, PCM _ write _ threshold + addwrite; otherwise, ending the program;
the Tupwth is a write threshold updating period;
addwrite increases the span for the write threshold;
the Tuprth is a read threshold updating period;
addread increments the span for the read threshold.
The second embodiment is as follows: the difference between this embodiment and the first embodiment is that the two hash functions in step 1 are respectively
i＝(R1*7+pageNo+1)％bf_size；
j＝(R2*31+pageNo+1)％bf_size；
Wherein, bf _ size is the length of the bloom filter, and the value is 256; pageNo is a special code for each address; r1 and R2 are random numbers.
Other steps and parameters are the same as those in the first embodiment.
The third concrete implementation mode: the difference between this embodiment and the first embodiment is that the time T in step 1 is 10000 memory access requests.
Other steps and parameters are the same as those in the first embodiment.
The fourth concrete implementation mode: in this embodiment, the second or third embodiment is different from the second or third embodiment in that the maximum write threshold in step 5 is 200< HRWTH < 8000.
Other steps and parameters are the same as those in the second or third embodiment.
The fifth concrete implementation mode: the difference between this embodiment and one of the first to the fourth embodiments is that the maximum threshold value 10000< HRRTH <80000 for the read operation in step 6.
Other steps and parameters are the same as in one of the first to fourth embodiments.
The sixth specific implementation mode: this embodiment is different from one of the first to fifth embodiments in that in step 7, the write threshold update period 10000< Tupwth < 80000;
the write threshold increase span is 1 < addwrite < 16.
Other steps and parameters are the same as those in one of the first to fifth embodiments.
The seventh embodiment: the difference between this embodiment and one of the first to sixth embodiments is that the read threshold update period 2000 in step 8<Tuprth<20000；
The read threshold increase span is greater than or equal to 1 and less than or equal to 8.
Other steps and parameters are the same as those in one of the first to sixth embodiments.
The following examples were used to demonstrate the beneficial effects of the present invention:
the first embodiment is as follows:
the invention uses a Gem5-Nvmain system simulator to test 10 common loads, namely bitcount, CRC32, dijkstra, FFT, jpeg _ decoder, jpeg _ encoder, mpeg2_ dec, patricia, qsort and sha, which come from mediabench or Mibench. The detailed simulation configuration of the main memory is listed in table 1.
Table 1: simulation configuration
As shown in FIG. 1, the present invention distributes the write operations in the access process uniformly in the hybrid memory. Compared with the mixed memory write distribution situation without the wear leveling algorithm, when the system runs the three test loads, the DLBF wear leveling algorithm improves the service life of the system by 67.99%, 84.21% and 54.23% respectively. Meanwhile, DLBF reduces the write distribution variance to 7.2%, 0.91% and 1.15% of the wear-free equalization algorithm.
As shown in fig. 2, compared with the wear-free equalization algorithm, random algorithm, and Bloom Filter algorithm, the DLBF of the present invention respectively increases the service life of the hybrid memory system to 2.34 times, 1.22 times, and 1.02 times of those algorithms.
FIG. 3 shows the normalized mean variance of the write distribution in the hybrid memory, DLBF reduces the mean variance of the write distribution to 1.04%, 66.27%, 96.97% of the wear leveling algorithm, random algorithm, Bloom Filter algorithm, respectively.
The present invention is capable of other embodiments and its several details are capable of modifications in various obvious respects, all without departing from the spirit and scope of the present invention.
Claims (7)
1. A double-layer read-write wear balancing method based on a bloom filter is characterized by comprising the following steps: the method comprises the following specific processes:
step 1, adding 1 to a request _ counter when an operation accesses a page P;
if the current operation is a write operation, adding 1 to the corresponding position of the write _ counting _ bloom _ filter through two hash functions, and entering the step 2;
if the current operation is a read operation, adding 1 to the corresponding position of the read _ counting _ bloom _ filter through two hash functions, and entering step 3;
the request _ counter is a memory access request counter;
the write _ counting _ bloom _ filter is a write bloom filter, and the read _ counting _ bloom _ filter is a read bloom filter;
in time T, regarding the page which is subjected to the current write operation and has two hash functions with the value of the corresponding position of the write _ counting _ block _ filter [ i ] and the value of the write _ counting _ block _ filter [ j ] both larger than the PCM _ write _ threshold as the page with more write wear;
in time T, the current reading operation enables the values of the corresponding positions of the two hash function pairs read _ counting _ block _ filter [ i ] and read _ counting _ block _ filter [ j ] to be larger than PCM _ read _ threshold, and the pages of the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], read _ counting _ block _ filter [ j ] and read _ counting _ block _ filter [ j ] are regarded as the pages with less write wear and are read hot pages;
step 2, if the current write operation enables the values of the corresponding positions of the two hash functions to the write _ counting _ bloom _ filter [ i ] and the write _ counting _ bloom _ filter [ j ] to be larger than the PCM _ write _ threshold, exchanging the page with more write wear with the page with less write wear, and entering the step 4; otherwise, entering step 5;
the PCM _ write _ threshold is a phase change memory write threshold;
step 3, if the current read operation causes the values of the corresponding positions of the read _ counting _ block _ filter [ i ] and the read _ counting _ block _ filter [ j ] of the two hash function pairs to be larger than the PCM _ read _ threshold, and the read _ counting _ block _ filter [ i ] > write _ counting _ block _ filter [ i ], the read _ counting _ block _ filter [ j ] > write _ counting _ block _ filter [ j ], the current read operation page is placed in a hot page candidate list, and the step 6 is performed; otherwise, directly entering step 6;
the PCM _ read _ threshold is a phase change memory read threshold;
step 4, taking out the page K stored in the header in the hot page reading candidate list, exchanging the position of the page P and the page K, and entering step 5;
step 5, if PCM _ write _ threshold > HRWTH, PCM _ write _ threshold is halved, all record values in write _ counting _ bloom _ filter are halved, and step 7 is entered; otherwise, directly entering step 7;
the HRWTH is a maximum write threshold;
step 6, if the PCM _ read _ threshold is greater than HRRTH, halving the PCM _ read _ threshold and halving all record values in the read _ counting _ bloom _ filter, and entering step 8; otherwise, directly entering the step 8;
the HRRTH is a maximum threshold value of the read operation;
step 7, if the request _ counter is an integer multiple of Tupwth, PCM _ write _ threshold + addwrite; otherwise, ending the program;
the Tupwth is a write threshold updating period;
addwrite increases the span for the write threshold;
step 8, if the request _ counter is an integral multiple of Tuprth, PCM _ read _ threshold + addread; otherwise, ending the program;
the Tuprth is a read threshold updating period;
addread increments the span for the read threshold.
2. The bloom filter-based double-layer read-write wear leveling method according to claim 1, characterized in that: in the step 1, the two hash functions are respectively
i＝(R1*7+pageNo+1)％bf_size；
j＝(R2*31+pageNo+1)％bf_size；
Wherein, bf _ size is the length of the bloom filter, and the value is 256; pageNo is a special code for each address; r1 and R2 are random numbers.
3. The bloom filter-based double-layer read-write wear leveling method according to claim 1, characterized in that: and the time T in the step 1 is 10000 memory access requests.
4. The bloom filter-based double-layer read-write wear leveling method according to claim 2 or 3, wherein: the maximum threshold for write operation 200< HRWTH <8000 in said step 5.
5. The bloom filter-based double-layer read-write wear leveling method according to claim 4, wherein: the maximum threshold for read operation 10000< HRRTH <80000 in step 6.
6. The bloom filter-based double-layer read-write wear leveling method according to claim 5, wherein: the update cycle of the write threshold value in the step 7 is 10000< Tupwth < 80000;
the write threshold increase span is 1 < addwrite < 16.
7. The bloom filter-based double-layer read-write wear leveling method according to claim 6, wherein: the read threshold update period 2000 of step 8<Tuprth<20000；
The read threshold increase span is greater than or equal to 1 and less than or equal to 8.
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