CN108987486A - A kind of power diode and preparation method thereof - Google Patents
A kind of power diode and preparation method thereof Download PDFInfo
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- CN108987486A CN108987486A CN201810800736.5A CN201810800736A CN108987486A CN 108987486 A CN108987486 A CN 108987486A CN 201810800736 A CN201810800736 A CN 201810800736A CN 108987486 A CN108987486 A CN 108987486A
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 276
- 239000007924 injection Substances 0.000 claims abstract description 276
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 230000026267 regulation of growth Effects 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 31
- 239000004065 semiconductor Substances 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000927 vapour-phase epitaxy Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
The present invention provides a kind of power diode and preparation method thereof, comprising: provides the substrate of the first conduction type；First epitaxial layer of one conduction type of surface growth regulation over the substrate；The buried layer to form the second conduction type is injected in first epitaxial layer upper surface；The second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；The first injection region to form the first conduction type is injected in second epitaxial layer upper surface；Position corresponding with the buried layer forms the second injection region of the second conduction type in second epitaxial layer, and second injection region is connect with the buried layer；The third injection region of the second conduction type is formed positioned at the top of second injection region in second epitaxial layer, second injection region is connect with the third injection region；First electrode is formed in second epitaxial layer upper surface；The second electrode connecting with the substrate is formed in the lower surface of the substrate, to reduce on-state voltage drop, improves breakdown voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power diode and preparation method thereof.
Background technique
Power diode is the critical component of circuit system, is widely used in high-frequency inverter, digital product, power generation
The various advanced weaponry control systems of the products for civilian use and satellite receiver, guided missile and aircraft etc. such as mechanical, electrical view machine and instrument and meter
The military scenario of equipment.Power diode is just expanded towards two important directions: (1) to several ten million or even up to ten thousand ampere develops,
It can be applied to the occasions such as high-temperature electric arc wind-tunnel, resistance welder；(2) reverse recovery time is shorter and shorter, present to ultrafast, ultra-soft,
Super durable direction is developed, and makes itself to be applied not only to rectification occasion, has different role in various switching circuits.It is low in order to meet
The application requirements such as power consumption, high frequency, high temperature, miniaturization are to its pressure resistance, conducting resistance, unlatching pressure drop, reverse recovery characteristic, high temperature
Characteristic etc. is higher and higher.
Commonly used has common rectifier diode, Schottky diode, PIN diode.Wherein Schottky Rectifier has
There is a lower on-state voltage drop, biggish leakage current, reverse recovery time is almost nil.And the bandwidth of PIN diode, it is reachable
10GHz, but the on-state voltage drop of current PIN diode is higher, therefore, in view of the deficiencies of the prior art, needs one kind that can drop
The power diode of low on-state voltage drop.
Summary of the invention
The present invention is based on the above problems, proposes a kind of power diode and preparation method thereof, can reduce on-state
Pressure drop.
In view of this, on the one hand the embodiment of the present invention proposes a kind of power diode, which includes:
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate；
The buried layer of second conduction type, injection are formed in the upper surface of first epitaxial layer；
Second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
First injection region of the first conduction type, injection are formed in the upper surface of second epitaxial layer, first note
The width for entering area is substantially equal to the width of the buried layer；
Second injection region of the second conduction type is formed in position corresponding with the buried layer in second epitaxial layer
And it is connect with the buried layer；
The third injection region of second conduction type is formed in second epitaxial layer and is located at second injection region
Top, second injection region are connect with the third injection region, and the depth and width of second injection region are greater than described the
The depth and width of three injection regions；
First electrode is formed in the upper surface of second epitaxial layer；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
Further, the doping concentration of first injection region is higher than the doping concentration of the substrate, and the substrate is mixed
Miscellaneous concentration is higher than the doping concentration of first epitaxial layer, and the doping concentration of first epitaxial layer is higher than second epitaxial layer
Doping concentration.
Further, the doping concentration of the buried layer is higher than the doping concentration of the third injection region, the third injection
The doping concentration in area is higher than the doping concentration of second injection region.
Further, the quantity of second injection region is identical as the quantity of the third injection region and the buried layer,
First injection region and third injection region interval are arranged.
Further, first injection region is connect with second injection region part.
On the other hand the embodiment of the present invention provides a kind of production method of power diode, this method comprises:
The substrate of first conduction type is provided；
First epitaxial layer of one conduction type of surface growth regulation over the substrate；
The buried layer to form the second conduction type is injected in first epitaxial layer upper surface；
The second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
The first injection region to form the first conduction type, first injection region are injected in second epitaxial layer upper surface
Width be substantially equal to the width of the buried layer；
Position corresponding with the buried layer forms the second injection region of the second conduction type in second epitaxial layer,
And second injection region is connect with the buried layer；
Top in second epitaxial layer positioned at second injection region forms the third injection of the second conduction type
Area, second injection region are connect with the third injection region, and the depth and width of second injection region are greater than the third
The depth and width of injection region；
First electrode is formed in second epitaxial layer upper surface；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
Further, the doping concentration of first injection region is higher than to the doping concentration of the substrate, by the substrate
Doping concentration be higher than the doping concentration of first epitaxial layer, and the doping concentration of first epitaxial layer is higher than described the
The doping concentration of two epitaxial layers.
Further, the doping concentration of the buried layer is higher than to the doping concentration of the third injection region, and by described the
The doping concentration of three injection regions is higher than the doping concentration of second injection region.
Further, the depth and width of second injection region are specific greater than the depth and width of the third injection region
Include:
Formed the third injection region ion implantation energy and implantation dosage be greater than formed second injection region from
Sub- Implantation Energy and implantation dosage so that the depth and width of second injection region be greater than the third injection region depth and
Width；
The quantity of second injection region and the quantity of the third injection region and the buried layer is corresponding identical；
First injection region and third injection region interval are arranged.
Further, first injection region is connect with second injection region part.
The technical solution of the embodiment of the present invention is by providing the substrate of the first conduction type；Surface is grown over the substrate
First epitaxial layer of the first conduction type；The buried layer to form the second conduction type is injected in first epitaxial layer upper surface；?
First epitaxial layer upper surface forms the second epitaxial layer of the first conduction type；Shape is injected in second epitaxial layer upper surface
At the first injection region of the first conduction type, the width of first injection region is substantially equal to the width of the buried layer；Described
Position corresponding with the buried layer forms the second injection region of the second conduction type, and second injection in second epitaxial layer
Area is connect with the buried layer；Top in second epitaxial layer positioned at second injection region forms the second conduction type
Third injection region, second injection region are connect with the third injection region, and the depth and width of second injection region are greater than
The depth and width of the third injection region；First electrode is formed in second epitaxial layer upper surface；Under the substrate
Surface forms the second electrode connecting with the substrate.The technical solution that the embodiment of the present invention proposes can reduce on-state voltage drop.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the production method for the power diode that one embodiment of the present of invention provides；
Fig. 2 is the structural schematic diagram for the power diode that one embodiment of the present of invention provides；
Fig. 3 to Fig. 8 is the structural representation of the production method step for the power diode that one embodiment of the present of invention provides
Figure；
Fig. 9 is the equivalent circuit diagram for the power diode structure that one embodiment of the present of invention provides；
In figure: 1, substrate；2, the first epitaxial layer；3, buried layer；4, the second epitaxial layer；5, the first injection region；6, width one；7,
Width two；8, the second injection region；9, third injection region；10, first electrode；11, second electrode.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Referring next to attached drawing, a kind of production method of power diode of the embodiment of the present invention is elaborated.
A kind of power diode provided in an embodiment of the present invention and preparation method thereof is carried out below in conjunction with Fig. 1 to Fig. 9 detailed
It describes in detail bright.
The embodiment of the present invention provides a kind of production method of power diode, as depicted in figs. 1 and 2, the power diode
Production method include:
Step S01: providing the substrate 1 of the first conduction type, the of 1 upper surface growth regulation of substrate, one conduction type
One epitaxial layer 2；
Step S02: the buried layer 3 to form the second conduction type is injected in 2 upper surface of the first epitaxial layer；
Step S03: the second epitaxial layer 4 of the first conduction type is formed in 2 upper surface of the first epitaxial layer；
Step S04: injecting the first injection region 5 to form the first conduction type in 4 upper surface of the second epitaxial layer, described
The width of first injection region 5 is substantially equal to the width of the buried layer 3；
Step S05: position corresponding with the buried layer 3 forms the second conduction type in second epitaxial layer 4
Second injection region 8, and second injection region 8 is connect with the buried layer 3；
Step S06: the top in second epitaxial layer 4 positioned at second injection region 8 forms the second conduction type
Third injection region 9, second injection region 8 connect with the third injection region 9, the depth and width of second injection region 8
Degree is greater than the depth and width of the third injection region 9；
Step S07: first electrode 10 is formed in 4 upper surface of the second epitaxial layer；It is formed in the lower surface of the substrate 1
The second electrode 11 being connect with the substrate 1.
The present invention improves on the basis of PIN diode proposes a kind of high injection efficiency power diode chip,
The embodiment of the present invention forms the semiconductor regions of the second conduction type, second formed at this time by the way of buried layer 3 plus extension
The defect of the semiconductor regions of conduction type can be fewer, thus caused by leak electricity it is also small, in addition, the depth due to epitaxial layer can
Arbitrarily to adjust, junction depth is bigger, and device pressure resistance is better.First injection region 5 is formed with Schottky gesture with the first electrode 10
It builds, so that there are Schottky contacts, third injection region 9 described in the pressure drop ratio of the Schottky contacts formed at this time and second note
The PN junction for entering the formation of area 8 is small, and the Schottky contacts are used in mixed way with the PN junction, have not only been improved breakdown voltage but also have been reduced and have led
Logical pressure drop.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, using first conduction type as n-type doping, second conduction type is doped to for p-type
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
Attached drawing 3 is please referred to, step S01 is executed, specifically: the substrate 1 of the first conduction type is provided, on the substrate 1
First epitaxial layer 2 of one conduction type of surface growth regulation.Wherein, it is led in 1 upper surface growth regulation one of the substrate of the first conduction type
The mode of first epitaxial layer 2 of electric type is not limited to a kind of fixed mode, can be raw using extension in 1 upper surface of substrate
It is long to be formed, first epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.
It is possible to further be epitaxially-formed in the 1 upper surface use of substrate, ion implanting and/or diffused with boron can also be passed through
The method of any combination of element or phosphide element or aluminium element or three forms first epitaxial layer in 1 upper surface of substrate
2.Specifically, the extension or the method for diffusion include depositing operation.In some embodiments of the invention, deposition can be used
Technique forms first epitaxial layer 2 in 1 upper surface of substrate, for example, depositing operation can be selected from electron beam evaporation, change
Learn one of vapor deposition, atomic layer deposition, sputtering.Preferably, the is formed using chemical vapor deposition on the substrate 1
One epitaxial layer 2, chemical vapor deposition include process for vapor phase epitaxy.In production, chemical vapor deposition uses vapour phase epitaxy mostly
Technique forms the first epitaxial layer 2 using process for vapor phase epitaxy in 1 upper surface of substrate, and silicon can be improved in process for vapor phase epitaxy
The perfection of material improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.Preferably, institute
It states the first epitaxial layer 2 and the substrate 1 is all that silicon materials are made, so that the substrate 1 and first epitaxial layer 2 have the phase isomorphous
The silicon face of body structure, to keep the control to dopant type and concentration.
It please refers to attached drawing 4, executes step S02, specifically: it injects to form second and lead in 2 upper surface of the first epitaxial layer
The buried layer 3 of electric type.The buried layer 3 can also pass through ion implanting and/or diffusion P elements by being epitaxially-formed
Or the method for any combination of arsenic element or both is formed.Preferably, the method that ion implanting can be used forms the buried layer
3, the accumulated dose, depth distribution and surface uniformity of impurity can accurately be controlled by forming the buried layer 3 by ion implanting, can prevent original
Carry out spreading again for impurity, while can realize self-aligned technology, to reduce capacity effect.In some embodiments of the invention,
For at least partly surface exposure of the buried layer 3 in the upper surface of first epitaxial layer 2, i.e., the upper surface of the described buried layer 3 is exposed
In first epitaxial layer 2.In some embodiments of the invention, the buried layer 3 is heavy doping, to further reduced institute
State the resistivity of power diode.
Attached drawing 5 is please referred to, step S03 is executed, specifically: the first conductive-type is formed in 2 upper surface of the first epitaxial layer
Second epitaxial layer 4 of type.Wherein, the side of the second epitaxial layer 4 of the first conduction type is formed in 2 upper surface of the first epitaxial layer
Formula is not limited to a kind of fixed mode, and extension, diffusion and/or the method for injection can be used and form second epitaxial layer 4, has
Body, the method for the extension or diffusion includes depositing operation.It is possible to further use extension, diffusion and/or injection phosphorus member
The method of any combination of plain or arsenic element or both forms second epitaxial layer 4.In some embodiments of the invention, make
The second epitaxial layer 4 is formed in 2 upper surface of the first epitaxial layer with depositing operation, for example, depositing operation can be selected from electronics
One of beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Wherein, chemical vapor deposition includes vapour phase epitaxy work
Skill, it is preferred that form the second epitaxial layer 4, process for vapor phase epitaxy using process for vapor phase epitaxy in 2 upper surface of the first epitaxial layer
The perfection that silicon materials can be improved improves the integrated level of device, reaches raising minority carrier life time, reduces the electric leakage of storage element
Stream.Second epitaxial layer 4 covers the upper surface of first epitaxial layer 2, and is equipped with certain thickness.
It please refers to attached drawing 6, executes step S04, specifically, inject to form first and lead in 4 upper surface of the second epitaxial layer
First injection region 5 of electric type, the width of first injection region 5 are substantially equal to the width of the buried layer 3.Of the invention one
In a little embodiments, mask material is prepared in the upper surface of second epitaxial layer 4, the mask material is specially photoresist, because
This forms the first photoresist layer (not shown) for being used for exposure mask, is existed respectively on first photoresist layer by the method for photoetching
The first injection region 5 of the first conduction type is formed in second epitaxial layer 4.It is used in the upper surface of first photoresist layer
Ion implanting and/or the method for diffusion form the first injection region 5 of the first conduction type, then get rid of first photoresist
Layer, finally carries out thermal annealing.Further, ion implanting and/or diffusion phosphorus are used in the upper surface of first photoresist layer
The method of any combination of element or arsenic element or both forms the first injection region 5 of the first conduction type.It is understood that
In some embodiments of the invention, it is illustrated in figure 6 the sectional view of the power diode, at this time the width of the buried layer 3
For the width of 3 left and right sides of buried layer, the width of first injection region 5 is the width of 5 left and right sides of the first injection region
Degree, in addition, in embodiment below, using width as the width at left and right sides of device, and using depth as device above and below
It is illustrated for the height of two sides, but not to this restriction.It should be noted that the width of the buried layer 3 is set as width
One 6, the width of first injection region 5 is set as width 27, during injection forms the first injection region 5, the width
It spends 27 and is greater than width 1, since during forming the second epitaxial layer 4, the buried layer 3 can be spread, so that
The width of the buried layer 3 increases, and the setting width when injection by first injection region 5 is needed to be greater than the buried layer 3 at this time
Setting width when formation, just can guarantee when resulting devices formation described in the width of the first injection region 5 be substantially equal to the buried layer 3
Width.It should be noted that width be substantially equal to it will be appreciated by those skilled in the art that error range in.When described
When the width of one injection region 5 is substantially equal to the width of the buried layer 3, the conductive path area in the power diode of formation compares
Greatly, so as to improve breakdown voltage, conducting resistance is reduced.
Further, the doping concentration of first injection region 5 is higher than to the doping concentration of the substrate 1, by the lining
The doping concentration at bottom 1 is higher than the doping concentration of first epitaxial layer 2, and the doping concentration of first epitaxial layer 2 is higher than
The doping concentration of second epitaxial layer 4.First epitaxial layer 2 and second epitaxial layer 4 are grown on the substrate 1
During, since first epitaxial layer 2 is formed on the basis of substrate 1, second epitaxial layer 4 is described first
It is formed on the basis of epitaxial layer 2, therefore the doping concentration of the substrate 1 is higher than the doping concentration of first epitaxial layer 2, and institute
The doping concentration for stating the first epitaxial layer 2 is higher than the doping concentration of second epitaxial layer 4.The electricity of second epitaxial layer 4 at this time
Resistance rate is higher than the resistivity of first epitaxial layer 2, and the resistivity of first epitaxial layer 2 is higher than the resistivity of the substrate 1,
In order to reduce the integral device resistivity of the power diode, more Surge handling capabilities are obtained, are needed outside described second
Prolong first injection region 5 for increasing heavy doping in layer 4, to reduce resistivity, electric current also can be better by.
Attached drawing 7 is please referred to, step S05 is executed, specifically: it is corresponding with the buried layer 3 in second epitaxial layer 4
Position forms the second injection region 8 of the second conduction type, and second injection region 8 is connect with the buried layer 3.Of the invention
In some embodiments, mask material is prepared in the upper surface of second epitaxial layer 4, the mask material is specially photoresist,
Therefore the second photoresist layer (not shown) for being used for exposure mask is formed, the method on second photoresist layer through photoetching is in institute
State the second injection region 8 that the second conduction type is formed in the second epitaxial layer 4.Second photoresist layer upper surface use from
The method of son injection and/or diffusion forms the second injection region 8 of the second conduction type, then gets rid of second photoresist layer,
Finally carry out thermal annealing.Further, ion implanting and/or diffusion boron element are used in the upper surface of second photoresist layer
Or the method for any combination of phosphide element or aluminium element or three forms the second injection region 8 of the second conduction type.It needs to illustrate
, second injection region 8 contacted with the buried layer 3, i.e., described second injection region 8 is connect with the buried layer 3.Ying Li
Solution, when forming second injection region 8, by second injection region 8 be set to the buried layer 3 top and the injection region
It is connect with the buried layer 3, and the width of second injection region 8 is substantially equal to the width of the buried layer 3, in addition, due to described
The width of second injection region 8 is substantially equal to the width of the buried layer 3, therefore the part of second injection region 8 and described first
Injection region 5 connects.
Attached drawing 7 is please referred to, step S06 is executed, specifically: being located at second injection region 8 in second epitaxial layer 4
Top formed the second conduction type third injection region 9, second injection region 8 is connect with the third injection region 9, described
The depth and width of second injection region 8 are greater than the depth and width of the third injection region 9.In some embodiments of the present invention
In, above-mentioned steps are based on, pass through the method for photoetching on second photoresist layer while forming the second injection region 8
The third injection region 9 of the second conduction type is formed in second injection region 8.Make in the upper surface of second photoresist layer
The third injection region 9 of the second conduction type is formed with ion implanting and/or the method for diffusion, then gets rid of second photoresist
Layer, finally carries out thermal annealing.Further, ion implanting and/or diffused with boron are used in the upper surface of second photoresist layer
The method of any combination of element or phosphide element or aluminium element or three forms the third injection region 9 of the second conduction type.Ying Li
Solution, the third injection region 9 second injection region 8 top and the third injection region 9 and second injection region 8 connect
It connects.It should be noted that second injection region 8 and the third injection region 9 are formed by multiple ion implanting respectively, wherein
The ion energy and dosage injected in second injection region 8 and 9 forming process of third injection region is all different, to make
The depth and width for obtaining second injection region 8 are greater than the depth and width of the third injection region 9.Those skilled in the art can
With the ion energy and dosage for needing to inject determine according to actual needs.
Further, the doping concentration of the buried layer 3 is higher than to the doping concentration of the third injection region 9, and will be described
The doping concentration of third injection region 9 is higher than the doping concentration of second injection region 8.Outside due to the buried layer 3 and described first
The conduction type for prolonging layer 2 is different, therefore the buried layer 3 and first epitaxial layer 2 form PN junction, in the process for forming PN junction
In, the doping concentration of the buried layer 3 is higher than to the doping concentration of the third injection region 9, and mixing the third injection region 9
Miscellaneous concentration is higher than the doping concentration of second injection region 8, leads so as to increase the whole result of the power diode
Electric energy power.
Further, the depth and width that the depth and width of second injection region 8 are greater than the third injection region 9 have
Body include: to be formed the third injection region 9 ion implantation energy and implantation dosage be greater than formed second injection region 8 from
Sub- Implantation Energy and implantation dosage, so that the depth and width of second injection region 8 are greater than the depth of the third injection region 9
And width；The quantity of second injection region 8 and the quantity of the third injection region 9 and the buried layer 3 is corresponding identical；It will
First injection region 5 is arranged with the third injection region 9 interval.When the depth and width of second injection region 8 are greater than institute
When stating the depth and width of third injection region 9, i.e., the junction depth and width of described second injection region 8 are greater than the third injection region 9
Junction depth and width when, the cross-sectional area of second injection region 8 is greater than the cross-sectional area of the third injection region 9, due to this
The width of the first injection region Shi Suoshu 5 is substantially equal to the width of the buried layer 3, and the quantity of second injection region 8 with it is described
The quantity of third injection region 9 and the buried layer 3 corresponds to identical, and first injection region 5 and the third injection region 9 interval are set
It sets, to guarantee that first injection region 5 is contacted with second injection region 8.It should be noted that in some realities of the invention
Apply in example, the buried layer 3, first injection region 5, second injection region 8 and the third injection region 9 quantity phase
Together, for example, the buried layer 3, first injection region 5, second injection region 8 and the quantity of the third injection region 9 can
It can also be two to be one, can also be three, but not limited to this, those skilled in the art can be according to reality
Border needs to select the quantity of the buried layer 3, first injection region 5, second injection region 8 and the third injection region 9.
Attached drawing 8 is please referred to, step S07 is executed, specifically: forming first electrode 10 in 4 upper surface of the second epitaxial layer；
The second electrode 11 connecting with the substrate 1 is formed in the lower surface of the substrate 1.It, can be described by annealing process
The upper surface of two epitaxial layers 4, which is formed, has certain thickness the first metal layer, and the first metal layer is the first electrode 10,
And it is formed in the second metal layer that the substrate 1 connects in the lower surface of the substrate 1, the second metal layer also has centainly
Thickness, the second metal layer is the second electrode 11 at this time.
Further, first injection region 5 is connect with 8 part of the second injection region.First injection at this time
Area 5 and 8 part of the second injection region form PN junction, due to the contact of first injection region 5 and second injection region 8
Area is greater than the contact area of first injection region 5 with second injection region 8, therefore the PN junction formed at this time is with described the
The PN junction that one injection region 5 and second injection region 8 are formed is main PN junction.It should be noted that 10 shape of first electrode
Second epitaxial layer, 4 upper surface described in Cheng Yu, therefore first injection region 5 is directly contacted with the first metal layer, at this time institute
The Schottky contacts that the first metal layer forms similar PN junction with first injection region 5 are stated, by first injection region 5 and institute
The PN junction for stating the formation of the second injection region 8 is reverse biased pn junction, therefore the potential barrier of the reverse biased pn junction is higher, will not pass through electricity at this time
Stream.
In some embodiments of the invention, the buried layer 3, first injection region 5, second injection region 8 and
The quantity of the third injection region 9 is identical, and the buried layer 3, first injection region 5, second injection region 8 and described
Third injection region 9 is connected with each other, at this time by the buried layer 3, first injection region 5, second injection region 8 and described the
Three injection regions 9 are considered as first area, at this time the buried layer 3, first injection region 5, second injection region 8 and described
The quantity at least two of three injection regions 9, the i.e. quantity at least two of first area at this time, it is to be understood that described
There is the conductive channel of one first conduction type, the conductive channel passes through the lining between one region and adjacent first area
Bottom 1, first epitaxial layer 2, second epitaxial layer 4 and first injection region 5 are formed.When forward current passes through,
Since the PN junction that first area and first epitaxial layer 2 are formed has potential barrier, which is about 0.7V, when the forward current
When less than 0.7V, the forward current is flowed through from the conductive channel, when electric current is greater than or equal to 0.7V, the forward current
The conductive channel and the PN junction can just be passed through simultaneously.
As shown in Fig. 2, the embodiment of the present invention provides a kind of power diode, shown power diode includes:
The substrate 1 of first conduction type；
First epitaxial layer 2 of the first conduction type is grown on 1 upper surface of substrate；
The buried layer 3 of second conduction type, injection are formed in the upper surface of first epitaxial layer 2；
Second epitaxial layer 4 of the first conduction type is formed in 2 upper surface of the first epitaxial layer；
First injection region 5 of the first conduction type, injection are formed in the upper surface of second epitaxial layer 4, and described first
The width of injection region 5 is substantially equal to the width of the buried layer 3；
Second injection region 8 of the second conduction type is formed in corresponding with the buried layer 3 in second epitaxial layer 4
It position and is connect with the buried layer 3；
The third injection region 9 of second conduction type is formed in second epitaxial layer 4 and is located at second injection region
8 top, second injection region 8 are connect with the third injection region 9, and the depth and width of second injection region 8 are greater than
The depth and width of the third injection region 9；
First electrode 10 is formed in the upper surface of second epitaxial layer 4；
Second electrode 11 is formed in the lower surface of the substrate 1 and connect with the substrate 1.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
In some embodiments of the invention, as shown in Fig. 2, the power diode includes the substrate of the first conduction type
1 and first epitaxial layer 2, first epitaxial layer 2 be grown on 1 upper surface of substrate.Specifically, the substrate 1 is integrated electricity
Carrier in road, the substrate 1 play the role of support, and the substrate 1 also assists in the work of the integrated circuit.The substrate
1 can be silicon substrate, or Sapphire Substrate can also be silicon Chu substrate, it is preferred that the substrate 1 is silicon substrate, this
It is to avoid edge effect because silicon substrate material has the characteristics that low cost, large scale, conductive, can increase substantially
Yield.Preferably, the doping concentration of the substrate 1 is higher than the doping concentration of first epitaxial layer 2, at this time first extension
The resistivity of substrate 1 described in the resistivity ratio of layer 2 is high, reduces dead resistance, to improve the breakdown reverse voltage of device.
In some embodiments of the invention, as shown in Fig. 2, the power diode further includes burying for the first conduction type
Layer 3, the buried layer 3 is formed in first epitaxial layer 2, and at least partly surface exposure of the buried layer 3 is in described first
2 upper surface of epitaxial layer, the doping concentration of the buried layer 3 are higher than the doping concentration of first epitaxial layer 2, and the buried layer 3 is mixed
Miscellaneous concentration is higher than the doping concentration of second epitaxial layer 4, to reduce the resistivity of the buried layer 3.Electric current can be along electricity
The low buried layer 3 of resistance rate, to change current path, is equivalent to 2 downside of the first epitaxial layer and reduces series electrical
Resistance, and electric current is able to flow to the buried layer 3, avoids leaking electricity.
In some embodiments of the invention, as shown in Fig. 2, the power diode further includes the of the first conduction type
Two epitaxial layers 4, second epitaxial layer 4 are formed in 2 upper surface of the first epitaxial layer.First epitaxial layer 2 and described
The thickness of two epitaxial layers 4 depends on during the physical size and the device fabrication of the semiconductor devices to be realized
Silicon loss.Second epitaxial layer 4 is grown on 2 upper surface of the first epitaxial layer, and playing reduces PN in semiconductor devices
The effect of the leakage current of knot.
In some embodiments of the invention, as shown in Fig. 2, the power diode further includes the of the first conduction type
One injection region 5, first injection region 5 are formed in 4 upper surface of the second epitaxial layer.In some embodiments of the invention,
First injection region 5 is heavy doping, to further decrease the resistivity of the power diode.
In conclusion the power diode overall structure is symmetrical and is the first primitive unit cell.
Please refer to the equivalent circuit diagram of power diode structure shown in Fig. 9.When to the first electrode 10 and described
When two electrodes 11 are powered, the electric current flows to the second electrode 11 from the first electrode 10.It should be noted that following
The forward and reverse of the PN junction of formation is set as N-type with the first conduction type, and it is this hair that second conduction type, which is set as p-type,
Bright one embodiment does not limit this to be judged.Due to the buried layer 3, first injection region 5, described
The quantity of two injection regions 8 and the third injection region 9 is identical, when the buried layer 3, first injection region 5, described second
When the quantity of injection region 8 and the third injection region 9 is one, the third injection region 9, second injection region 8 with
And the buried layer 3 is the second conduction type, and the buried layer 3 is in contact with the first epitaxial layer 2 of the first conduction type, therefore
First epitaxial layer 2 of the buried layer 3 of the second conduction type and first conduction type forms positive PN junction, the forward direction PN
Knot forms a positive diode；When the buried layer 3, first injection region 5, second injection region 8 and the third
When the quantity of injection region 9 is two or more, by the buried layer 3, first injection region 5, second injection region 8
And the third injection region 9 is as the semiconductor regions with the second conduction type, in semiconductor regions and adjacent
Between semiconductor regions, with the first conduction type conductive channel, the conductive channel by the substrate 1, described first outside
Prolong layer 2, second epitaxial layer 4 and first injection region 5 to be formed, the conductive channel is the first conduction type, will not
PN junction is formed, but the conductive channel still has certain resistance, therefore, in the equivalent circuit formed in Fig. 9, the conduction
Channel is equivalent to a small resistance, and the forward diode that the small resistance and the buried layer 3 are formed with first epitaxial layer 2 is simultaneously
Connection forms equivalent circuit in parallel.
The technical solution of the embodiment of the present invention is had been described in detail above with reference to the accompanying drawings, the embodiment of the present invention is in PIN diode
On the basis of improve and propose a kind of diode chip for backlight unit with high injection efficiency power, by first epitaxial layer
2 and second epitaxial layer 4 in carry out the semiconductor regions that ion implanting forms the second conduction type, and the semiconductor and phase
The conductive channel that the first conduction type is formed between the adjacent semiconductor, when electric current flows to described the from the first electrode 10
When two electrodes 11, i.e., under forward current, when the forward current is low current, most of electric current is all from the conduction
Channel is flowed through, and the hole injection efficiency of the semiconductor regions is low；It is described in parallel small when the forward current is high current
The pressure drop of resistance is more than the cut-in voltage for the PN junction that the buried layer 3 is formed with first epitaxial layer 2, and the semiconductor regions are opened
Begin to inject hole, the hole injection efficiency of the semiconductor regions increases, Antisurge current ability with the increase of forward current
By force.In the case where same breakdown voltage, the concentration of the semiconductor regions of new construction is lower than traditional structure, can reduce just
To pressure drop, and breakdown voltage can be improved.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of power diode characterized by comprising
The substrate of first conduction type；
First epitaxial layer of the first conduction type, is grown on the upper surface of substrate；
The buried layer of second conduction type, injection are formed in the upper surface of first epitaxial layer；
Second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
First injection region of the first conduction type, injection are formed in the upper surface of second epitaxial layer, first injection region
Width be substantially equal to the width of the buried layer；
Second injection region of the second conduction type, be formed in second epitaxial layer position corresponding with the buried layer and with
The buried layer connection；
The third injection region of second conduction type is formed in second epitaxial layer and is located at the upper of second injection region
Side, second injection region are connect with the third injection region, and the depth and width of second injection region are greater than the third
The depth and width of injection region；
First electrode is formed in the upper surface of second epitaxial layer；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
2. power diode according to claim 1, which is characterized in that the doping concentration of first injection region is higher than institute
The doping concentration of substrate is stated, the doping concentration of the substrate is higher than the doping concentration of first epitaxial layer, first extension
The doping concentration of layer is higher than the doping concentration of second epitaxial layer.
3. power diode according to claim 1, which is characterized in that the doping concentration of the buried layer is higher than the third
The doping concentration of injection region, the doping concentration of the third injection region are higher than the doping concentration of second injection region.
4. power diode according to claim 1, which is characterized in that the quantity and the third of second injection region
The quantity of injection region and the buried layer is identical, and first injection region and third injection region interval are arranged.
5. power diode according to claim 4, which is characterized in that first injection region and second injection region
Part connects.
6. a kind of production method of power diode comprising:
The substrate of first conduction type is provided；
First epitaxial layer of one conduction type of surface growth regulation over the substrate；
The buried layer to form the second conduction type is injected in first epitaxial layer upper surface；
The second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface；
The first injection region to form the first conduction type, the width of first injection region are injected in second epitaxial layer upper surface
Degree is substantially equal to the width of the buried layer；
Position corresponding with the buried layer forms the second injection region of the second conduction type, and institute in second epitaxial layer
The second injection region is stated to connect with the buried layer；
The third injection region of the second conduction type, institute are formed positioned at the top of second injection region in second epitaxial layer
It states the second injection region to connect with the third injection region, the depth and width of second injection region are greater than the third injection region
Depth and width；
First electrode is formed in second epitaxial layer upper surface；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
7. a kind of production method of power diode according to claim 6, which is characterized in that by first injection region
Doping concentration be higher than the substrate doping concentration, by the doping concentration of the substrate be higher than first epitaxial layer doping
Concentration, and the doping concentration by the doping concentration of first epitaxial layer higher than second epitaxial layer.
8. a kind of production method of power diode according to claim 6, which is characterized in that by the doping of the buried layer
Concentration is higher than the doping concentration of the third injection region, and the doping concentration of the third injection region is higher than second injection
The doping concentration in area.
9. a kind of production method of power diode according to claim 6, which is characterized in that second injection region
The depth and width that depth and width are greater than the third injection region specifically include:
The ion implantation energy and implantation dosage for forming the third injection region are greater than the ion note for forming second injection region
Enter energy and implantation dosage, so that the depth and width of second injection region are greater than the depth and width of the third injection region
Degree；
The quantity of second injection region and the quantity of the third injection region and the buried layer is corresponding identical；
First injection region and third injection region interval are arranged.
10. a kind of production method of power diode according to claim 9, which is characterized in that injected described first
Area is connect with second injection region part.
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| CN201810800736.5A CN108987486A (en) | 2018-07-20 | 2018-07-20 | A kind of power diode and preparation method thereof |
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| CN201810800736.5A CN108987486A (en) | 2018-07-20 | 2018-07-20 | A kind of power diode and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063758A (en) * | 2019-12-31 | 2020-04-24 | 华润半导体（深圳）有限公司 | Photodiode, manufacturing method thereof and high-speed optical coupler |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101707214A (en) * | 2009-11-30 | 2010-05-12 | 浙江大学 | Semiconductor device |
| CN103681781A (en) * | 2012-09-18 | 2014-03-26 | 桂林斯壮微电子有限责任公司 | Buried PN junction barrier Schottky diode |
| US20150372093A1 (en) * | 2014-06-20 | 2015-12-24 | Stmicroelectronics S.R.L. | Wide bandgap high-density semiconductor switching device and manufacturing process thereof |
-
2018
- 2018-07-20 CN CN201810800736.5A patent/CN108987486A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101707214A (en) * | 2009-11-30 | 2010-05-12 | 浙江大学 | Semiconductor device |
| CN103681781A (en) * | 2012-09-18 | 2014-03-26 | 桂林斯壮微电子有限责任公司 | Buried PN junction barrier Schottky diode |
| US20150372093A1 (en) * | 2014-06-20 | 2015-12-24 | Stmicroelectronics S.R.L. | Wide bandgap high-density semiconductor switching device and manufacturing process thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063758A (en) * | 2019-12-31 | 2020-04-24 | 华润半导体（深圳）有限公司 | Photodiode, manufacturing method thereof and high-speed optical coupler |
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Application publication date: 20181211 |