CN108965674B - Photosensitive chip, camera module and electronic equipment - Google Patents
Photosensitive chip, camera module and electronic equipment Download PDFInfo
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- CN108965674B CN108965674B CN201810967292.4A CN201810967292A CN108965674B CN 108965674 B CN108965674 B CN 108965674B CN 201810967292 A CN201810967292 A CN 201810967292A CN 108965674 B CN108965674 B CN 108965674B
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
The embodiment of the application discloses a photosensitive chip, a camera module and electronic equipment. The photosensitive chip comprises a substrate, wherein the substrate comprises at least two pixel arrays and an integrated circuit, the integrated circuit comprises an image processor, and the at least two pixel arrays are multiplexed with the image processor. By adopting the technical scheme of the embodiment of the application, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, and the circuits on the substrate can be reduced through multiplexing the image processors by the pixel arrays, so that the sizes of the photosensitive chip and the camera module can be reduced.
Description
Technical Field
The embodiment of the application relates to a semiconductor device technology, in particular to a photosensitive chip, a camera module and electronic equipment.
Background
Electronic equipment with a plurality of camera modules can control different cameras respectively and carry out different functions to make the picture of catching through the camera have more content and more clear, the formation of image is more exquisite, the color is more bright-colored.
However, in the related art, a multi-camera system having a plurality of camera modules is generally assembled by a bracket. As shown in fig. 1, the first camera module 10 and the second camera module 20 are assembled into a multi-camera system by the bracket 130. Each camera module comprises a photosensitive chip (140, 150) and a lens assembly (110, 120), wherein the lens assembly (110, 120) comprises a lens, a lens seat and a motor. The photosensitive chips (140, 150) are soldered on the circuit board 160, and the imaging areas (141, 151) on the photosensitive chips (140, 150) are located in the vertical projection areas of the lenses (110, 120). Because of the module level assembly mode, the production and calibration precision requirements of the positions among the modules may not be met. Such as binocular ranging, image fusion, etc., the small distance or angle deviation will cause larger deviation to the final result.
Disclosure of Invention
The embodiment of the application provides a photosensitive chip, a camera module and electronic equipment, which can optimize the design scheme of a multi-camera system in the related technology.
In a first aspect, an embodiment of the present application provides a photosensitive chip, including a substrate, where the substrate includes at least two pixel arrays and an integrated circuit, where the integrated circuit includes an image processor, and where the at least two pixel arrays multiplex the image processor.
In a second aspect, an embodiment of the present application further provides a camera module, where the camera module includes the photosensitive chip described in the first aspect.
In a third aspect, an embodiment of the present application further provides an electronic device, where the electronic device has the camera module set in the second aspect.
The embodiment of the application provides a photosensitive chip scheme, which comprises a substrate, wherein the substrate comprises at least two pixel arrays and an integrated circuit, the integrated circuit comprises an image processor, and the at least two pixel arrays are multiplexed with the image processor. According to the technical scheme, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, the position calibration of the multi-camera system is completed in the stage of manufacturing the photosensitive chip through the semiconductor, and the assembly precision of the multi-camera system is improved. In addition, the photosensitive chip is provided with a plurality of pixel arrays required by a multi-camera system, and the pixel arrays multiplex the image processor, so that circuits on a substrate are reduced, and further, the sizes of the photosensitive chip and the camera module can be reduced. Meanwhile, at least two pixel arrays share one image processor, so that the consistency of image effects can be improved, the situation that the finally output image effects are different due to the fact that the image processors are different is avoided, the time for adjusting the image effects to enable the effects to be consistent is saved, and therefore the processing time of image data is shortened.
Drawings
FIG. 1 is a schematic diagram of a conventional dual camera system;
FIG. 2 is a block diagram of a photosensitive chip according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of another embodiment of a photosensitive chip;
FIG. 4 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 5 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 6 is a block diagram of a further embodiment of a photosensitive chip;
FIG. 7 is a block diagram of a photosensitive chip according to an embodiment of the present disclosure;
FIG. 8 is a schematic circuit diagram of a classical correlated double sampling circuit in the related art;
FIG. 9 is a timing diagram of the operation of the correlated double sampling circuit;
fig. 10 is a schematic structural diagram of a camera module according to an embodiment of the present disclosure;
fig. 11 is a block diagram of a structure of a smart phone according to an embodiment of the present application.
Detailed Description
The technical solution of the present application is further described below by means of specific embodiments in conjunction with the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.
It should be noted that, due to the continuous improvement of the semiconductor technology and the technological level, the photosensitive chip (Image Sensor) is used as a basic device for obtaining visual information, and has wider and wider application because it can realize the obtaining, conversion and expansion of visual functions of information, and gives visual Image information with visual, multi-level and rich content. The most widely used solid-state image sensors in the related art mainly include Charge Coupled Device (CCD) image sensors and Complementary Metal Oxide Semiconductor (CMOS) image sensors. The photosensitive chip of the embodiment of the present application may be the above-described two types of image sensors.
The semiconductor substrate of the photosensitive chip is provided with at least two pixel arrays and an integrated circuit for realizing the function of the photosensitive chip. The integrated circuit comprises an image processor, wherein the image processor performs preset processing on pixel signals read by at least two pixel arrays to obtain image data, and adds an array identifier for the image data according to the source of the pixel signals so as to realize multiplexing of the image processor by the at least two pixel arrays. It should be noted that, in the embodiment of the present application, at least two pixel arrays are sequentially read according to a set time sequence, and a line-by-line scanning and column-by-column reading manner is adopted for each pixel array, so that it is ensured that the pixel signals in the second pixel array are read only after the pixel signals corresponding to all the pixel points in the first pixel array are read. The pixel signal is output to the image processor, so that the image processor preprocesses the pixel signal. It should be noted that, the pixel array is an imaging region of an image, and includes x×y (row×column) imaging pixels, each pixel has a light sensing capability, and can convert an optical signal into a corresponding analog electronic signal.
The integrated circuit comprises a line scanning circuit, and the pixel array is electrically connected with the line scanning circuit through a switch tube (triode or field effect tube) and outputs a line scanning signal to the pixel array. It will be appreciated that the number of row scan circuits may be the same as the number of pixel arrays, the first row scan circuit being electrically connected to the first pixel array, the second row scan circuit being electrically connected to the second pixel array, … …, the nth row scan circuit being electrically connected to the nth pixel array, wherein the value of n is determined by the number of pixel arrays of the multi-camera system. Optionally, the at least two line scanning circuits output line scanning signals according to a serial working mode, so as to realize sequential scanning of the at least two pixel arrays.
It should be noted that, a plurality of photosensitive chips may be formed on the same wafer by using the semiconductor device manufacturing process, and dicing may be performed one by one. The photosensitive chip comprises at least two pixel arrays and corresponding integrated circuits. The problem that the multi-camera system module in the related art is difficult to assemble and debug can be avoided. In the related art, the camera module of the multi-camera system is a plurality of photosensitive chips corresponding to a plurality of lenses, each camera has independent functions, and has no function sharing part, and as the chips are respectively positioned on the circuit boards, the placement angle and the inclination of each chip are different, and the difficulty of subsequent equipment and debugging can be increased.
For ease of understanding, the structure of the photosensitive chip will be described by taking a CMOS image sensor as an example. Fig. 2 is a block diagram of a photosensitive chip according to an embodiment of the present application. The light sensing chip shown in fig. 2 includes a first pixel array 202, a second pixel array 206, and an integrated circuit, wherein the integrated circuit includes a first row scanning circuit 201 and a first column reading circuit 203 electrically connected to the first pixel array 202, a second row scanning circuit 205 and a second column reading circuit 207 electrically connected to the second pixel array 206, a first analog signal amplifier 212 electrically connected to the first column reading circuit 203, a second analog signal amplifier 213 electrically connected to the second column reading circuit 207, a first analog-to-digital converter 210 electrically connected to the first analog signal amplifier 212, a second analog-to-digital converter 211 electrically connected to the second analog signal amplifier 213, an image processor 209, a first I/O interface (i.e., an input/output interface) 214, and a second I/O interface 215. The first analog-to-digital converter 210 and the second analog-to-digital converter 211 are electrically connected to the image processor 209, and the image processor 209 is electrically connected to the first I/O interface 214 and the second I/O interface 215, respectively.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photosensitive chip, so that the timing control circuit outputs a scan control pulse to the first row scan circuit 201, and outputs a column selection control signal to the first column selection circuit 204. The first row scanning circuit 201 outputs row scanning signals to the first pixel array 202 row by row in accordance with the scanning control pulse. The first column selecting circuit 204 is used for gating the column bus 216 of the column to be read and the first column reading circuit 203 according to the column selecting control signal. The scan control pulse is used to control the first row scan circuit 201 to output a row scan signal to a first row of the first pixel array 202 in a first period of time, so as to realize the conduction of the field effect transistors electrically connected to the pixels of the first row, and during the first period of time, the column selection control signal is used to control the first column selection circuit 204 to output a conduction signal to the field effect transistors between the column bus and the first column reading circuit 203, so as to respectively turn on each field effect transistor, realize the reading of the pixel signals on the column bus one by one, and output the pixel signals to the first analog signal amplifier 212. After the pixel signals of the last column of pixels in the first row are read, scanning signals are output to the second row to realize the conduction of field effect transistors electrically connected with the pixels in the second row, and the pixel signals on the column bus are read one by one. And so on until the pixel signals of the last row and the last column of pixels in the first pixel array 202 are read out.
After the pixel signals of the last row and the last column of the pixels in the first pixel array 202 are read, the timing control circuit outputs a scan control pulse to the second row scanning circuit 205, and outputs a column selection control signal to the second column selection circuit 208. The second line scanning circuit 205 outputs line scanning signals to the second pixel array 206 line by line in accordance with the scanning control pulse. The second column selection circuit 208 is used for gating the column bus 216 of a column to be read and the second column reading circuit 207 according to a column selection control signal. The scan control pulse is used to control the second row scan circuit 205 to output a row scan signal to the first row of the second pixel array in a second period of time, so as to realize the conduction of the field effect transistors electrically connected to the pixels of the first row, and during the second period of time, the column selection control signal is used to control the second column selection circuit 208 to output a conduction signal to the field effect transistors between the column bus and the second column reading circuit 207, so as to respectively turn on each field effect transistor, realize the reading of the pixel signals on the column bus one by one, and output the pixel signals to the second analog signal amplifier 213. After the pixel signals of the last column of pixels in the first row are read, scanning signals are output to the second row to realize the conduction of field effect transistors electrically connected with the pixels in the second row, and the pixel signals on the column bus are read one by one. And so on until the pixel signals of the last row and the last column of pixels in the second pixel array 206 are read out.
The first analog signal amplifier 212 is configured to amplify the acquired pixel signals of the first pixel array 202, and output the amplified pixel signals to the first analog-to-digital converter 210.
The second analog signal amplifier 213 is configured to amplify the acquired pixel signals of the second pixel array 206, and output the amplified pixel signals to the second analog-to-digital converter 211.
The first analog-to-digital converter 210 receives the pixel signal corresponding to the amplified first pixel array 202 output from the first analog signal amplifier 212, converts the amplified pixel signal into a digital signal, and outputs the digital signal to the image processor 209 electrically connected to the first analog-to-digital converter 210.
The second analog-to-digital converter 211 receives the pixel signal corresponding to the amplified second pixel array 206 output from the second analog signal amplifier 213, converts the amplified pixel signal into a digital signal, and outputs the digital signal to the image processor 209 electrically connected to the second analog-to-digital converter 211.
The image processor 209 receives the digital signals output by the first analog-to-digital converter 210 and the second analog-to-digital converter 211, performs preset processing on the digital signals according to the chip definition function of the photosensitive chip to obtain image data, and adds an array identifier to the image data according to the source of the digital signals to realize multiplexing of the at least two pixel arrays by the image processor. For example, the image processor 209 performs image processing on the digital signal output by the first analog-to-digital converter 210 to obtain image processing data, and adds an array identifier to the image processing data to indicate that the image data is determined according to the pixel signal read by the first pixel array 202. The image processor 209 performs image processing on the digital signal output from the second analog-to-digital converter 211 to obtain an image process, and adds an array identifier to the image process to indicate that the image data is determined according to the pixel signal read by the second pixel array 206. The image processor 209 sends the image data to the corresponding I/O interface according to the array identification. For example, the image processor 209 transmits image data determined from pixel signals read from the first pixel array 202 to the first I/O interface 214, and the image processor 209 transmits image data determined from pixel signals read from the second pixel array 206 to the second I/O interface 215. Note that the preset processing of the digital signal includes processing of AEC (automatic exposure control), AGC (automatic gain control), AWB (automatic White balance), color correction, lens Shading correction, gamma correction, dead pixel removal, auto Black Level correction, auto White Level correction, and the like.
The first I/O interface 214 receives the image data output by the image processor 209, adjusts the format of the image data according to the set format, and outputs the adjusted image data to the back-end platform according to a certain specification.
The second I/O interface 215 receives the image data output by the image processor 209, adjusts the format of the image data according to the set format, and outputs the adjusted image data to the back-end platform according to a certain specification.
The embodiment of the application provides a photosensitive chip scheme, which comprises a substrate, wherein the substrate comprises at least two pixel arrays and an integrated circuit, the integrated circuit comprises an image processor, and the at least two pixel arrays are multiplexed with the image processor. According to the technical scheme, the same wafer is used as the substrate, the photosensitive chip of the multi-camera system is designed and formed on the substrate, the position calibration of the multi-camera system is completed in the stage of manufacturing the photosensitive chip through the semiconductor, and the assembly precision of the multi-camera system is improved. In addition, the photosensitive chip is provided with a plurality of pixel arrays required by a multi-camera system, and the pixel arrays multiplex the image processor, so that circuits on a substrate are reduced, and further, the sizes of the photosensitive chip and the camera module can be reduced. Meanwhile, at least two pixel arrays share one image processor, so that the consistency of image effects can be improved, the situation that the finally output image effects are different due to the fact that the image processors are different is avoided, the time for adjusting the image effects to enable the effects to be consistent is saved, and therefore the processing time of image data is shortened.
Fig. 3 is a block diagram of another photosensitive chip according to an embodiment of the present application. The buses of at least two pixel arrays in the photosensitive chip shown in fig. 3 are correspondingly and electrically connected through an etching process, and the column buses are electrically connected with a column reading circuit through a switch unit, so that the column reading circuit is respectively connected with the at least two pixel arrays. It should be noted that the corresponding electrical connection may mean that the first column bus line 216 of the first pixel array 202 is electrically connected to the first column bus line 216 of the second pixel array 206, the second column bus line 216 of the first pixel array 202 is electrically connected to the second column bus line 216 of the second pixel array 206, and the 3 rd column bus line 216 of the first pixel array 202 is electrically connected to the 3 rd column bus line 216 of the second pixel array 206. As shown in fig. 3, the column bus 216 of the second pixel array 206 is formed by the column bus 216 of the first pixel array 202 extending downward. The column select circuit 302 is connected to the control terminal of the switch unit, and the column bus 216 and the column read circuit 301 are respectively connected to the remaining two terminals of the switch unit. The column read circuit 301 is electrically connected to the first analog signal amplifier 212 and the second analog signal amplifier 213, respectively, and a first switch circuit 303 is connected in series between the column read circuit 301 and the first analog signal amplifier 212, and a second switch circuit 304 is connected in series between the column read circuit 301 and the second analog signal amplifier 213. The remaining circuits are similar to the above embodiments and will not be described here again.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photo chip, so that the timing control circuit outputs a scan control pulse to the first row scan circuit 201, and outputs a column selection control signal to the column selection circuit 302. The first row scanning circuit 201 outputs row scanning signals to the first pixel array 202 row by row in accordance with the scanning control pulse. The column select circuit 302 gates the column bus 216 of the column to be read in the first pixel array 202 and the column read circuit 301 in accordance with the column select control signal. Thus, the pixel signals of the 3 pixel units in the first row in the first pixel array 202 are sequentially read; the pixel signals of the 3 pixel units in the second row in the first pixel array 202 are read, and then the pixel signals of the pixel units in the third row and the fourth row are sequentially read. When the pixel signals of one pixel unit of the last row and the last column in the first pixel array 202 are read, the timing control circuit outputs a scan control pulse to the second row scanning circuit 205, and the column selection circuit 302 gates the column bus 216 and the column reading circuit 301 of the column to be read in the second pixel array 206 according to the column selection control signal. Thus, the pixel signals of the 3 pixel units of the first row in the second pixel array 206 are sequentially read; the pixel signals of the 3 pixel units in the second row in the second pixel array 206 are read, and then the pixel signals of the pixel units in the third row and the fourth row are sequentially read.
The time sequence control circuit is electrically connected with the switch circuit. The timing control circuit generates a switching pulse based on the read order of at least two pixel arrays and the read time of each pixel array, outputs the switching pulse to the first switching circuit 303 and the second switching circuit 304, and turns on or off an analog signal amplifier connected to the column reading circuit 301 based on the switching pulse. For example, the timing control circuit generates the switching pulse according to the reading sequence of the first pixel array 202 and the second pixel array 206 and the reading time after reading each pixel array. If the first pixel array 202 is read first and the first switch circuit 303 is turned on at a high level, the switch pulse output to the control terminal of the switch unit in the first switch circuit 303 is turned on at a high level, and the first switch circuit 303 turns on the column bus line of the first pixel array 202 and the column read circuit 301 until the first pixel array 202 is read. Correspondingly, if the second pixel array 206 is read later and the second switch circuit 304 is turned on at a high level, the switch pulse output to the control terminal of the switch unit in the second switch circuit 304 is first turned to a low level until the second pixel array 206 is read, and the second switch circuit 304 turns on the column bus of the second pixel array 206 and the column read circuit 301. In a period of reading the first pixel array 202, each time a pixel signal is read out by the column reading circuit 301, it is output to the first analog signal amplifier 212 to amplify the pixel signal by the first analog signal amplifier 212. In a period of reading the second pixel array 206, each time a pixel signal is read out by the column reading circuit 301, it is output to the second analog signal amplifier 213 to perform amplification processing on the pixel signal by the second analog signal amplifier 213. The amplified analog signals are then input to corresponding first and second analog-to-digital converters 210 and 211, respectively. The first adc 210 outputs a digital signal to the image processor 209, and the image processor 209 performs a preset process on the pixel signal to obtain image data, and adds an array identifier representing the first pixel array 202 to the image data. The second adc 211 outputs a digital signal to the image processor 209, and the image processor 209 performs a preset processing on the pixel signal to obtain image data, and adds an array identifier representing the second pixel array 206 to the image data. The image processor 209 sends the image data to the corresponding I/O interface according to the array identification. For example, the image processor 209 transmits image data determined from pixel signals read from the first pixel array 202 to the first I/O interface 214, and the image processor 209 transmits image data determined from pixel signals read from the second pixel array 206 to the second I/O interface 215.
The technical scheme of the embodiment of the application provides a photosensitive chip, which comprises that a column bus of at least two pixel arrays is correspondingly and electrically connected by adopting an etching process, and the column bus is respectively and electrically connected with a column selection circuit and a column reading circuit through a switch unit, so that the two pixel arrays share the column selection circuit and the column reading circuit. Therefore, circuits on the substrate are reduced, and further, the sizes of the photosensitive chip and the camera module can be reduced. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
Fig. 4 is a block diagram of still another embodiment of a photosensitive chip. The photosensitive chip comprises a column selection circuit, a column reading circuit, an analog signal amplifier, at least two analog-to-digital converters, an image processor and at least two input/output interfaces. The input of the analog signal amplifier 401 is electrically connected to the output of the column read circuit 301. The first analog-to-digital converter 210 and the second analog-to-digital converter 211 are electrically connected with the analog signal amplifier 401, and a third switch circuit 402 is connected in series between the first analog-to-digital converter 210 and the analog signal amplifier 401, and a fourth switch circuit 403 is connected in series between the second analog-to-digital converter 211 and the analog signal amplifier 401. The remaining circuits are similar to the above embodiments and will not be described here again.
The timing control circuit is electrically connected to the third switch circuit 402 and the fourth switch circuit 403. The timing control circuit generates a switching pulse based on the read order of at least two pixel arrays and the read time of each pixel array, outputs the switching pulse to the third switching circuit 402 and the fourth switching circuit 403, and turns on or off an analog-to-digital converter connected to the analog signal amplifier 401 based on the switching pulse. For example, the timing control circuit generates the switching pulse according to the reading sequence of the first pixel array 202 and the second pixel array 206 and the reading time after reading each pixel array. If the first pixel array 202 is read first, the output switch pulse turns on the third switch circuit 402 and turns off the fourth switch circuit 403 to input the amplified pixel signal to the first analog-to-digital converter 210. When the second pixel array 206 is read, the output switching pulse turns on the fourth switching circuit 403 and turns off the third switching circuit 402 to input the amplified pixel signal to the second analog-to-digital converter 211. The first adc 210 converts the pixel signal into a corresponding digital signal, and outputs the digital signal to the image processor 209. The image processor 209 performs a preset operation on the digital signal to obtain image data, and adds an array identifier representing the first pixel array 202 to the image data. Similarly, the second analog-to-digital converter 211 converts the pixel signal into a corresponding digital signal, and outputs the digital signal to the image processor 209. The image processor 209 performs a preset operation on the digital signal to obtain image data, and adds an array identifier representing the second pixel array 206 to the image data. The image processor 209 outputs the image data carrying the array identifier to the corresponding input/output interface, so as to output the image data carrying the array identifier in accordance with a preset format or specification.
The technical scheme of the embodiment of the application provides a photosensitive chip, which reduces circuits on a substrate by sharing a column selection circuit, a column reading circuit, an analog signal amplifier and an image processor by two pixel arrays, thereby reducing the sizes of the photosensitive chip and a camera module. Or, the area of the photosensitive area is increased on the basis of keeping the size of the photosensitive chip unchanged, so that the quality of a photographed image can be improved.
Fig. 5 is a block diagram of still another embodiment of a photosensitive chip. The photosensitive chip comprises a column selection circuit, a column reading circuit, an analog signal amplifier, an analog-to-digital converter, an image processor and at least two input/output interfaces. The input end of the analog signal amplifier 401 is electrically connected to the output end of the column read circuit 301, the output end of the analog signal amplifier 401 is electrically connected to the input end of the analog-to-digital converter 501, the output end of the analog-to-digital converter 501 is electrically connected to the image processor 209, and the output end of the image processor 209 is electrically connected to the first I/O interface 214 and the second I/O interface 215, respectively.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photosensitive chip, so that the timing control circuit sequentially outputs a scan control pulse to each row scanning circuit, and outputs a column selection control signal to the column selection circuit 302, so as to sequentially read the pixel signals in each pixel array by the column reading circuit 301. The column reading circuit 301 outputs a pixel signal to the analog signal amplifier 401 to perform amplification processing, and obtains an amplified pixel signal, which is input to the analog-to-digital converter 501. The analog-to-digital converter 501 converts the amplified pixel signal into a corresponding digital signal and outputs the digital signal to the image processor 209. The image processor 209 records the number of received digital signals and compares the number to a predetermined threshold. If the number of digital signals received by the image processor 209 is equal to the preset threshold, it is determined that the next read digital signal belongs to the next pixel array, a first array identifier in the preset identifier set is obtained, and the first array identifier is added to the image data. Then, the count value is cleared, and the read digital signal is counted again. The preset threshold may be a set of at least two positive integers arranged in sequence, and the value is determined by the reading sequence of the pixel array and the number of pixel units included in the pixel array. Taking two pixel arrays of 3×4 as an example, the first pixel array 202 is read first, which includes 12 pixel units, and the first number in the set corresponding to the preset threshold is 12, and since the second pixel array 206 also includes 12 pixel units, the second number is 12. The preset threshold is [12,12], and when the image processor 209 works, a first value is obtained as the preset threshold, and when the number of the recorded pixel signals is equal to the first value, a second value is taken as the preset threshold. The array identifiers in the preset identifier set are determined according to the reading sequence of each pixel array, and can be identifiers for uniquely identifying the pixel arrays.
The image processor 209 outputs the image data carrying the array identifier to the corresponding input/output interface, so as to output the image data carrying the array identifier in accordance with a preset format or specification.
The technical scheme of the embodiment of the application provides a photosensitive chip, which further reduces the circuits on the substrate by sharing a column selection circuit, a column reading circuit, an analog signal amplifier, an analog-to-digital converter and an image processor by two pixel arrays, thereby saving the space occupied by the chip in a camera module.
Fig. 6 is a block diagram of still another embodiment of a photosensitive chip. The photosensitive chip comprises a column selection circuit, a column reading circuit, an analog signal amplifier, an analog-to-digital converter, an image processor and an input/output interface. The input end of the analog signal amplifier 401 is electrically connected to the output end of the column read circuit 301, the output end of the analog signal amplifier 401 is electrically connected to the input end of the analog-to-digital converter 501, the output end of the analog-to-digital converter 501 is electrically connected to the image processor 209, and the output end of the image processor 209 is electrically connected to the I/O interface (i.e., input/output interface) 601.
When the camera on command is detected, the processor (e.g., CPU) outputs a control signal to the timing control circuit of the photosensitive chip, so that the timing control circuit sequentially outputs a scan control pulse to each row scanning circuit, and outputs a column selection control signal to the column selection circuit 302, so as to sequentially read the pixel signals in each pixel array by the column reading circuit 301. The column reading circuit 301 outputs a pixel signal to the analog signal amplifier 401 to perform amplification processing, and obtains an amplified pixel signal, which is input to the analog-to-digital converter 501. The analog-to-digital converter 501 converts the amplified pixel signal into a corresponding digital signal and outputs the digital signal to the image processor 209. The image processor 209 performs preprocessing on all pixel signals corresponding to each pixel array to obtain image data corresponding to the pixel array, and adds an array identifier at the tail of the image data. The image processor 209 sequentially outputs the image data carrying the array identifier to the queue corresponding to the I/O interface 601. The I/O interface 601 determines, from the array identifier read first to the tail of the queue, that the image data read next is the image data corresponding to the first pixel array 202 (until the array identifier corresponding to the second pixel array is read). The I/O interface 601 reads the image data from the queue, adjusts the format of the image data corresponding to the first pixel array 202 according to the set format, and outputs the image data with the adjusted format and the array identifier corresponding to the first pixel array 202. Similarly, the I/O interface 601 determines, from the array identifier corresponding to the second pixel array 206 read in the queue, that the image data read again below is the image data corresponding to the second pixel array 206 (until the array identifier corresponding to the third pixel array is read). The I/O interface 601 reads the image data from the queue, adjusts the format of the image data corresponding to the second pixel array 206 according to the set format, and outputs the image data with the adjusted format and the array identifier corresponding to the second pixel array 206. And the like until the image data of the last first pixel array and the array identification are output.
The technical scheme of the embodiment of the application provides a photosensitive chip, which further reduces the circuits on the substrate by sharing a column selection circuit, a column reading circuit, an analog signal amplifier, an analog-to-digital converter, an image processor and an input-output interface circuit by two pixel arrays, thereby saving the space occupied by the chip in a camera module.
In some embodiments, the integrated circuit of the photosensitive chip further includes a correlated double sampling circuit, and fig. 7 is a block diagram of still another structure of the photosensitive chip according to an embodiment of the present application. The correlated double sampling circuit comprises a first reset control circuit 305 and a second reset control circuit 306 for resetting the pixels in the first pixel array 202 and the pixels in the second pixel array 206, respectively, after receiving a reset signal. The design has the advantages that the reset of the pixels and the integrated signals after pixel integration are collected, the difference value between the integrated signals and the reset signals is calculated and output to an analog signal amplifier, and the fixed pattern noise (including column fixed pattern operation and pixel fixed pattern noise) is eliminated through a correlated double sampling technology. In this case, due to the limitation of the accuracy of the manufacturing process, the pixel signal read out by each column readout circuit has a certain error offset, which is called column fixed pattern noise. In addition, there is also a difference between pixels due to manufacturing process errors, which is called pixel fixed pattern noise.
Illustratively, the light sensing chip includes a first pixel array 202, a second pixel array 206, and an integrated circuit. The integrated circuit includes:
the interface circuit 701 is configured to load external control data into the set of on-chip memory registers.
The timing control circuit 702 is configured to generate internal timing signals such as integral reading and resetting of the pixel unit according to the data set by the internal register, and output the internal timing signals to the corresponding circuits in the form of pulse signals.
The first row scan circuit 201 (including the first row address decoder 2011 and the first row shift register 2012) is electrically connected to the timing control circuit 702 and the first pixel array 202, respectively, and is configured to output a row scan signal to the first pixel array 202 or a reset control signal to the first reset control circuit 705 under the control of the timing control circuit 702.
The second row scanning circuit 205 (including a second row address decoder 2051 and a second row shift register 2052) is electrically connected to the timing control circuit 702 and the second pixel array 206, respectively, and is configured to output a row scanning signal to the second pixel array 206 or output a reset control signal to the second reset control circuit 706 under the control of the timing control circuit 702.
The first reset control circuit 705 is electrically connected to the first pixel array 202, and is configured to perform a reset process on pixels in a current row according to a reset control signal output from the first row scanning circuit 201 (including the first row address decoder 2011 and the first row shift register 2012). Wherein the current row is the row to be read in the current pixel array.
The second reset control circuit 706 is electrically connected to the second pixel array 206, and is configured to perform a reset process on pixels in a current row according to a reset control signal output from the second row scanning circuit 205 (including the second row address decoder 2051 and the second row shift register 2052).
For ease of understanding, a classical correlated double sampling circuit is used to sample and reset a pixel cell, illustrating the manner in which fixed pattern noise is eliminated by correlated double sampling techniques. Fig. 8 is a circuit schematic of a classical correlated double sampling circuit in the related art. As shown in fig. 8, the pixel units are packedCurrent source I for photodiode ph Capacitance C d And resistance R d To be equivalently simulated, the reset switch is an NMOS transistor MR. NMOS transistors MLN and MIN form a source follower amplifier, PMOS transistors MSR and MSHS are two signal transmission gates and capacitor C R And C s Two sampling capacitors are formed, and NMOS transistors MS1 and MS2 are used for resetting the sampling capacitors.
Fig. 9 is a timing diagram of the operation of the correlated double sampling circuit. As shown in fig. 9, the related double sampling circuit works as follows:
(1) Sampling a reset signal Vr: time t is from 0 to t 0 In the process, the reset switching tube MR is conducted under the control of the reset control signal VR, the n-point potential becomes high level, and VX and VLN keep high level; at time t0, the photosensitive chip starts exposure, and n-point voltage is sampled to the capacitor CR through the source follower and the transmission gate MSR, and the output reset signal Vr.
(2) Sampling the integrated signal Vs: in the process from t1 to t2, the two transmission gates are disconnected, no signal sampling is performed, and the integral voltage at the n point gradually drops due to the action of the photocurrent Iph. At time t2, the transmission gate MSHS is turned on, and the n-point voltage is sampled onto the capacitor CS by the source follower and the transmission gate, and the output integrated voltage signal Vs.
(3) At time t3, the signals Vr and Vs on the two sampling capacitors are differenced, and the difference is outputted as an effective signal through the column bus.
The remaining circuits such as the analog signal amplifier and the analog-to-digital converter are similar to those of the above embodiments, and will not be repeated here.
The technical scheme of the embodiment of the application provides a photosensitive chip, which further comprises a correlated double sampling circuit, wherein the correlated double sampling circuit is used for collecting integral signals and reset signals of pixels in the pixel array, calculating the difference value between the integral signals and the reset signals, and outputting the difference value to the analog signal amplifier, so that fixed mode noise can be effectively eliminated.
The embodiment of the application also provides a camera module, which comprises the photosensitive chip provided by the embodiment, and a multi-camera system is formed by one photosensitive chip with at least two pixel arrays. The camera module may include a plurality of rear camera modules and/or a plurality of front camera modules having the photosensitive chip provided in the above embodiments. The camera module comprises:
The photosensitive chip with the structure described in the above embodiment is soldered on the circuit board. The precision of the semiconductor manufacturing process is far higher than that of the module manufacturing process, and two or more pixel arrays are prepared on the same substrate to form a plurality of photosensitive areas, so that the flatness of the chip, the relative deviation of at least two photosensitive areas, the relative inclination angle and other angles can be improved from millimeter level to micrometer level.
And the number of the lenses is consistent with that of the pixel arrays of the photosensitive chip. The lenses are fixed through the lens base to form a lens, the lens base and the voice coil motor form a lens assembly, and the lens assembly is fixed on the circuit board through the bracket to form a multi-camera system. It should be noted that the multi-camera system may be a camera system formed by a plurality of rear camera modules and/or a plurality of front camera modules.
Fig. 10 is a schematic structural diagram of a camera module according to an embodiment of the present application. As shown in fig. 10, the camera module includes: the first lens assembly 1010, the second lens assembly 1020, the bracket 1030, and the photo-sensing chip 1040. The first lens assembly 1010 includes a first lens, a first lens base, and a first motor, so that the first lens slides in the first lens barrel under the driving of the first motor to adjust a focal length; the second lens assembly 1020 comprises a second lens, a second lens seat and a second motor, so that the second lens slides in the second lens barrel under the drive of the second motor to adjust the focal length. The photo-sensing chip 1040 includes a first pixel array 1041 and a second pixel array 1042, and the circuit structure is shown in the above embodiments and will not be described herein. And the photosensitive chip 1040 is welded on the circuit board 1050, the size of the circuit board 1050 is larger than that of the photosensitive chip 1040, and the support 1030 is fixedly connected with the circuit board 1050 to form the packaging structure of the camera module.
Optionally, the first lens assembly 1010 further includes a first infrared filter for filtering infrared light signals collected by the first lens. The second lens assembly 1020 further comprises a second infrared filter for filtering infrared light signals collected by the second lens.
Alternatively, the first infrared filter may be further disposed separately from the first lens assembly 1010, and the second infrared filter may be further disposed separately from the second lens assembly 1020.
The embodiment of the application also provides electronic equipment, which is provided with the camera module. The electronic device may be a terminal with a camera, such as a smart phone, a PAD (tablet personal computer), a notebook computer, and an intelligent wearable device. Taking a smart phone as an example of a structure of an electronic device, fig. 11 is a block diagram of a structure of a smart phone according to an embodiment of the present application. As shown in fig. 11, the smart phone may include: memory 1101, a central processing unit (Central Processing Unit, CPU) 1102 (also called a processor, hereinafter CPU), a peripheral interface 1103, RF (Radio Frequency) circuitry 1105, audio circuitry 1106, speakers 1111, a touch screen 1112, a multi-camera system 1113, a power management chip 1108, an input/output (I/O) subsystem 1109, other input/control devices 1110, and external ports 1104, which communicate via one or more communication buses or signal lines 1107.
The memory 1101, the memory 1101 being accessible by the CPU1102, peripheral interface 1103, etc., the memory 1101 may comprise high speed random access memory, and may also comprise non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other volatile solid state storage devices.
A peripheral interface 1103, said peripheral interface 1103 may connect input and output peripherals of the device to the CPU1102 and the memory 1101.
I/O subsystem 1109, which I/O subsystem 1109 may connect to peripheral interfaces 1103 input/output peripherals on the device, such as touch screen 1112 and other input/control devices 1110. The I/O subsystem 1109 may include a display controller 11091 and one or more input controllers 11092 for controlling other input/control devices 1110. Wherein one or more input controllers 11092 receive electrical signals from other input/control devices 1110 or send electrical signals to other input/control devices 1110, other input/control devices 1110 may include physical buttons (push buttons, rocker buttons, etc.), dials, slider switches, joysticks, click wheels. It should be noted that the input controller 11092 may be connected to any one of the following: a keyboard, an infrared port, a USB interface, and a pointing device such as a mouse.
A touch screen 1112, the touch screen 1112 being an input interface and an output interface between the user terminal and the user, displaying visual output to the user, which may include graphics, text, icons, video, etc.
The display controller 11091 in the I/O subsystem 1109 receives electrical signals from the touch screen 1112 or sends electrical signals to the touch screen 1112. The touch screen 1112 detects a contact on the touch screen, and the display controller 11091 converts the detected contact into an interaction with a user interface object displayed on the touch screen 1112, i.e., to enable human-machine interaction, the user interface object displayed on the touch screen 1112 may be an icon running a game, an icon networked to a corresponding network, or the like. It is noted that the device may also include a light mouse, which is a touch sensitive surface that does not display a visual output, or an extension of a touch sensitive surface formed by a touch screen.
The RF circuit 1105 is mainly used for establishing communication between the mobile phone and the wireless network (i.e. network side), and implementing data receiving and sending between the mobile phone and the wireless network. Such as sending and receiving short messages, emails, etc. Specifically, the RF circuit 1105 receives and transmits RF signals, also referred to as electromagnetic signals, the RF circuit 1105 converts electrical signals into electromagnetic signals or converts electromagnetic signals into electrical signals, and communicates with a communication network and other devices through the electromagnetic signals. The RF circuitry 1105 may include known circuitry for performing these functions including, but not limited to, an antenna system, an RF transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a CODEC (COder-DECoder) chipset, a subscriber identity module (Subscriber Identity Module, SIM), and so forth.
The audio circuit 1106 is mainly used for receiving audio data from the peripheral interface 1103, converting the audio data into an electrical signal, and transmitting the electrical signal to the speaker 1111.
A speaker 1111 for reproducing voice signals received from the wireless network by the mobile phone through the RF circuit 1105 into sound and playing the sound to the user.
The power management chip 1108 is used for supplying power and managing power for the hardware connected with the CPU1102, the I/O subsystem and the peripheral interfaces.
The multi-camera system 1113 includes a plurality of rear camera modules and/or a plurality of front camera modules, and is configured to acquire image data of different view angles, different depths of field, and the like of the target object, and transmit the image data to the memory 1101 through the peripheral interface 1103 for storage, so as to be called by the CPU 1102. Because a plurality of photosensitive areas of the multi-camera system are formed on the same substrate and can share part of the integrated circuit, the size of the camera module is smaller than that of a camera module prepared by a separated photosensitive chip, and the volume of the multi-camera system is reduced.
It should be understood that the illustrated smartphone 1100 is merely one example of an electronic device, and that the smartphone 1100 may have more or fewer components than shown in the figures, may combine two or more components, or may have a different configuration of components. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Therefore, while the present application has been described in connection with the above embodiments, the present application is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, the scope of which is defined by the scope of the appended claims.
Claims (9)
1. The photosensitive chip comprises a substrate, wherein the substrate comprises at least two pixel arrays and an integrated circuit, and is characterized in that the integrated circuit comprises an image processor, and the at least two pixel arrays multiplex the image processor;
the etching process is adopted to enable column buses of at least two pixel arrays to be correspondingly and electrically connected, and the at least two pixel arrays multiplex a column reading circuit;
at least one analog signal amplifier is connected in series with the column reading circuit and is used for amplifying the pixel signals read in sequence and outputting the amplified pixel signals to corresponding analog-to-digital converters;
The image processor records the number of the acquired pixel signals, determines that the source of the pixel signals changes when the number exceeds a set threshold value, and acquires the next adjacent array identifier from an array set, wherein the set threshold value is a set of at least two positive integers which are sequentially arranged, the set threshold value is determined by the reading sequence of the pixel arrays and pixel units contained in each pixel array, and the array set contains the array identifiers which are sequentially arranged.
2. The photosensitive chip of claim 1, wherein the image processor is configured to perform a preset process on pixel signals read by at least two pixel arrays to obtain image data, and add an array identifier to the image data according to a source of the pixel signals, so as to implement multiplexing of the at least two pixel arrays by the image processor.
3. The light-sensing chip of claim 1, wherein the integrated circuit further comprises at least two row scan circuits outputting row scan signals in a serial operation mode to realize sequential scanning of the at least two pixel arrays.
4. The light-sensing chip of claim 1, wherein the integrated circuit further comprises at least two column read circuits, at least one analog signal amplifier, and at least one analog-to-digital converter;
the at least two column reading circuits are electrically connected with the analog signal amplifier and are used for sequentially reading pixel signals on a column bus in the pixel array and outputting the pixel signals to the analog signal amplifier;
the analog signal amplifier is used for amplifying the pixel signals and outputting the amplified pixel signals to the corresponding analog-to-digital converter.
5. The light-sensing chip according to claim 1 or 4, wherein the at least two pixel arrays multiplex analog signal amplifiers, the number of the analog-to-digital converters being the same as the number of the pixel arrays;
and the integrated circuit further comprises a switching circuit which is connected in series between the analog-to-digital converter and the analog signal amplifier and is used for switching the analog-to-digital converter which is communicated with the analog signal amplifier.
6. The light-sensing chip of claim 5, wherein the integrated circuit further comprises a timing control circuit electrically connected to the switching circuit for generating switching pulses based on a read sequence of at least two pixel arrays and a read time of each pixel array, and outputting the switching pulses to the switching circuit, respectively, to control the switching circuit to be turned on or off.
7. The photosensitive chip of claim 2, wherein said integrated circuit further comprises at least one input-output interface;
the input/output interface is used for respectively carrying out format adjustment on the image data according to a set format and outputting the image data and the array identifier after format adjustment.
8. A camera module comprising the photosensitive chip according to any one of claims 1 to 7.
9. An electronic device having the camera module of claim 8.
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| CN1523878A (en) * | 2003-02-18 | 2004-08-25 | CMOS image sensor having reduced numbers of column readout circuits | |
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| CN1523878A (en) * | 2003-02-18 | 2004-08-25 | CMOS image sensor having reduced numbers of column readout circuits | |
| CN102572320A (en) * | 2011-11-28 | 2012-07-11 | 北京思比科微电子技术股份有限公司 | Method for reducing height of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor module and CMOS image sensor module |
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