CN109167940A - A kind of sensitive chip, camera module and electronic equipment - Google Patents
A kind of sensitive chip, camera module and electronic equipment Download PDFInfo
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- CN109167940A CN109167940A CN201810967186.6A CN201810967186A CN109167940A CN 109167940 A CN109167940 A CN 109167940A CN 201810967186 A CN201810967186 A CN 201810967186A CN 109167940 A CN109167940 A CN 109167940A
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- sensitive chip
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- pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The embodiment of the present application discloses a kind of sensitive chip, camera module and electronic equipment.The sensitive chip includes integrated circuit and at least two pixel arrays on substrate；The integrated circuit includes analog signal amplifier, and at least two pixel array is multiplexed the analog signal amplifier.Using the technical solution of the embodiment of the present application, using same wafer as substrate, it designs over the substrate and forms the sensitive chip for more taking the photograph system, pass through multiple pixel array multiplexed analog signal amplifiers, the circuit on substrate can be reduced, in turn, it can reduce the size of sensitive chip and camera module.
Description
Technical field
The invention relates to semiconductor device art more particularly to a kind of sensitive chips, camera module and electronics
Equipment.
Background technique
Electronic equipment with multiple camera modules can control different cameras respectively and execute different function, thus
So that the picture captured by camera has more contents and is more clear, imaging is exquisiter, color is more bright-coloured.
However, the systems of taking the photograph with multiple camera modules are usually to pass through multiple camera modules more in the related technology
What bracket assembled obtained.As shown in Figure 1, first camera module 10 and second camera mould group 20 are assembled by bracket 130
Take the photograph system at more.Each camera module includes sensitive chip (140,150) and lens assembly (110,120), wherein lens group
Part (110,120) includes camera lens, microscope base and motor.Sensitive chip (140,150) is welded on wiring board 160, and sensitive chip
Imaging area (141,151) on (140,150) is located at the upright projection region of camera lens (110,120).Due to using mould group rank
Assembling mode, production, the stated accuracy requirement of position between mould group may be unable to satisfy.Such as binocular ranging, image co-registration field
Scape, the deviation of small distance or angle can all cause biggish deviation to final result.
Summary of the invention
The embodiment of the present application provides a kind of sensitive chip, camera module and electronic equipment, can optimize in the related technology
The design schemes for taking the photograph system more.
In a first aspect, the embodiment of the present application provides a kind of sensitive chip, including integrated circuit and on substrate extremely
Few two pixel arrays；The integrated circuit includes analog signal amplifier, and at least two pixel array is multiplexed the mould
Quasi- signal amplifier.
Second aspect, the embodiment of the present application also provides a kind of camera module, which includes such as above-mentioned the
Sensitive chip described in one side.
The third aspect, the embodiment of the present application also provides a kind of electronic equipment, which has such as above-mentioned second party
Camera module described in face.
The embodiment of the present application provides a kind of sensitive chip scheme, at least two pictures including integrated circuit and on substrate
Pixel array；The integrated circuit includes analog signal amplifier, and at least two pixel array is multiplexed the analog signal and puts
Big device.By the technical solution of the embodiment of the present application, using same wafer as substrate, designs over the substrate and form take the photograph more and be
The sensitive chip of system realizes that the position for completing the photosensitive areas for taking the photograph system in the stage by semiconductors manufacture sensitive chip is marked more
It is fixed, improve the assembly precision for more taking the photograph system.In addition, the sensitive chip has the pixel array for the number for more taking the photograph system requirements,
And multiple pixel array multiplexed analog signal amplifiers, to reduce the circuit on substrate, in turn, can reduce sensitive chip and
The size of camera module.Meanwhile at least two pixel array share an amplifying circuit of analog signal, can be improved image effect
The consistency of fruit avoids having differences the feelings for causing the image effect of final output to have differences because of amplifying circuit of analog signal
Condition, saving adjustment image effect makes the effect consistent time, thus, shorten the processing time of image data.
Detailed description of the invention
Fig. 1 is traditional double structural schematic diagrams for taking the photograph system；
Fig. 2 is a kind of structural block diagram of sensitive chip provided by the embodiments of the present application；
Fig. 3 is the structural block diagram of another sensitive chip provided by the embodiments of the present application；
Fig. 4 is the circuit diagram of correlated double sampling circuit classical in the related technology；
Fig. 5 is the working timing figure of correlated double sampling circuit；
Fig. 6 is a kind of structural block diagram of sensitive chip provided by the embodiments of the present application；
Fig. 7 is a kind of structural schematic diagram of camera module provided by the embodiments of the present application；
Fig. 8 is a kind of structural block diagram of smart phone provided by the embodiments of the present application.
Specific embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the application, rather than the restriction to the application.It also should be noted that in order to just
Part relevant to the application is illustrated only in description, attached drawing rather than entire infrastructure.
It should be noted that due to the continuous improvement of semiconductor technology and technological level, imaging sensor (Image
Sensor) as a kind of elemental device of acquisition of vision information, because of the expansion of its acquisition, the conversion and visual performance that are able to achieve information
Exhibition provides intuitive, multi-level, abundant in content visible image information, and has and be more and more widely used.It answers in the related technology
It mainly include charge-coupled device (CCD) imaging sensor and complementary metal oxide with most commonly used solid state image sensor
Semiconductor (CMOS) imaging sensor.The sensitive chip of the embodiment of the present application can be the imaging sensor of above two type.
There are at least two pixel arrays in the semiconductor substrate of the sensitive chip, and realize the collection of sensitive chip function
At circuit.The integrated circuit includes that analog signal amplifier (can think that the analog signal that can be achieved on signal amplification is put
Big circuit), above-mentioned at least two pixel array is multiplexed the amplifying circuit of analog signal.It should be noted that the embodiment of the present application
According to setting when at least two pixel array carry out sequence reading of ordered pair, and to each pixel array using progressive scan by column
The mode of reading thereby guarantees that and just reads after being read by the corresponding picture element signal of all pixels point in the first pixel array
Picture element signal in two pixel arrays.The picture element signal is exported after carrying out signal amplification to amplifying circuit of analog signal, then defeated
Out to analog-digital converter.It is the imaging area of image it should be noted that pixel array, containing x*y (row * column) imaging pixel point,
Each pixel all has photoperceptivity, can convert optical signals to corresponding analog electronic signal.
Integrated circuit includes line-scan circuit, and pixel array is scanned by switching tube (triode or field-effect tube) and the row
Circuit electrical connection, output line scan signals to the pixel array.It is understood that the quantity of line-scan circuit can be with pixel
The quantity of array is identical, and the first line-scan circuit is electrically connected with the first pixel array, the second line-scan circuit and the second pixel battle array
Column electrical connection ... ..., line n scanning circuit is electrically connected with the n-th pixel array, wherein the value of n by taking the photograph the pixel battle array of system more
The quantity of column determines.Optionally, above-mentioned at least two line-scan circuit exports line scan signals according to work in series mode, realizes
At least two pixel array of sequential scan.
It should be noted that multiple sensitive chips can be formed on same wafer using semiconductor device fabrication processes,
And it is cut one by one.Wherein, sensitive chip includes at least two pixel arrays and corresponding integrated circuit.It can be to avoid correlation
The problem of taking the photograph big system mould group grade assembly difficulty, hardly possible debugging in technology more.In the related technology, the camera module for more taking the photograph system is
Multiple sensitive chips correspond to a plurality of lenses, and each camera has function independent, do not have function common portion between each other
Point, since chip is located on respective wiring board, the placed angle of each chip, gradient are variant, will increase
Downstream equipment and the difficulty of debugging.
In order to make it easy to understand, introducing the structure of sensitive chip by taking cmos image sensor as an example.Fig. 2 is the embodiment of the present application
A kind of structural block diagram of the sensitive chip provided.Sensitive chip shown in Fig. 2 includes the first pixel array 202, the second pixel battle array
Column 206 and integrated circuit, wherein integrated circuit includes the first line-scan circuit being electrically connected with the first pixel array 202
201 and first row reading circuit 203, the second line-scan circuit 205 for being electrically connected with the second pixel array 206 and secondary series read
Circuit 206, analog signal amplifier 209, the first analog-digital converter 210 and the second analog-digital converter 211.First row reading circuit
203 are electrically connected with analog signal amplifier 209 with secondary series reading circuit 207, total for sequentially reading column in pixel array
Picture element signal on line, and the picture element signal is exported to the analog signal amplifier 209.Analog signal amplifier 209 is distinguished
It is electrically connected with the first analog-digital converter 210 and the second analog-digital converter 211.First analog-digital converter 210 and the first image processing
Device electrical connection, the first image processor are electrically connected with the first I/O interface.Second analog-digital converter 211 and the second image processor
213 electrical connections, the second image processor are electrically connected with the 2nd I/O interface.Wherein, the first image processor, the first I/O interface,
Second image processor and the 2nd I/O interface can integrate on wiring board.
When detecting camera open command, processor (such as CPU) outputs control signals to the timing control of sensitive chip
Circuit processed, so that sequential control circuit exports scan control pulse to the first line-scan circuit 201, and, output column selection control
Signal is to the first column select circuit 204.First line-scan circuit 201 exports line scan signals extremely according to scan control pulse line by line
First pixel array 202.First column select circuit 204, for the column bus 216 according to column selection control signal gating column to be read
With first row reading circuit 203.Wherein, scan control pulse for control the first line-scan circuit 201 first time period to
The first row of first pixel array exports line scan signals, to realize that the field-effect tube being electrically connected with the pixel of the first row is connected,
And in the first time period, column selection controls signal and exports Continuity signal to column bus for controlling the first column select circuit 204
It realizes and reads on column bus one by one to be respectively turned on each field-effect tube with the field-effect tube between first row reading circuit 203
Picture element signal, and the picture element signal is exported to analog signal amplifier 209.Reading last column pixel of the first row
Picture element signal after, export scanning signal to the second row, be connected with realizing with the field-effect tube of the pixel of the second row electrical connection, and
The picture element signal on column bus is read one by one.The rest may be inferred, until read complete the first pixel array in last line last
The picture element signal of column pixel.
It is completed in the first pixel array after the picture element signal of last column pixel of last line reading, sequential control circuit
Scan control pulse is exported to the second line-scan circuit 205, and, output column selection controls signal to the second column select circuit 208.
Second line-scan circuit 205 exports line scan signals to the second pixel array 206 according to scan control pulse line by line.Second column selection
Circuit 208 is selected, for controlling the column bus 216 and secondary series reading circuit 207 of a signal gating column to be read according to column selection.
Wherein, scan control pulse is for controlling the first row of second line-scan circuit 205 in second time period to the second pixel array
Line scan signals are exported, to realize that the field-effect tube being electrically connected with the pixel of the first row is connected, and in the second time period, column
Selected control signal for control the second column select circuit 208 export Continuity signal to column bus and secondary series reading circuit 207 it
Between field-effect tube realize the picture element signal read on column bus one by one to be respectively turned on each field-effect tube, and by the picture
Plain signal is exported to analog signal amplifier 209.After the picture element signal for having read last column pixel of the first row, to the second row
Scanning signal is exported, to realize that the field-effect tube being electrically connected with the pixel of the second row is connected, and reads the picture on column bus one by one
Plain signal.The rest may be inferred, until reading the picture element signal for completing last column pixel of last line in the second pixel array.
Analog signal amplifier 209, for amplifying processing to the picture element signal, and by amplified picture element signal
It exports to corresponding analog-digital converter.It should be noted that the quantity of analog-digital converter can be identical as the quantity of pixel array,
Between analog signal amplifier 209 and each analog-digital converter distinguish tandem tap circuit, the switching circuit can to mould
The analog-digital converter that quasi- signal amplifier 209 is connected switches over.Illustratively, in analog signal amplifier 209 and the first mould
It connects first switch circuit (such as can be transistor, field-effect tube) between number converter 210, in the first pixel array
Analog signal amplifier 209 and the first analog-digital converter 210 are connected in reading process.In addition, analog signal amplifier 209 with
Series connection second switch circuit between second analog-digital converter 211, for connecting simulation in the reading process of the second pixel array
Signal amplifier 209 and the second analog-digital converter 211.
It is corresponding to receive amplified first pixel array that analog signal amplifier 209 exports for first analog-digital converter 210
Picture element signal, which is converted to digital signal, output with the first analog-digital converter 210 to being electrically connected
The first image processor.
It is corresponding to receive amplified second pixel array that analog signal amplifier 209 exports for second analog-digital converter 211
Picture element signal, which is converted to digital signal, output with the second analog-digital converter 211 to being electrically connected
The second image processor.
First image processor receives the digital signal of the first analog-digital converter 210 output, according to the chip of sensitive chip
Defined function carries out default processing to digital signal, and treated, and image data according to certain format or is standardized through the first I/O
Interface is exported to back-end platform.It should be noted that including AEC (auto-exposure control), AGC to the default processing of digital signal
(automatic growth control), AWB (automatic white balance), colour correction, Lens Shading (camera lens shadow correction), Gamma correction,
Dispel bad point, Auto Black Level (Automatic Black Level correction) and Auto White Level (automatic white level correction) etc.
Etc. functions processing.
Second image processor receives the digital signal of the second analog-digital converter 211 output, according to the chip of sensitive chip
Defined function carries out default processing to digital signal, and treated, and image data according to certain format or is standardized through the 2nd I/O
Interface is exported to back-end platform.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, including integrated circuit and on substrate at least
Two pixel arrays；The integrated circuit includes analog signal amplifier, and at least two pixel array is multiplexed the simulation
Signal amplifier.It designs and is formed over the substrate using same wafer as substrate by the technical solution of the embodiment of the present application
It takes the photograph the sensitive chip of system more, realizes and complete the location positions for taking the photograph system in the stage by semiconductors manufacture sensitive chip more,
Improve the assembly precision for more taking the photograph system.In addition, the sensitive chip has the pixel array for the number for more taking the photograph system requirements, and more
A pixel array multiplexed analog signal amplifier in turn, can reduce sensitive chip and camera shooting to reduce the circuit on substrate
The size of head mould group.Meanwhile at least two pixel array share an amplifying circuit of analog signal, image effect can be improved
Consistency avoids having differences the case where causing the image effect of final output to have differences because of amplifying circuit of analog signal, section
Saving adjustment image effect makes the effect consistent time, thus, shorten the processing time of image data.
Fig. 3 is the structural block diagram of another sensitive chip provided by the embodiments of the present application.The collection of sensitive chip shown in Fig. 3
It further include correlated double sampling circuit at circuit, which includes that the first reset control circuit 305 and second resets
Control circuit 306, for after receiving reset signal respectively to the pixel and the second pixel battle array in the first pixel array 202
Pixel in column 204 is resetted.The reset for being advantageous in that acquisition pixel and the integral letter after pixel integration are designed in this way
Number, it calculates the difference of integrated signal and reset signal and exports to analog signal amplifier, eliminated by Correlated Double Sampling
Fixed pattern noise (including the operation of column fixed mode and pixel fixed pattern noise).Wherein, due to manufacture craft accuracy
Limitation, the picture element signal that each row reading circuit is read can there is a certain error offset, this offset be referred to as arrange it is solid
Mould-fixed noise.In addition, there is also manufacture craft error bring differences, referred to as pixel stent between pixel and pixel
Formula noise.
Illustratively, sensitive chip includes the first pixel array 202, the second pixel array 206 and integrated circuit.The collection
Include: at circuit
Interface circuit 301, for external control data to be loaded into chip memory register group.
Sequential control circuit 302, the integral that the data for being arranged according to internal register generate pixel unit read, are multiple
The internal timing signals such as position, and exported in the form of pulse signal to corresponding circuit.
First line-scan circuit (including the first row address decoder 3031 and first line shift register 3032) respectively with
Sequential control circuit 302 and the electrical connection of the first pixel array 202, sweep for exporting row under the control of sequential control circuit 302
Retouching signal to the first pixel array 202, or output reseting controling signal can distinguish real to the first reset control circuit 305
Existing selection and row reset function.
Second line-scan circuit (including the second row address decoder 3041 and second line shift register 3042) respectively with
Sequential control circuit 302 and the electrical connection of the second pixel array 206, sweep for exporting row under the control of sequential control circuit 302
Retouching signal to the second pixel array 206, or output reseting controling signal can distinguish real to the second reset control circuit 306
Existing selection and row reset function.
First reset control circuit 305 is electrically connected with the first pixel array 202, is used for according to reseting controling signal to current
Pixel in row carries out reset processing.Wherein, current line is a line to be read in current pixel array.
Second reset control circuit 306 is electrically connected with the second pixel array 206, is used for according to reseting controling signal to current
Pixel in row carries out reset processing.
In order to make it easy to understand, one pixel unit is sampled and is reset to using classical correlated double sampling circuit
Example illustrates in such a way that Correlated Double Sampling eliminates fixed pattern noise.Fig. 4 is correlation classical in the related technology
The circuit diagram of dual-sampling circuit.As shown in figure 4, the photodiode for including by pixel unit current source Iph, capacitor Cd
With resistance RdCarry out equivalent simulation, reset switch is NMOS transistor MR.NMOS tube MLN and MIN constitute source follower amplifier,
PMOS tube MSR and MSHS are two signal transmission gates, capacitor CRAnd CsTwo sampling capacitances are constituted, NMOS tube MS1 and MS2 are used to
It is reset to sampling capacitance.
Fig. 5 is the working timing figure of correlated double sampling circuit.As shown in figure 5, the course of work of correlated double sampling circuit is such as
Under:
(1) sample reset signal Vr: time t is by 0 to t0In the process, reset switch pipe MR is controlled in reseting controling signal VR
Lower conducting, n point current potential become high level, and VX and VLN keep high level；Start to expose in t0 moment sensitive chip, n point voltage is logical
Source follower and transmission gate MSR are crossed, the reset signal Vr of output is sampled on capacitor CR.
(2) sample integration signal Vs: by during t1 to t2, two transmission gates are disconnected, without signal sampling, due to photoelectricity
The effect of stream Iph is gradually reduced the integral voltage at n point.At the t2 moment, transmission gate MSHS conducting, n point voltage passes through at this time
The integrated voltage signal Vs of source follower and transmission gate, output is sampled on capacitor CS.
(3) the signal Vr and Vs on the t3 moment, two sampling capacitances make the difference, and using the difference as useful signal, pass through
Column bus output.
First row reading circuit 203, the picture element signal on column bus for reading the first pixel array 202 is corresponding to be had
Imitate signal.
First column select circuit 204 (including the first column shift register 2041 and first column address decoder 2042), point
It is not electrically connected with sequential control circuit 302 and first row reading circuit 203, for defeated under the control of sequential control circuit 302
It falls out selected control signal, connects first row reading circuit 203 and column bus to control signal according to column selection.
Secondary series reading circuit 207, the picture element signal on column bus for reading the second pixel array 206 is corresponding to be had
Imitate signal.
Second column select circuit 208 (including the second column shift register 2081 and second column address decoder 2082), point
It is not electrically connected with sequential control circuit 302 and secondary series reading circuit 208, for defeated under the control of sequential control circuit 302
It falls out selected control signal, connects secondary series reading circuit 208 and column bus to control signal according to column selection.
Analog signal amplifier 209, for amplifying processing to the picture element signal, and by amplified picture element signal
It exports to corresponding analog-digital converter.
First switch circuit 309 is series between analog signal amplifier 209 and the first analog-digital converter 210, and and when
Sequence control circuit 302 is electrically connected, for leading on-off under the control for the setting pulse signal that sequential control circuit 302 exports
It opens, realizes and connect analog signal amplifier 209 and the first analog-digital converter within the period for reading the first pixel array 202
210, and analog signal amplifier 209 and the first analog-digital converter 210 are disconnected within the period for reading the second pixel array 206
Electrical connection.
Second switch circuit 310 is series between analog signal amplifier 209 and the second analog-digital converter 211, and and when
Sequence control circuit 302 is electrically connected, for leading on-off under the control for the setting pulse signal that sequential control circuit 302 exports
It opens, realizes and disconnect analog signal amplifier 209 and the second analog-digital converter within the period for reading the first pixel array 202
211 electrical connection, and analog signal amplifier 209 and the second modulus are connected within the period for reading the second pixel array 206
Converter 211.
First analog-digital converter 210 is put within corresponding period with analog signal with the second analog-digital converter 211
Big device 209 is connected.The picture element signal that analog signal amplifier 209 exports is received, and picture element signal is converted to digital signal, it is real
The Digital output of existing picture element signal.
The number that corresponding analog-digital converter can be exported by the first image processor and the second image processor respectively
Signal carries out default processing, obtains image data, and by corresponding I/O interface format according to needed for subsequent operation or
Rule handles image data, and treated for output with certain format/rule image data.It should be noted that
First image processor and the second image processor can integrate in sensitive chip, for example, the first image processor and the first mould
Number converter 210 is electrically connected, and receives the number letter for corresponding to the acquisition of the first pixel array of the first analog-digital converter 210 output
Number, default processing is carried out to digital signal and obtains image data, and is exported to the first I/O interface circuit.Second image processor
It is electrically connected with the second analog-digital converter 211, receive the output of the second analog-digital converter 211 corresponds to what the second pixel array acquired
Digital signal carries out default processing to digital signal and obtains image data, and exports to the 2nd I/O interface circuit.Optionally,
One image processor and the second image processor can also be the individual chips being integrated on wiring board.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, further includes correlated double sampling circuit, based on correlation
Dual-sampling circuit acquires the integrated signal and reset signal of pixel in the pixel array, calculate the integrated signal with it is described multiple
The difference of position signal, the difference is exported to the analog signal amplifier, fixed pattern noise can be effectively eliminated.
Fig. 6 is the structural block diagram of another sensitive chip provided by the embodiments of the present application.As shown in fig. 6, the sensitive chip
In 200, the column bus of the first pixel array 202 and the second pixel array 206 is correspondingly connected with, and at least two pixel array is multiple
With column select circuit 650 and column reading circuit 660.It should be noted that the meaning being correspondingly connected with can be the first pixel array
202 first column bus 216 is electrically connected with first column bus 216 of the second pixel array 206, the first pixel array 202
Second column bus 216 be electrically connected with second column bus 216 of the second pixel array 206, the of the first pixel array 202
3 column bus 216 are electrically connected with the 3rd column bus 216 of the second pixel array 206, and the mode of connection can be using etching
The electrical connection of column bus is formed on the substrate in technique.Column bus 216, column select circuit 650 and column reading circuit 660 are separately connected
Three ends of triode or field-effect tube.Sequential control circuit controls column select circuit 650 and successively connects column reading according to setting timing
The column bus corresponding with each pixel unit (the first pixel array 202) of sense circuit 660 is realized and successively reads the first pixel array
The picture element signal of 3 pixel units of the first row in 202；3 pixel units of the second row in the first pixel array 202 are read again
Picture element signal, be then successively read the picture element signal of each pixel unit in the third line and fourth line.Reading the first pixel
In array 202 when the picture element signal of a pixel unit of last column of last line, sequential control circuit controls column selection electricity
The column corresponding with each pixel unit (the second pixel array 206) of column reading circuit 660 are successively connected according to setting timing in road 650
Bus 216 realizes the picture element signal for successively reading 3 pixel units of the first row in the second pixel array 206；Second is read again
The picture element signal of 3 pixel units of the second row in pixel array 206, is then successively read each picture in the third line and fourth line
The picture element signal of plain unit.The corresponding picture element signal of one pixel unit of every reading of column reading circuit 660 is exported to simulation letter
Number amplifier 209, to amplify processing to picture element signal by analog signal amplifier 209.Then, by amplified simulation
Signal inputs corresponding analog-digital converter respectively, obtains corresponding digital signal.Since sensitive chip and image processor are electrically connected
It connects, the number that corresponding analog-digital converter can be exported by the first image processor 610 and the second image processor 620 respectively
Signal carries out image procossing, obtains image data, and passes through I/O interface circuit (including the first I/O interface circuit 630 and the
Two I/O interface circuits 640) format according to needed for subsequent operation or rule image data is handled, output treated
With certain format/rule image data.
Optionally, at least two pixel arrays are multiplexed I/O interface circuit, at the first image processor 610 and the second image
Reason device 620 is electrically connected with analog-digital converter, is preset processing for carrying out to the digital signal of input, is obtained image data, and
Increase array mark for the image data；Input/output interface (i.e. I/O interface circuit) is electrically connected with the image processor,
For carrying out Format adjusting, and output format image data adjusted and battle array to the image data respectively according to setting format
Column mark.For example, the first image processor 610 carries out image procossing to the digital signal that the first analog-digital converter 210 exports, obtain
To image processing, array mark is added for the image processing, to indicate that the image data is read according to by the first pixel array 202
Picture element signal determine.Second image processor 620 carries out at image the digital signal that the second analog-digital converter 211 exports
Reason, obtains image processing, array mark is added for the image processing, to indicate the image data according to by the second pixel array
206 picture element signals read determine.The advantages of this arrangement are as follows passing through the first image processor 610 and the second image processing
Device 620 can also share an I/O interface circuit, can further decrease chip size.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, including makes at least two pixels using etch process
The corresponding electrical connection of the column bus of array, column bus by transistor or field-effect tube respectively with column select circuit and column reading circuit
Electrical connection realizes that two pixel arrays share column select circuit and column reading circuit.To reduce the circuit on substrate, in turn,
It can reduce the size of sensitive chip and camera module.Alternatively, increasing sense on the basis of keeping sensitive chip size constancy
The quality of shooting image can be improved in the area in light region.
The embodiment of the present application also provides a kind of camera module, including such as sensitive chip provided by the above embodiment, realization
It is made up of one piece of sensitive chip with multiple photosensitive regions and takes the photograph system more.The camera module may include having above-mentioned reality
The multiple rear camera mould groups and/or multiple front camera mould groups of the sensitive chip of example offer are provided.The camera module packet
It includes:
The sensitive chip of structure is recorded with above-described embodiment, which is welded on wiring board.Wherein, at least two
A pixel array (i.e. imaging area) is made on the same substrate since the precision of manufacture of semiconductor is significantly larger than module group procedure precision
Standby two or more pixel arrays form multiple photosensitive regions, can by chip flatness, at least two photosensitive regions it is opposite
Deviation, relative tilt angle are angularly improved by grade to micron order.
Camera lens, it is consistent with the quantity of the pixel array of the sensitive chip.Multiple lens form camera lens, mirror by microscope base fixation
Head, microscope base and voice coil motor constitute lens assembly, and lens assembly is fixed by the bracket takes the photograph system in composition on wiring board more.It needs
Illustrate, take the photograph system can be the shooting being made of multiple rear camera mould groups and/or multiple front camera mould groups more
System.
Image processor is electrically connected with the sensitive chip；Optionally, image processor is electrically connected with analog-digital converter
It connects, for carrying out default processing to the digital signal of input, obtains image data, and increase array mark for the image data
Know.
Input/output interface is electrically connected with image processor, for according to setting format respectively to the image data into
Row format adjustment, and output format image data adjusted and array mark.
Fig. 7 is a kind of structural schematic diagram of camera module provided by the embodiments of the present application.As shown in fig. 7, the camera
Mould group includes: the first lens assembly 710, the second lens assembly 720, bracket 730 and sensitive chip 740.Wherein, the first lens group
Part 710 includes the first camera lens, the first microscope base and the first motor, realizes the first camera lens under the drive of the first motor in the first lens barrel
Middle sliding, to focus；Second lens assembly 720 includes the second camera lens, the second microscope base and the second motor, realizes the second camera lens
It is slided in the second lens barrel under the drive of the second motor, to focus.Sensitive chip 740 includes the first pixel array 741
With the second pixel array 742, circuit structure is as shown in above-described embodiment, and details are not described herein again.And sensitive chip 740 is welded in
On wiring board 750, the size of wiring board 750 is greater than the size of sensitive chip 740, and bracket 730 is fixedly connected with wiring board 750,
Constitute the encapsulating structure of camera module.
Optionally, the first lens assembly 710 further includes the first infrared fileter, for filtering out through the acquisition of the first camera lens
Infrared signal.Second lens assembly 720 further includes the second infrared fileter, for filtering out through the infrared of the second camera lens acquisition
Optical signal.
Optionally, the first infrared fileter can also be separately positioned with the first lens assembly 710, the second infrared light optical filter
It can also be separately positioned with the second lens assembly 720.
The embodiment of the present application also provides a kind of electronic equipment, has camera module provided by the embodiments of the present application.Wherein,
Electronic equipment can have the end of camera for smart phone, PAD (tablet computer), laptop and intelligent wearable device etc.
End.Illustrate the structure of electronic equipment by taking smart phone as an example, Fig. 8 is a kind of structure of smart phone provided by the embodiments of the present application
Block diagram.As shown in figure 8, the smart phone may include: memory 801, central processing unit (Central Processing
Unit, CPU) 802 (also known as processors, hereinafter referred to as CPU), Peripheral Interface 803, RF (Radio Frequency, radio frequency) circuit
805, voicefrequency circuit 806, loudspeaker 811, touch screen 812, take the photograph system 813, power management chip 808, input/output (I/ more
O) subsystem 809, other input/control devicess 810 and outside port 804, these components are total by one or more communications
Line or signal wire 807 communicate.
Memory 801, the memory 801 can be accessed by CPU802, Peripheral Interface 803 etc., and the memory 801 can
It can also include nonvolatile memory to include high-speed random access memory, such as one or more disk memory,
Flush memory device or other volatile solid-state parts.
The peripheral hardware that outputs and inputs of equipment can be connected to CPU802 and deposited by Peripheral Interface 803, the Peripheral Interface 803
Reservoir 801.
I/O subsystem 809, the I/O subsystem 809 can be by the input/output peripherals in equipment, such as touch screen 812
With other input/control devicess 810, it is connected to Peripheral Interface 803.I/O subsystem 809 may include 8091 He of display controller
For controlling one or more input controllers 8092 of other input/control devicess 810.Wherein, one or more input controls
Device 8092 processed receives electric signal from other input/control devicess 810 or sends electric signal to other input/control devicess 810,
Other input/control devicess 810 may include physical button (push button, rocker buttons etc.), dial, slide switch, behaviour
Vertical pole clicks idler wheel.It is worth noting that input controller 8092 can with it is following any one connect: keyboard, infrared port,
The indicating equipment of USB interface and such as mouse.
Touch screen 812, the touch screen 812 are the input interface and output interface between user terminal and user, can
It is shown to user depending on output, visual output may include figure, text, icon, video etc..
Display controller 8091 in I/O subsystem 809 receives electric signal from touch screen 812 or sends out to touch screen 812
Electric signals.Touch screen 812 detects the contact on touch screen, and the contact that display controller 8091 will test is converted to and is shown
The interaction of user interface object on touch screen 812, i.e. realization human-computer interaction, the user interface being shown on touch screen 812
Object can be the icon of running game, the icon for being networked to corresponding network etc..It is worth noting that equipment can also include light
Mouse, light mouse are the extensions for the touch sensitive surface for not showing the touch sensitive surface visually exported, or formed by touch screen.
RF circuit 805 is mainly used for establishing the communication of mobile phone Yu wireless network (i.e. network side), realizes mobile phone and wireless network
The data receiver of network and transmission.Such as transmitting-receiving short message, Email etc..Specifically, RF circuit 805 receives and sends RF letter
Number, RF signal is also referred to as electromagnetic signal, and RF circuit 805 converts electrical signals to electromagnetic signal or electromagnetic signal is converted to telecommunications
Number, and communicated by the electromagnetic signal with communication network and other equipment.RF circuit 805 may include for executing
The known circuit of these functions comprising but it is not limited to antenna system, RF transceiver, one or more amplifiers, tuner, one
A or multiple oscillators, digital signal processor, CODEC (COder-DECoder, coder) chipset, user identifier mould
Block (Subscriber Identity Module, SIM) etc..
Voicefrequency circuit 806 is mainly used for receiving audio data from Peripheral Interface 803, which is converted to telecommunications
Number, and the electric signal is sent to loudspeaker 811.
Loudspeaker 811 is reduced to sound for mobile phone to be passed through RF circuit 805 from the received voice signal of wireless network
And the sound is played to user.
Power management chip 808, the hardware for being connected by CPU802, I/O subsystem and Peripheral Interface are powered
And power management.
System 813, including multiple rear camera mould groups and/or multiple front camera mould groups are taken the photograph, for obtaining mesh more
Mark the image data of the different perspectives of object, different depth of field etc., and by Peripheral Interface 803 be transmitted to memory 801 into
Row storage, in case CPU802 is called.Multiple photosensitive regions due to more taking the photograph system are formed on the same substrate, and can be with common portion
Divide integrated circuit, thus, the size of camera module is smaller than the camera module prepared by separate type sensitive chip, reduces more
Take the photograph the volume of system.
It should be understood that illustrating the example that smart phone 800 is only electronic equipment, and smart phone 800
It can have than shown in the drawings more or less component, can combine two or more components, or can be with
It is configured with different components.Various parts shown in the drawings can include one or more signal processings and/or dedicated
It is realized in the combination of hardware, software or hardware and software including integrated circuit.
Note that above are only the preferred embodiment and institute's application technology principle of the application.It will be appreciated by those skilled in the art that
The application is not limited to specific embodiment described here, be able to carry out for a person skilled in the art it is various it is apparent variation,
The protection scope readjusted and substituted without departing from the application.Therefore, although being carried out by above embodiments to the application
It is described in further detail, but the application is not limited only to above embodiments, in the case where not departing from the application design, also
It may include more other equivalent embodiments, and scope of the present application is determined by the scope of the appended claims.
Claims (10)
1. a kind of sensitive chip, at least two pixel arrays including integrated circuit and on substrate；It is characterized in that, described
Integrated circuit includes analog signal amplifier, and at least two pixel array is multiplexed the analog signal amplifier.
2. sensitive chip according to claim 1, which is characterized in that the integrated circuit further includes the scanning of at least two rows
Circuit, at least two line-scan circuits export line scan signals according to work in series mode, realize at least two picture of sequential scan
Pixel array.
3. sensitive chip according to claim 1, which is characterized in that the integrated circuit further includes that at least two column are read
Circuit；
At least two column reading circuit is electrically connected with the analog signal amplifier, for sequentially reading in pixel array
Picture element signal on column bus, and the picture element signal is exported to the analog signal amplifier；
The analog signal amplifier, for amplifying processing to the picture element signal, and amplified picture element signal is defeated
Out to corresponding analog-digital converter.
4. sensitive chip according to claim 3, which is characterized in that the column reading circuit includes correlated-double-sampling electricity
Road calculates the integrated signal and the reset for acquiring the integrated signal and reset signal of pixel in the pixel array
The difference of signal exports the difference to the analog signal amplifier.
5. sensitive chip according to claim 3, which is characterized in that the quantity of the analog-digital converter and pixel array
Quantity is identical；
And the integrated circuit further includes switching circuit, the switching circuit in series is in the analog signal amplifier and institute
It states between analog-digital converter, for being switched over to the analog-digital converter connected with the analog signal amplifier.
6. sensitive chip according to claim 5, which is characterized in that the integrated circuit further includes sequential control circuit,
The sequential control circuit is electrically connected with the switching circuit, for the reading order based at least two pixel arrays and often
The read access time of a pixel array generates switching pulse, exports the switching pulse respectively to the switching circuit, to control
Switching circuit is stated to be turned on or off.
7. sensitive chip according to claim 1, which is characterized in that make at least two pixel arrays using etch process
The corresponding electrical connection of column bus, at least two pixel array are multiplexed column reading circuit.
8. a kind of camera module, which is characterized in that including the sensitive chip as described in any one of claims 1 to 7.
9. camera module according to claim 8, which is characterized in that including the image being electrically connected with the sensitive chip
Processor and the input/output interface being electrically connected with the image processor, and at least two pixel arrays of the sensitive chip
It is multiplexed the input/output interface；
The image processor is electrically connected with analog-digital converter, for carrying out default processing to the digital signal of input, obtains shadow
Increase array mark as data, and for the image data；
The input/output interface for carrying out Format adjusting to the image data respectively according to setting format, and exports lattice
Formula image data adjusted and array mark.
10. a kind of electronic equipment, which is characterized in that the electronic equipment has camera mould as claimed in claim 8 or 9
Group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810967186.6A CN109167940A (en) | 2018-08-23 | 2018-08-23 | A kind of sensitive chip, camera module and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810967186.6A CN109167940A (en) | 2018-08-23 | 2018-08-23 | A kind of sensitive chip, camera module and electronic equipment |
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| CN109167940A true CN109167940A (en) | 2019-01-08 |
Family
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| CN201810967186.6A Pending CN109167940A (en) | 2018-08-23 | 2018-08-23 | A kind of sensitive chip, camera module and electronic equipment |
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