CN108769499A - A kind of sensitive chip, camera module and electronic equipment - Google Patents
A kind of sensitive chip, camera module and electronic equipment Download PDFInfo
- Publication number
- CN108769499A CN108769499A CN201810967264.2A CN201810967264A CN108769499A CN 108769499 A CN108769499 A CN 108769499A CN 201810967264 A CN201810967264 A CN 201810967264A CN 108769499 A CN108769499 A CN 108769499A
- Authority
- CN
- China
- Prior art keywords
- circuit
- sensitive chip
- analog
- signal
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003491 array Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005070 sampling Methods 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000013461 design Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 17
- 230000002596 correlated effect Effects 0.000 description 10
- 230000000875 corresponding effect Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 10
- 238000003384 imaging method Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Human Computer Interaction (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The embodiment of the present application discloses sensitive chip, camera module and electronic equipment.Wherein, sensitive chip includes integrated circuit and at least two pel arrays on substrate, which is characterized in that the integrated circuit includes row reading circuit, and at least two pel array is multiplexed the row reading circuit.The embodiment of the present application is by using above-mentioned technical proposal, using same wafer as substrate, it designs and is formed the sensitive chips for taking the photograph system more over the substrate, realize that the stage of manufacture sensitive chip on the semiconductor realizes the location positions for taking the photograph system photosensitive area more, improve the assembly precisions for taking the photograph system more.In addition, the sensitive chip has the pel array for more taking the photograph system requirements number, and at least two pel arrays multiplexing row reading circuit in turn, can reduce the size of sensitive chip and camera module to reduce the circuit on substrate.Alternatively, increasing the area of photosensitive region on the basis of keeping sensitive chip size constancy, the quality of shooting image can be improved.
Description
Technical field
The invention relates to a kind of technical field of mobile terminals more particularly to sensitive chip, camera module and electricity
Sub- equipment.
Background technology
Electronic equipment with multiple camera modules can control different cameras and execute different function respectively, to
So that the picture captured by camera has more contents and is more clear, imaging is exquisiter, color is more bright-coloured.
The process of camera imaging is mainly optical signal digitized process, which is mainly completed by camera module, taken the photograph
It is made of lens assembly and sensitive chip as head mould group.Currently, in the related technology there are multiple camera modules to take the photograph more
System is typically to obtain multiple camera modules by bracket assembled.However, the circuit in camera module is complicated, and it is each
Spacing between camera module is larger, the assembling mode of module rank, cannot be satisfied production site between module, stated accuracy
It is required that.Such as in binocular ranging, image co-registration scene, the deviation of small distance or angle final result can all be caused compared with
Big deviation.
Invention content
A kind of sensitive chip of the embodiment of the present application offer, camera module and electronic equipment, can optimize in the related technology
The design schemes for taking the photograph system more.
Include integrated circuit on substrate and extremely in a first aspect, the embodiment of the present application provides a kind of sensitive chip
Few two pel arrays, which is characterized in that the integrated circuit includes row reading circuit, at least two pel arrays multiplexing
The row reading circuit.
Second aspect, the embodiment of the present application provide a kind of camera module, including any embodiment of the present invention provides
Sensitive chip.
The third aspect, the embodiment of the present application provide a kind of electronic equipment, and the electronic equipment has the present invention arbitrary real
The camera module of example offer is provided.
The sensitive chip provided in the embodiment of the present application.By using said program, using same wafer as substrate, at this
It designs and is formed the sensitive chips for taking the photograph system more on substrate, realize that the stage of manufacture sensitive chip on the semiconductor realizes that take the photograph is more
The location position of system photosensitive area improves the assembly precisions for taking the photograph system more.In addition, the sensitive chip has takes the photograph system requirements number more
Purpose pel array, and at least two pel arrays are multiplexed row reading circuit, it, in turn, can be with to reduce the circuit on substrate
Reduce the size of sensitive chip and camera module.Alternatively, increasing photosensitive area on the basis of keeping sensitive chip size constancy
The area in domain can improve the quality of shooting image.
Description of the drawings
Fig. 1 is traditional double structural schematic diagrams for taking the photograph system；
Fig. 2 is a kind of structure diagram of sensitive chip provided by the embodiments of the present application；
Fig. 3 is the structure diagram of another sensitive chip provided by the embodiments of the present application；
Fig. 4 is the structure diagram of another sensitive chip provided by the embodiments of the present application；
Fig. 5 is the structure diagram of another sensitive chip provided by the embodiments of the present application；
Fig. 6 is the circuit diagram of correlated double sampling circuit classical in the related technology；
Fig. 7 is the working timing figure of correlated double sampling circuit；
Fig. 8 is a kind of structural schematic diagram of camera module provided by the embodiments of the present application；
Fig. 9 is the structural schematic diagram of a kind of electronic equipment provided by the embodiments of the present application.
Specific implementation mode
Further illustrate the technical solution of the application below with reference to the accompanying drawings and specific embodiments.It is appreciated that
It is that specific embodiment described herein is used only for explaining the application, rather than the restriction to the application.It further needs exist for illustrating
, illustrate only for ease of description, in attached drawing and the relevant part of the application rather than entire infrastructure.
As shown in FIG. 1, FIG. 1 is traditional double structural schematic diagrams for taking the photograph system.By holder 130 by the first camera module
10 and second camera module 20 be assembled into and take the photograph system more.Each camera module includes sensitive chip (140,150) and camera lens
Component (110,120), wherein lens assembly (110,120) includes camera lens, microscope base and motor.Sensitive chip (140,150) welds
It is located at the vertical throwing of camera lens (110,120) in the imaging area (141,151) on wiring board 160, and on sensitive chip (140,150)
Shadow zone domain.
It should be noted that due to the continuous improvement of semiconductor technology and technological level, imaging sensor (Image
Sensor) as a kind of elemental device of acquisition of vision information, because of the expansion of its acquisition, the conversion and visual performance that can realize information
Exhibition provides intuitive, multi-level, abundant in content visible image information, and has and be more and more widely used.It answers in the related technology
Include mainly charge coupling device (CCD) imaging sensor and complementary metal oxide with most commonly used solid state image sensor
Semiconductor (CMOS) imaging sensor.The sensitive chip of the embodiment of the present application can be the imaging sensor of above two type.
In the semiconductor substrate of the sensitive chip have at least two pel arrays, and around the pel array be arranged with
Realize the integrated circuit of sensitive chip function.Integrated circuit includes row reading circuit, and above-mentioned at least two pel array is multiplexed institute
State row reading circuit.It should be noted that suitable according at least two pel array of ordered pair progress when setting in the embodiment of the present application
Sequence is read, and to each pel array in such a way that progressive scan is read by column, thereby guarantees that in the first pel array and owns
The corresponding picture element signal of pixel unit just reads the picture element signal in the second pel array after being read.The picture element signal is defeated
Go out after carrying out signal amplification to amplifying circuit of analog signal, then exports to analog-digital converter.It should be noted that pel array,
For the imaging area of image, containing x*y (row * row) imaging pixel cell, each pixel unit all has photoperceptivity, can be by light
Signal is converted to corresponding analog electronic signal.It is provided with row bus and column bus in pel array, pixel unit is connected to pair
The row bus and column bus answered.
Integrated circuit includes line-scan circuit, and row bus is scanned by switch unit (triode or field-effect tube) and the row
Circuit is electrically connected, and line-scan circuit exports line scan signals to the pel array.It is understood that the quantity of line-scan circuit
Can be identical as the quantity of pel array, the first line-scan circuit is electrically connected with the first pel array, the second line-scan circuit with
Second pel array is electrically connected ... ..., and line n scanning circuit is electrically connected with the n-th pel array, wherein the value of n is more by taking the photograph
The quantity of camera module determines in system.Optionally, above-mentioned at least two line-scan circuit exports row according to work in series mode
Scanning signal realizes at least two pel array of sequential scan.Integrated circuit further includes column select circuit and row reading circuit, is somebody's turn to do
The control terminal of column select circuit connecting valve unit (triode or field-effect tube), one end connects in the other both ends of the switch unit
Column bus is connect, the other end connects row reading circuit, realizes and is connected to column bus to be read and row reading circuit.
It should be noted that semiconductor device fabrication processes may be used forms multiple sensitive chips on same wafer,
And it is cut one by one.Wherein, sensitive chip includes at least two pel arrays and corresponding integrated circuit.It can be to avoid correlation
The problem of taking the photograph big system module grade assembly difficulty, hardly possible debugging in technology more.In the related technology, the camera module for more taking the photograph system is
Multiple sensitive chips correspond to a plurality of lenses, and each camera has separate function, do not have function common portion between each other
Point, since chip is located on respective wiring board, the placed angle of each chip, gradient are variant, can increase
Downstream equipment and the difficulty of debugging.
In order to make it easy to understand, introducing the structure of sensitive chip by taking cmos image sensor as an example.Fig. 2 is the embodiment of the present application
A kind of structure diagram of the sensitive chip provided.Sensitive chip shown in Fig. 2 includes the first pel array 202, the second pixel battle array
Row 206 and integrated circuit, wherein integrated circuit includes the first line-scan circuit being electrically connected with the first pel array 202
201, the second line-scan circuit 205 being electrically connected with the second pel array 206, and respectively at the first pel array 202 and
The row reading circuit 203 of two pel arrays 206 electrical connection, the column selection being electrically connected by switch unit with row reading circuit 203
Circuit 204.Wherein, the column bus 216 of the second pel array 206 extends downwardly structure by the column bus 216 of the first pel array 202
At.The control terminal (one end marked as 1) of 204 connecting valve unit of column select circuit, column bus 216 and row reading circuit 203
It is separately connected the remaining both ends of switch unit (label is respectively 2 and 3).Integrated circuit further includes distinguishing with row reading circuit 203
The first analog signal amplifier 207 and the second analog signal amplifier 208 of connection, with the first analog signal amplifier 207
First analog-digital converter 209 of output end connection and the second analog-digital converter being connect with the second analog signal amplifier 208
210, the first image processor 211 for being connect with the first analog-digital converter 209, second connect with the second analog-digital converter 210
Image processor 212, and the first input/output interface circuit 213 for being connect with the first image processor 211, with the second image
The second input/output interface circuit 214 that processor 212 connects.
When detecting camera open command, processor (such as CPU) outputs control signals to the sequential control of sensitive chip
Circuit processed, so that sequential control circuit Sequential output scan control pulse is to each line-scan circuit, and, output column selection control
Signal is to column select circuit 204.First line-scan circuit 201 exports line scan signals to first line by line according to scan control pulse
Pel array 202.Column select circuit 204 controls the column bus 216 and row reading circuit of signal gating row to be read according to column selection
203.Wherein, scan control pulse is used to control the of the first line-scan circuit 201 in first time period to the first pel array
A line exports line scan signals, to realize the switching means conductive being electrically connected with the pixel of the first row, and in the first time period
Interior, column selection control signal exports Continuity signal between column bus and row reading circuit 203 for controlling column select circuit 204
Switch unit realizes the picture element signal read one by one on column bus, and the pixel is believed to be respectively turned on each switch unit
Number output is to the first analog signal amplifier 207.After the picture element signal for having read last row pixel of the first row, to the second row
Scanning signal is exported, to realize that the field-effect tube being electrically connected with the pixel of the second row is connected, and reads the picture on column bus one by one
Plain signal.The rest may be inferred, until reading the picture element signal for completing last row pixel of last column in the first pel array.
It is completed in the first pel array after the picture element signal of last row pixel of last column reading, sequential control circuit
Scan control pulse is exported to the second line-scan circuit 205, and, output column selection controls signal to column select circuit 204.Second
Line-scan circuit 205 exports line scan signals to the second pel array 206 line by line according to scan control pulse.Column select circuit
204 control the column bus 216 and row reading circuit 203 of a signal gating row pixel unit to be read according to column selection.Wherein, it sweeps
It retouches control pulse and is swept to the first row of the second pel array output row in second time period for controlling the second line-scan circuit 205
Signal is retouched, to realize the switching means conductive being electrically connected with the pixel of the first row, and in the second time period, column selection control letter
Number control column select circuit 204 export Continuity signal to the switch unit between column bus and row reading circuit 203, to connect respectively
Lead to each switch unit, realizes the picture element signal read one by one on column bus, and the picture element signal is exported to the second simulation
Signal amplifier 208.After the picture element signal for having read last row pixel of the first row, scanning signal is exported to the second row, with
It realizes the switching means conductive being electrically connected with the pixel of the second row, and reads the picture element signal on column bus one by one.The rest may be inferred,
Until reading the picture element signal for completing last row pixel of last column in the second pel array.
Optionally, row read array 203 and determined according to the odd even for reading picture element signal number is sent to the by picture element signal
One analog signal amplifier 207 or the second analog signal amplifier 208 are illustrative, and row read array 203 and read odd-times
The picture element signal taken is sent to the first analog signal amplifier 207, and the picture element signal that even-times is read is sent to the second simulation
Signal amplifier 208 reads the picture element signal in two pel arrays on column bus with realization sequence.It should be noted that working as picture
When the quantity of pixel array is more than 2, the row of multiplexing, which read array 203, to determine picture element signal using the quantity of pel array as the period
With the correspondence of analogue amplifier.
First analog signal amplifier 207 is amplified processing to the picture element signal read by the first pel array, and defeated
Go out to amplify picture element signal to the first analog-digital converter 209.
Second analog signal amplifier 208 is amplified processing to the picture element signal read by the second pel array, and defeated
Go out to amplify picture element signal to the second analog-digital converter 210.
The amplification picture element signal that first analog signal amplifier 207 exports is converted to number by the first analog-digital converter 209
Signal, and export to the first image processor 211.
The amplification picture element signal that second analog signal amplifier 208 exports is converted to number by the second analog-digital converter 210
Signal, and export to the second image processor 212.
First image processor 211 receives the digital signal of the first analog-digital converter 209 output, according to the core of sensitive chip
Piece defined function carries out default processing to digital signal, obtains image data, and is the image number according to the source of picture element signal
It is identified according to array is increased.It should be noted that including AEC (auto-exposure control), AGC (oneself to the default processing of digital signal
Dynamic gain control), AWB (automatic white balance), colour correction, Lens Shading (camera lens shadow correction), Gamma corrections, dispel
Except bad point, Auto Black Level (Automatic Black Level correction) and Auto White Level (automatic white level correction) etc.
The processing of function.It should be noted that since the output end of the first image processor 211 and the first analog-digital converter 209 is electrically connected
It connects, to obtain digitized picture element signal by the first analog-digital converter 209, and the picture element signal is read by the first pel array,
It can thus be appreciated that the source of picture element signal is the first pel array.
Second image processor 212 receives the digital signal of the second analog-digital converter 210 output, according to the core of sensitive chip
Piece defined function carries out default processing to digital signal, obtains image data, and is the image number according to the source of picture element signal
It is identified according to array is increased.It should be noted that due to the output end of the second image processor 212 and the second analog-digital converter 210
Electrical connection, to obtain digitized picture element signal by the second analog-digital converter 210, and the picture element signal is read by the second pel array
It takes, it can thus be appreciated that the source of picture element signal is the second pel array.
First input/output interface circuit 213 obtains the image data of the first image processor 211 output, and according to setting
Format carries out Format adjusting, the predeterminated position of the image data after Format adjusting to the image data of each pel array respectively
Output is to back-end platform after adding array mark, so that subsequent step uses.Correspondingly, the second input/output interface circuit 214
The image data of the second image processor 212 output is obtained, and according to setting format respectively to the image number of each pel array
According to Format adjusting is carried out, exported to back-end platform after the predeterminated position addition array mark of the image data after Format adjusting.
Wherein, predeterminated position can there are many selections, the embodiment of the present application to be simultaneously not especially limited.For example, can be after Format adjusting
Image data head addition array mark.For another example, array mark can be added in the tail portion of the image data after Format adjusting
Know etc..
In the present embodiment, analog signal amplifier, analog-digital converter, line-scan circuit, image processor and input
The quantity of output interface is identical as the quantity of pel array, handles respectively the picture element signal of each pel array, mutually
It does not influence.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, including substrate, and the substrate includes at least two
Pel array and integrated circuit, the integrated circuit include the column bus pair for making at least two pel arrays using etch process
It should be electrically connected, column bus is electrically connected with column select circuit and row reading circuit respectively by switch unit, realizes two pixel battle arrays
Row share column select circuit and row reading circuit.By the technical solution of the embodiment of the present application, using same wafer as substrate,
It designs and is formed the sensitive chips for taking the photograph system more on the substrate, realize that the stage of manufacture sensitive chip on the semiconductor realizes take the photograph more
The location position of system photosensitive area improves the assembly precisions for taking the photograph system more.In addition, the sensitive chip has takes the photograph system requirements more
The pel array of number, and at least two pel arrays multiplexing row reading circuit in turn, can to reduce the circuit on substrate
To reduce the size of sensitive chip and camera module.Alternatively, increasing on the basis of keeping sensitive chip size constancy photosensitive
The area in region can improve the quality of shooting image.
Fig. 3 is the structure diagram of another sensitive chip provided by the embodiments of the present application, which includes a row
The row reading circuit 203, one of selection circuit 204, one analog signal amplifier 301, at least two analog-digital converters (209,
210), at least two image processors (211,212) and an input/output interface circuit 215.The analog signal amplifier 301
Input terminal be electrically connected with the output end of row reading circuit 203.First analog-digital converter 209 and the second analog-digital converter 210 are
It is electrically connected with analog signal amplifier 301, and connects first between the first analog-digital converter 209 and analog signal amplifier 301
Switching circuit 302, second switch circuit 303 of connecting between the second analog-digital converter 210 and analog signal amplifier 301.Remaining
Circuit is similar to the aforementioned embodiment, and details are not described herein again.
Sequential control circuit is electrically connected with first switch circuit 302 and second switch circuit 303.The sequential control circuit base
Switching pulse is generated in the reading order of at least two pel arrays and the read access time of each pel array, exports the switch
Pulse is to first switch circuit 302 and second switch circuit 303, based on switching pulse control switching circuit (including first switch
Circuit 302 and second switch circuit 303) realize be switched on or switched off the analog-digital converter being connect with analog signal amplifier 301.
For example, reading order and reading of the sequential control circuit according to the first pel array 202 and the second pel array 206
The read access time for taking each pel array generates switching pulse.If first reading the first pel array 202, switching pulse is exported
So that first switch circuit 302 is connected and second switch circuit 303 is made to disconnect, amplified picture element signal is input to the first mould
Number converter 209.When reading the second pel array 206, output switching pulse makes second switch circuit 303 be connected and makes first
Switching circuit 302 disconnects, and amplified picture element signal is input to the second analog-digital converter 210.First analog-digital converter 209
Picture element signal is converted into corresponding digital signal, output digit signals to the first image processor 211.First image processor
211 pairs of digital signals obtain image data after executing predetermined registration operation, and the battle array of the first pel array is represented for image data addition
Row mark exports the image data for carrying array mark to input/output interface circuit 215, realizes that output meets preset format
Or the image data for carrying array mark of specification.Similarly, the second analog-digital converter 210 is converted to picture element signal corresponding
Digital signal, output digit signals to the second image processor 212.Second image processor 212 executes digital signal default
Image data is obtained after operation, and represents the array mark of the second pel array for image data addition, will carry array mark
Image data export to input/output interface circuit 215, realize that output meets the carrying array mark of preset format or specification
Image data.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, and column selection electricity is shared by two pel arrays
Road, row reading circuit, analog signal amplifier and input/output interface reduce the circuit on substrate, it is thus possible to reduce photosensitive
The size of chip and camera module.Alternatively, increase the area of photosensitive region on the basis of keeping sensitive chip size constancy,
The quality of shooting image can be improved.
Specification is needed, the input/output interface circuit 215 in Fig. 3 may be replaced by the first input/output interface
Circuit 213 and the second input/output interface circuit 214, wherein the first input/output interface circuit 213 and the first image processor
211 electrical connections, the second input/output interface circuit 214 are electrically connected with the second image processor 212.
Fig. 4 is the structure diagram of another sensitive chip provided by the embodiments of the present application.The sensitive chip includes a row
The 301, analog-digital converters 401 of the analog signal amplifier of row reading circuit 203, one of selection circuit 204, one and a shadow
As processor 402 and an input/output interface circuit 215.The input terminal of the analog signal amplifier 301 and row reading circuit
203 output end electrical connection, the output end of the analog signal amplifier 301 are electrically connected with the input terminal of analog-digital converter 401, should
The output end of analog-digital converter 401 is electrically connected with image processor 402, and output end and the input and output of image processor 402 connect
Mouth circuit 215 is electrically connected.
When detecting camera open command, processor (such as CPU) outputs control signals to the sequential control of sensitive chip
Circuit processed, so that sequential control circuit Sequential output scan control pulse is to each line-scan circuit, and, output column selection control
Signal is realized to column select circuit 204 and sequentially reads the picture element signal in each pel array by row reading circuit 203.Row
203 output pixel signal of reading circuit is amplified processing to analog signal amplifier 301, obtains amplification picture element signal, this is put
Big picture element signal is input to analog-digital converter 401.Analog-digital converter 401 will amplify picture element signal and be converted to corresponding number letter
Number, and export to image processor 402.The quantity of digital signal that the image processor 402 record receives, and by the quantity
It is compared with predetermined threshold value.If the quantity for the digital signal that image processor 402 receives is equal to predetermined threshold value, it is determined that under
The digital signal of one reading belongs to next pel array, the first array mark preset in logo collection is obtained, by this
First array mark is added to image data.Then, count value is reset, the digital signal of reading is counted again.
Wherein, predetermined threshold value can be the set of tactic at least two positive integer, and value is by the reading order of pel array
It is determined with the quantity for the pixel unit for including in pel array.By taking the pel array of two 3*4 as an example, the first pixel battle array is first read
Row, it includes 12 pixel units, then first number is 12 in the corresponding set of predetermined threshold value, since the second pel array also wraps
Containing 12 pixel units, then second number is also 12.Predetermined threshold value is that [12,12] first obtain when image processor 402 works
First numerical value is as predetermined threshold value, when the quantity of the picture element signal of record is equal to first numerical value, then by second numerical value
As predetermined threshold value.Array mark in default logo collection is determined according to the reading order of each pel array, and array mark
Knowledge can be the mark for uniquely determining pel array.
Image processor 402 exports the image data for carrying array mark to input/output interface circuit 215, this is defeated
Enter output interface circuit 215 and Format adjusting is carried out to the image data of each pel array according to setting format sequential, and
Image data after output format adjustment and array mark.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, and column selection electricity is shared by two pel arrays
Road, row reading circuit, analog signal amplifier, analog-digital converter, image processor and input/output interface circuit, further subtract
Circuit on few substrate, it is thus possible to save chip the space occupied in camera module.
The integrated circuit of sensitive chip further includes correlated double sampling circuit in some embodiments, and Fig. 5 is implemented for the application
The structure diagram for another sensitive chip that example provides.The correlated double sampling circuit includes that the first reset control circuit and second are multiple
Position control circuit, for after receiving reset signal respectively in the first pel array pixel and the second pel array in
Pixel resetted.The reset for being advantageous in that acquisition pixel and the integrated signal after pixel integration are designed in this way, are calculated
The difference of integrated signal and reset signal is simultaneously exported to analog signal amplifier, and fixed mode is eliminated by Correlated Double Sampling
Noise (including the operation of row fixed mode and pixel fixed pattern noise).Wherein, each due to the limitation of manufacture craft accuracy
The picture element signal that row reading circuit is read can have certain error deviation amount, this offset is referred to as row fixed mode and makes an uproar
Sound.In addition, being referred to as pixel fixed pattern noise there is also the difference that manufacture craft error band comes between pixel and pixel.
Illustratively, sensitive chip includes the first pel array 202, the second pel array 206 and integrated circuit.The collection
Include at circuit：
Interface circuit, for external control data to be loaded into chip memory register group.9
Sequential control circuit, the integral that the data for being arranged according to internal register generate pixel unit read, reset
Equal internal timing signals, and exported to corresponding circuit in the form of pulse signal.
First line-scan circuit (including the first row address decoder and first line shift register) respectively with timing control
Circuit and the electrical connection of the first pel array 202, for exporting line scan signals under the control of sequential control circuit to the first picture
Pixel array 202, or reseting controling signal is exported to the first reset control circuit.
Second line-scan circuit (including the second row address decoder and second line shift register) respectively with timing control
Circuit and the electrical connection of the second pel array 206, for exporting line scan signals under the control of sequential control circuit to the second picture
Pixel array 206, or reseting controling signal is exported to the second reset control circuit.
First reset control circuit is electrically connected with the first pel array 202, for according to the first row reset circuit (including the
A line address decoder and the first line shift register) output reseting controling signal the pixel in current line is carried out at reset
Reason.Wherein, current line is a line to be read in current pixel array.
Second reset control circuit is electrically connected with the second pel array 206, for according to the second row reset circuit (including the
Two row address decoders and the second line shift register) output reseting controling signal the pixel in current line is carried out at reset
Reason.
In order to make it easy to understand, being sampled and being reset to using classical pixel unit of correlated double sampling circuit pair
Example illustrates in such a way that Correlated Double Sampling eliminates fixed pattern noise.Fig. 6 is the correlation of classics in the related technology
The circuit diagram of dual-sampling circuit.As shown in fig. 6, the photodiode for including by pixel unit current source Iph, capacitance Cd
Carry out equivalent simulation with resistance Rd, reset switch is NMOS transistor MR.NMOS tube MLN and MIN constitute source follower amplifier,
PMOS tube MSR and MSHS are two signal transmission doors, and capacitance CR and Cs constitute two sampling capacitances, and NMOS tube MS1 and MS2 are used for
It is reset to sampling capacitance.
Fig. 7 is the working timing figure of correlated double sampling circuit.As shown in fig. 7, the course of work of correlated double sampling circuit is such as
Under：
(1) sampling reset signal Vr：Time t is by during 0 to t0, reset switch pipe MR is controlled in reseting controling signal VR
Lower conducting, n point current potentials become high level, and VX and VLN keeps high level；Start to expose in t0 moment sensitive chips, n point voltages are logical
Source follower and transmission gate MSR are crossed, the reset signal Vr of output is sampled on capacitance CR.
(2) sample integration signal Vs：By during t1 to t2, two transmission gates disconnect, without signal sampling, due to photoelectricity
The effect of stream Iph makes the integral voltage at n points be gradually reduced.At t2 moment, transmission gate MSHS conductings, n points voltage passes through at this time
The integral voltage signal Vs of source follower and transmission gate, output is sampled on capacitance CS.
(3) the signal Vr and Vs on the t3 moment, two sampling capacitances make the difference, and using the difference as useful signal, pass through
Column bus exports.
The residual circuits such as analog signal amplifier, analog-digital converter are similar to the aforementioned embodiment, and details are not described herein again.
The technical solution of the embodiment of the present application provides a kind of sensitive chip, further includes correlated double sampling circuit, based on correlation
Dual-sampling circuit acquires the integrated signal and reset signal of pixel in the pel array, calculate the integrated signal with it is described multiple
The difference of position signal, the difference is exported to the analog signal amplifier, fixed pattern noise can be effectively eliminated.
The embodiment of the present application also provides a kind of camera module, includes the sensitive chip provided such as above-described embodiment, realizes
It is made up of one piece of sensitive chip at least two pel arrays and takes the photograph system more.The camera module may include have it is upper
Multiple rear camera modules of the sensitive chip of embodiment offer and/or multiple front camera modules are provided.The camera shooting head mould
Group includes：
The sensitive chip of structure is recorded with above-described embodiment, which is welded on wiring board.Wherein, at least two
A pel array (i.e. imaging area or photosensitive area), since the precision of manufacture of semiconductor is significantly larger than module group procedure precision, same
Two or more pel arrays are prepared on substrate forms multiple photosensitive regions, it can be by chip flatness, at least two photosensitive areas
The relative deviation in domain, relative tilt angle are angularly improved by grade to micron order.
Camera lens, it is consistent with the quantity of the pel array of the sensitive chip.Multiple lens are fixed to form camera lens by microscope base, mirror
Head, microscope base and voice coil motor constitute lens assembly, and lens assembly is fixed by the bracket takes the photograph system more in composition on wiring board.It needs
Illustrate, it can be the shooting being made of multiple rear camera modules and/or multiple front camera modules to take the photograph system more
System.
Fig. 8 is a kind of structural schematic diagram of camera module provided by the embodiments of the present application.As shown in figure 8, the camera
Module includes：First lens assembly 810, the second lens assembly 820, holder 830 and sensitive chip 840.Wherein, the first lens group
Part 810 includes the first camera lens, the first microscope base and the first motor, realizes the first camera lens under the drive of the first motor in the first lens barrel
Middle sliding, to focus；Second lens assembly 820 includes the second camera lens, the second microscope base and the second motor, realizes the second camera lens
It is slided in the second lens barrel under the drive of the second motor, to focus.Sensitive chip 840 includes the first pel array 841
With the second pel array 842, circuit structure is as shown in above-described embodiment, and details are not described herein again.And sensitive chip 840 is welded in
On wiring board 850, the size of wiring board 850 is more than the size of sensitive chip 840, and holder 830 is fixedly connected with wiring board 850,
Constitute the encapsulating structure of camera module.
Optionally, the first lens assembly 810 further includes the first infrared fileter, is acquired by the first camera lens for filtering out
Infrared signal.Second lens assembly 820 further includes the second infrared fileter, for filter out acquired by the second camera lens it is infrared
Optical signal.
Optionally, the first infrared fileter can also be separately positioned with the first lens assembly 810, the second infrared light optical filter
It can also be separately positioned with the second lens assembly 820.
Fig. 9 provides the structural schematic diagram of a kind of electronic equipment for the embodiment of the present application.With provided by the embodiments of the present application
Camera module.Wherein, electronic equipment can be smart mobile phone, PAD (tablet computer), laptop and intelligent wearable device
Deng the terminal with camera.Illustrate that the structure of electronic equipment, Fig. 9 are provided by the embodiments of the present application one by taking smart mobile phone as an example
The structure diagram of kind smart mobile phone.As shown in figure 9, the smart mobile phone may include：Shell (not shown), memory 901,
Central processing unit (Central Processing Unit, CPU) 902 (also known as processor, hereinafter referred to as CPU), Peripheral Interface
903, RF (Radio Frequency, radio frequency) circuit 905, voicefrequency circuit 906, loud speaker 911, touch screen 912, take the photograph system more
913, power management chip 908, input/output (I/O) subsystem 909, other input/control devicess 910 and outside port
904, these components are communicated by one or more communication bus or signal wire 907.
Memory 901, the memory 901 can be by access such as CPU902, Peripheral Interfaces 903, and the memory 901 can
Can also include nonvolatile memory to include high-speed random access memory, such as one or more disk memory,
Flush memory device or other volatile solid-state parts.
The peripheral hardware that outputs and inputs of equipment can be connected to CPU902 and deposited by Peripheral Interface 903, the Peripheral Interface 903
Reservoir 901.
I/O subsystems 909, the I/O subsystems 909 can be by the input/output peripherals in equipment, such as touch screen 912
With other input/control devicess 910, it is connected to Peripheral Interface 903.I/O subsystems 909 may include 9091 He of display controller
One or more input controllers 9092 for controlling other input/control devicess 910.Wherein, one or more input controls
Device 9092 processed receives electric signal from other input/control devicess 910 or sends electric signal to other input/control devicess 910,
Other input/control devicess 910 may include physical button (pressing button, rocker buttons etc.), dial, slide switch, behaviour
Vertical pole clicks idler wheel.It is worth noting that input controller 9092 can with it is following any one connect：Keyboard, infrared port,
The indicating equipment of USB interface and such as mouse.
Touch screen 912, the touch screen 912 are the input interface and output interface between customer mobile terminal and user,
Visual output is shown to user, visual output may include figure, text, icon, video etc..
Display controller 9091 in I/O subsystems 909 receives electric signal from touch screen 912 or is sent out to touch screen 912
Electric signals.Touch screen 912 detects the contact on touch screen, and the contact detected is converted to and is shown by display controller 9091
The interaction of user interface object on touch screen 912, that is, realize human-computer interaction, the user interface being shown on touch screen 912
Object can be the icon of running game, be networked to the icon etc. of corresponding network.It is worth noting that equipment can also include light
Mouse, light mouse are the extensions for the touch sensitive surface for not showing the touch sensitive surface visually exported, or formed by touch screen.
RF circuits 905 are mainly used for establishing the communication of mobile phone and wireless network (i.e. network side), realize mobile phone and wireless network
The data receiver of network and transmission.Such as transmitting-receiving short message, Email etc..Specifically, RF circuits 905 receive and send RF letters
Number, RF signals are also referred to as electromagnetic signal, and RF circuits 905 convert electrical signals to electromagnetic signal or electromagnetic signal is converted to telecommunications
Number, and communicated with communication network and other equipment by the electromagnetic signal.RF circuits 905 may include for executing
The known circuit of these functions comprising but it is not limited to antenna system, RF transceivers, one or more amplifiers, tuner, one
A or multiple oscillators, digital signal processor, CODEC (COder-DECoder, coder) chipset, user identifier mould
Block (Subscriber Identity Module, SIM) etc..
Voicefrequency circuit 906 is mainly used for receiving audio data from Peripheral Interface 903, which is converted to telecommunications
Number, and the electric signal is sent to loud speaker 911.
Loud speaker 911, the voice signal for receiving mobile phone from wireless network by RF circuits 905, is reduced to sound
And play the sound to user.
Power management chip 908, the hardware for being connected by CPU902, I/O subsystem and Peripheral Interface are powered
And power management.
Information encryption device, storage medium and the mobile terminal provided in above-described embodiment, which can perform the application, arbitrarily to be implemented
The information ciphering method that example is provided has and executes the corresponding function module of this method and advantageous effect.Not in above-described embodiment
In detailed description technical detail, reference can be made to the information ciphering method that the application any embodiment is provided.
Note that above are only preferred embodiment and the institute's application technology principle of the application.It will be appreciated by those skilled in the art that
The application is not limited to specific embodiment described here, can carry out for a person skilled in the art it is various it is apparent variation,
The protection domain readjusted and substituted without departing from the application.Therefore, although being carried out to the application by above example
It is described in further detail, but the application is not limited only to above example, in the case where not departing from the application design, also
May include other more equivalent embodiments, and scope of the present application is determined by scope of the appended claims.
Claims (10)
1. a kind of sensitive chip includes integrated circuit and at least two pel arrays on substrate, which is characterized in that described
Integrated circuit includes row reading circuit, and at least two pel array is multiplexed the row reading circuit.
2. sensitive chip according to claim 1, which is characterized in that make at least two pel arrays using etch process
Column bus corresponds to electrical connection；
The row reading circuit is electrically connected with the column bus of at least two pel array, at least two described in sequence reading
Picture element signal in a pel array on column bus, and the picture element signal of reading is transmitted to analog signal amplifier.
3. sensitive chip according to claim 2, which is characterized in that the quantity of the analog signal amplifier and the picture
The quantity of pixel array is identical；
At least two analog signal amplifier is electrically connected with the row reading circuit respectively, for respectively to corresponding pixel
Picture element signal in array on column bus is amplified processing.
4. sensitive chip according to claim 2, which is characterized in that the quantity of the analog signal amplifier and the row
The quantity of reading circuit is identical, and at least two pel array is multiplexed the analog signal amplifier.
5. sensitive chip according to claim 3 or 4, which is characterized in that the row reading circuit includes correlated-double-sampling
Circuit acquires the integrated signal and reset signal of pixel in any pixel array, calculates the product to any pixel array
The difference of sub-signal and the reset signal exports the difference to the analog signal amplifier.
6. sensitive chip according to claim 3 or 4, which is characterized in that the integrated circuit include analog-digital converter and
Switching circuit；
The input terminal of the switching circuit is electrically connected with the analog signal amplifier, the output end of the switching circuit with it is described
Analog-digital converter is electrically connected, and is switched over for pair analog-digital converter connected with the analog signal amplifier.
7. sensitive chip according to claim 6, which is characterized in that the integrated circuit further includes sequential control circuit,
The sequential control circuit is electrically connected with the switching circuit, for scanning sequency based at least two pel arrays and every
The sweep time of a pel array generates switching pulse, exports the switching pulse respectively to the switching circuit, to control
Switching circuit is stated to be turned on or off.
8. sensitive chip according to claim 1, which is characterized in that the integrated circuit further includes the scanning of at least two rows
Circuit, at least two line-scan circuits export line scan signals according to work in series mode, realize at least two picture of sequential scan
Pixel array.
9. a kind of camera module, which is characterized in that including sensitive chip such as described in any item of the claim 1 to 8.
10. a kind of electronic equipment, which is characterized in that the electronic equipment has camera module as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810967264.2A CN108769499B (en) | 2018-08-23 | 2018-08-23 | Photosensitive chip, camera module and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810967264.2A CN108769499B (en) | 2018-08-23 | 2018-08-23 | Photosensitive chip, camera module and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108769499A true CN108769499A (en) | 2018-11-06 |
| CN108769499B CN108769499B (en) | 2024-04-09 |
Family
ID=63967640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810967264.2A Active CN108769499B (en) | 2018-08-23 | 2018-08-23 | Photosensitive chip, camera module and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108769499B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842768A (en) * | 2019-01-29 | 2019-06-04 | 上海芯仑光电科技有限公司 | A kind of pixel Acquisition Circuit and imaging sensor |
| CN110690238A (en) * | 2019-09-30 | 2020-01-14 | 芯盟科技有限公司 | Image sensor module |
| CN112399111A (en) * | 2020-10-09 | 2021-02-23 | 电子科技大学中山学院 | Shift register and CMOS solid-state imaging sensor |
| CN112511769A (en) * | 2020-11-05 | 2021-03-16 | 北京大学深圳研究生院 | Image sensor pixel circuit and image sensing array |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007147963A (en) * | 2005-11-28 | 2007-06-14 | Epson Imaging Devices Corp | Electrooptical apparatus, driving method, and electronic equipment |
| US20080128698A1 (en) * | 2002-02-05 | 2008-06-05 | Peter Martin | Many million pixel image sensor |
| US20090135245A1 (en) * | 2007-11-27 | 2009-05-28 | Jiafu Luo | Camera system with multiple pixel arrays on a chip |
| CN102572320A (en) * | 2011-11-28 | 2012-07-11 | 北京思比科微电子技术股份有限公司 | Method for reducing height of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor module and CMOS image sensor module |
| US20120188422A1 (en) * | 2011-01-20 | 2012-07-26 | Kwang-Bo Cho | Imaging system with an array of image sensors |
| JP2012222763A (en) * | 2011-04-14 | 2012-11-12 | Panasonic Corp | Solid state image pickup device and its driving method |
| JP2017103771A (en) * | 2016-12-05 | 2017-06-08 | ソニー株式会社 | Semiconductor device, solid state image sensor and camera system |
| CN208509090U (en) * | 2018-08-23 | 2019-02-15 | Oppo广东移动通信有限公司 | A kind of sensitive chip, camera module and electronic equipment |
-
2018
- 2018-08-23 CN CN201810967264.2A patent/CN108769499B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080128698A1 (en) * | 2002-02-05 | 2008-06-05 | Peter Martin | Many million pixel image sensor |
| JP2007147963A (en) * | 2005-11-28 | 2007-06-14 | Epson Imaging Devices Corp | Electrooptical apparatus, driving method, and electronic equipment |
| US20090135245A1 (en) * | 2007-11-27 | 2009-05-28 | Jiafu Luo | Camera system with multiple pixel arrays on a chip |
| CN101926171A (en) * | 2007-11-27 | 2010-12-22 | 卡普索影像股份有限公司 | Camera system with multiple pixel arrays on chip |
| US20120188422A1 (en) * | 2011-01-20 | 2012-07-26 | Kwang-Bo Cho | Imaging system with an array of image sensors |
| JP2012222763A (en) * | 2011-04-14 | 2012-11-12 | Panasonic Corp | Solid state image pickup device and its driving method |
| CN102572320A (en) * | 2011-11-28 | 2012-07-11 | 北京思比科微电子技术股份有限公司 | Method for reducing height of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor module and CMOS image sensor module |
| JP2017103771A (en) * | 2016-12-05 | 2017-06-08 | ソニー株式会社 | Semiconductor device, solid state image sensor and camera system |
| CN208509090U (en) * | 2018-08-23 | 2019-02-15 | Oppo广东移动通信有限公司 | A kind of sensitive chip, camera module and electronic equipment |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842768A (en) * | 2019-01-29 | 2019-06-04 | 上海芯仑光电科技有限公司 | A kind of pixel Acquisition Circuit and imaging sensor |
| CN110690238A (en) * | 2019-09-30 | 2020-01-14 | 芯盟科技有限公司 | Image sensor module |
| CN112399111A (en) * | 2020-10-09 | 2021-02-23 | 电子科技大学中山学院 | Shift register and CMOS solid-state imaging sensor |
| CN112399111B (en) * | 2020-10-09 | 2022-04-08 | 电子科技大学中山学院 | Shift register and CMOS solid-state imaging sensor |
| CN112511769A (en) * | 2020-11-05 | 2021-03-16 | 北京大学深圳研究生院 | Image sensor pixel circuit and image sensing array |
| CN112511769B (en) * | 2020-11-05 | 2022-09-20 | 北京大学深圳研究生院 | Image sensor pixel circuit and image sensing array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108769499B (en) | 2024-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10764522B2 (en) | Image sensor, output method, phase focusing method, imaging device, and terminal | |
| CN108769499A (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN106254727B (en) | Photographic device and signal processing circuit | |
| TW548962B (en) | X-Y address type solid-state image pickup device | |
| US7352400B2 (en) | Solid-state image pickup apparatus having a differential output | |
| CN104683668B (en) | Camera device and mobile phone | |
| US8792033B2 (en) | Image pickup apparatus capable of changing operation condition of image sensing device and control method therefor | |
| CN106060430A (en) | Image pickup apparatus, image pickup system, and method of driving an image pickup apparatus | |
| CN108668068A (en) | A kind of camera module and electronic equipment | |
| CN104137421A (en) | A/d conversion circuit, and solid-state image pickup apparatus | |
| CN105008976A (en) | Imaging device, signal processing method, and signal processing program | |
| US10044956B2 (en) | Image capturing apparatus, control method thereof, and storage medium | |
| US10313612B2 (en) | Image sensor, control method, and electronic device | |
| CN109167940A (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN104702865A (en) | Image sensor, image capturing apparatus and cellular phone | |
| CN112004036B (en) | Method for acquiring image data and image sensing system thereof | |
| CN208509085U (en) | A kind of camera module and electronic equipment | |
| CN208509090U (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN208754415U (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN208509103U (en) | A kind of sensitive chip, camera module and electronic equipment | |
| US20190068870A1 (en) | Image processing device, electronic apparatus, reproduction device, reproduction program, and reproduction method | |
| CN208509089U (en) | A kind of imaging sensor, camera module and electronic equipment | |
| CN108769500A (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN208509088U (en) | A kind of sensitive chip, camera module and electronic equipment | |
| CN208509102U (en) | A kind of imaging sensor, camera module and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |