CN108962861B - Substrate, preparation method of substrate and power-up method of substrate - Google Patents
Substrate, preparation method of substrate and power-up method of substrate Download PDFInfo
- Publication number
- CN108962861B CN108962861B CN201810857819.8A CN201810857819A CN108962861B CN 108962861 B CN108962861 B CN 108962861B CN 201810857819 A CN201810857819 A CN 201810857819A CN 108962861 B CN108962861 B CN 108962861B
- Authority
- CN
- China
- Prior art keywords
- substrate
- pad
- power
- bonding pad
- electric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 11
- 239000000523 sample Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 3
- 230000007306 turnover Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810857819.8A CN108962861B (en) | 2018-07-31 | 2018-07-31 | Substrate, preparation method of substrate and power-up method of substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810857819.8A CN108962861B (en) | 2018-07-31 | 2018-07-31 | Substrate, preparation method of substrate and power-up method of substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108962861A CN108962861A (en) | 2018-12-07 |
CN108962861B true CN108962861B (en) | 2020-05-01 |
Family
ID=64466149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810857819.8A Active CN108962861B (en) | 2018-07-31 | 2018-07-31 | Substrate, preparation method of substrate and power-up method of substrate |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN108962861B (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4792726B2 (en) * | 2003-10-30 | 2011-10-12 | 日亜化学工業株式会社 | Manufacturing method of support for semiconductor element |
CN103197227A (en) * | 2013-03-25 | 2013-07-10 | 西安华芯半导体有限公司 | Wafer testing method used for design analysis purpose |
US20170263546A1 (en) * | 2014-03-07 | 2017-09-14 | Bridge Semiconductor Corporation | Wiring board with electrical isolator and base board incorporated therein and semiconductor assembly and manufacturing method thereof |
-
2018
- 2018-07-31 CN CN201810857819.8A patent/CN108962861B/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN108962861A (en) | 2018-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7852101B2 (en) | Semiconductor device testing apparatus and power supply unit for semiconductor device testing apparatus | |
TW512233B (en) | Contact structure and assembly mechanism thereof | |
US7745943B2 (en) | Microelectonic packages and methods therefor | |
US9123362B1 (en) | Methods for assembling an electrically assisted magnetic recording (EAMR) head | |
JP5195087B2 (en) | Photoelectric conversion device, photoelectric conversion module, and method of manufacturing photoelectric conversion device | |
KR100337588B1 (en) | Semiconductor inspection device and inspection method using the same | |
CN102484108A (en) | A high-bandwidth ramp-stack chip package | |
JP2010135513A (en) | Package | |
JP2009506539A (en) | Microelectronic devices and microelectronic support devices and related assemblies and methods | |
JP2012533063A (en) | Probe card | |
JP2012059782A (en) | Resin sealing type semiconductor device, and method of manufacturing the same | |
KR100711292B1 (en) | Probe card and method for manufacturing the same | |
CN103926430A (en) | Through-silicon via patch board testing method | |
JP2022094269A (en) | Alignment module for magnetic led die transfer and alignment method thereof | |
CN108962861B (en) | Substrate, preparation method of substrate and power-up method of substrate | |
CN102782829B (en) | Non-uniform vacuum profile die attach tip | |
CN110226270A (en) | Optical module and CAN packaging part | |
JPH0536457A (en) | Electronic part, its application device, and manufacture thereof | |
CN213517669U (en) | Optical module structure | |
JP2009176924A (en) | Manufacturing method of semiconductor device, and manufacturing device for the semiconductor device | |
CN105607196B (en) | A kind of optical interconnection module of optical chip, the preparation method and application optical chip | |
CN118248658B (en) | Flip chip frame | |
CN114823548B (en) | LGA packaging structure for photoelectric co-packaging | |
CN110083370B (en) | Firmware burning mechanism and method based on PLCC packaging | |
JP2005321655A (en) | Optical component, optical communication module, electronic apparatus, and method for manufacturing optical component and optical communication module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20200403 Address after: 243000 Anhui city of Ma'anshan province high tech Zone at 1669 North Road Huo sparkle Building No. 2 Applicant after: Yirui Optoelectronic Technology (Anhui) Co.,Ltd. Applicant after: SUZHOU YIRUI OPTOELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 215123 13 301A, North Korea's Nancheng West District, 99 Suzhou Industrial Park, Suzhou, Jiangsu. Applicant before: SUZHOU YIRUI OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
|
TA01 | Transfer of patent application right | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20240426 Address after: 518000 a1706, Shenzhen national engineering laboratory building, No. 20, Gaoxin South seventh Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen, Guangdong Patentee after: Shenzhen Yingu Jianke Network Co.,Ltd. Country or region after: China Patentee after: Shenzhen Iridium Semiconductor Technology Co.,Ltd. Address before: 243000 2, 1669 north section of Huo Li Shan Road, Ma'anshan high tech Zone, Anhui Patentee before: Yirui Optoelectronic Technology (Anhui) Co.,Ltd. Country or region before: China Patentee before: SUZHOU YIRUI OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
|
TR01 | Transfer of patent right |