CN108962843A - Semiconducter IC built-in substrate and its manufacturing method - Google Patents

Semiconducter IC built-in substrate and its manufacturing method Download PDF

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Publication number
CN108962843A
CN108962843A CN201810479432.3A CN201810479432A CN108962843A CN 108962843 A CN108962843 A CN 108962843A CN 201810479432 A CN201810479432 A CN 201810479432A CN 108962843 A CN108962843 A CN 108962843A
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China
Prior art keywords
semiconducter
insulating layer
wiring layer
substrate
built
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CN201810479432.3A
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Chinese (zh)
Inventor
露谷和俊
胜俣正史
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TDK Corp
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TDK Corp
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention, which provides, to configure wiring in the back portion of semiconducter IC, and do not generate the semiconducter IC built-in substrate in gap between die bonding material and insulating layer comprising: the upper surface (11a) for being embedded in insulating layer (11), upper surface (21a) and insulating layer (11) constitutes conplane wiring layer (21)；The semiconducter IC (40) of the upper surface (21a) of wiring layer (21) is configured at via die bonding film (41)；With the insulating layer (12) for the upper surface (21a) for being laminated in wiring layer (21) in a manner of by semiconducter IC (40) embedment, the back side (41a) of die bonding film (41) connects with upper surface (21a) both sides of the upper surface (11a) of insulating layer (11) and wiring layer (21), in this way, wiring layer (21) and insulating layer (11) constitute same plane, therefore gap is not generated between die bonding film (41) and insulating layer (11), and wiring layer (21) positioned at the back portion of semiconducter IC (40) can be efficiently used.

Description

Semiconducter IC built-in substrate and its manufacturing method
Technical field
The present invention relates to semiconducter IC built-in substrate and its manufacturing methods, in particular to are provided at the back side of semiconducter IC The semiconducter IC built-in substrate and its manufacturing method of die bonding material.
Background technique
In recent years, the miniaturization to the portable electronic devices such as smart phone and plate computer terminal and multifunction is wanted It asks further significant, in order to realize this requirement, uses the semiconducter IC built-in substrate in multilager base plate embedment semiconducter IC sometimes. For example, the semiconducter IC built-in substrate recorded in patent document 1 is recessed by being formed in the defined insulating layer for constituting multilager base plate Portion is embedded to semiconducter IC in the recess portion to form semiconducter IC built-in substrate.
But the semiconducter IC built-in substrate recorded in patent document 1, due to cannot be in the back portion of semiconducter IC Wiring is configured, therefore there is a problem of that the utilization efficiency of wiring layer is low.In order to solve this problem, consider warp as shown in Figure 13 Semiconducter IC 40 is carried to the insulating layer 80 of wiring layer 81 is formed in upper surface, later such as Figure 14 by die bonding film 41 The method that shown such mode for being embedded to semiconducter IC 40 forms insulating layer 90.Then, via through-hole connection semiconducter IC 40 Terminal electrode 42 and wiring layer 91 and wiring layer 82,91 is patterned to form Wiring pattern, thus completes semiconductor IC built-in substrate.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2007-165810 bulletin
Summary of the invention
Problem to be solved by the invention
But in the methods described above, near wiring layer 81, the meeting between insulating layer 80 and die bonding film 41 It generates in gap V (space), thus there are problems that the reliability of product reduces.This is because by wiring layer 81 in insulating layer 80 Surface generate step difference, it is difficult to the step difference is filled and led up completely using die bonding film 41.
Therefore, the purpose of the present invention is to provide can configure wiring in the back portion of semiconducter IC and glue in chip Connect the semiconducter IC built-in substrate and its manufacturing method for not generating gap between material and insulating layer.
Mode for solving the problems, such as
Semiconducter IC built-in substrate of the invention is characterised by comprising: the first insulating layer；It is embedded in above-mentioned first insulation Layer, upper surface expose from the upper surface of above-mentioned first insulating layer and constitute with the above-mentioned upper surface of above-mentioned first insulating layer same First wiring layer of plane；Semiconducter IC via the configuration of die bonding material in the above-mentioned upper surface of above-mentioned first wiring layer； It is above-mentioned with the second insulating layer for the above-mentioned upper surface for being laminated in above-mentioned first wiring layer in a manner of being embedded to above-mentioned semiconducter IC The back side of die bonding material and the above-mentioned upper surface of above-mentioned first insulating layer and the above-mentioned upper surface of above-mentioned first wiring layer Both sides connect.
According to the present invention, the first wiring layer is embedded in the first insulating layer, and the upper surface of the two constitutes same plane, therefore Gap is not generated between die bonding material and the first insulating layer.Moreover, the back part positioned at semiconducter IC can be efficiently used The first wiring layer divided, therefore the utilization efficiency of wiring layer can also be improved.
In the present invention, the back side of die bonding material can also be with multiple signal wiring phases of the first wiring layer of composition It connects.Using such structure, the utilization efficiency of wiring layer can be further increased.
Semiconducter IC built-in substrate of the invention can further include: the formed in the upper surface of second insulating layer Two wiring layers；Perforation second insulating layer and be arranged, connect the first through hole conductor of the first wiring layer and the second wiring layer；And perforation Second insulating layer and the second via conductors for being arranged, connecting the terminal electrode of the second wiring layer and semiconducter IC.In such case Under, semiconducter IC built-in substrate of the invention can further include the third wiring in the formation of the lower surface of the first insulating layer It layer and penetrates through the first insulating layer and is arranged, connects the third through-hole conductor of the first wiring layer Yu third wiring layer, it can also be into one Step includes: the third insulating layer that the upper surface of second insulating layer is laminated in a manner of by the embedment of the second wiring layer；It is exhausted in third The 4th wiring layer that the upper surface of edge layer is formed；With perforation third insulating layer and be arranged, connect the second wiring layer and the 4th wiring The fourth hole conductor of layer.Using such structure, it is capable of providing the semiconducter IC built-in substrate for having more wiring layers.
In the present invention, die bonding material is also possible to be adhered to the die bonding film at the back side of semiconducter IC.It adopts With such structure, even if also can be realized the processing of semiconducter IC in the case where the thickness of semiconducter IC is very thin.At this In the case of kind, die bonding film can also be thicker than constituting the silicon of semiconducter IC.Using such structure, it is able to use thinner Semiconducter IC.
The manufacturing method of semiconducter IC built-in substrate of the invention is characterised by comprising: preparing substrate and conductor foil Laminated body, the first step being equipped on semiconducter IC via die bonding material on above-mentioned conductor foil；With by above-mentioned semiconductor The mode of IC embedment forms the second step of second insulating layer on above-mentioned conductor foil；The third step that above-mentioned substrate is removed； The fourth step of the first wiring layer is formed and being patterned to above-mentioned conductor foil；With with by above-mentioned first wiring layer be embedded to Mode above-mentioned second insulating layer lower surface formed the first insulating layer the 5th process, it is above in above-mentioned the fourth step The a part at the back side of die bonding material is stated to be covered and the above-mentioned back side of said chip adhesives by above-mentioned first wiring layer Remainder expose the above-mentioned conductor foil of mode be patterned, the above-mentioned back side of said chip adhesives is upper as a result, Remainder is stated to connect with above-mentioned first insulating layer.
According to the present invention, by being patterned the conductor foil come shape after semiconducter IC is equipped on conductor foil At the first wiring layer, therefore step difference is not present in the substrate when carrying semiconducter IC.Therefore, it can prevent due to step difference The generation in gap.
In the present invention, conductor foil is made of the first and second conductor foils that the surface in substrate stacks gradually, in third It, thus can also be using the second conductor foil as the first wiring by the interface peel of the first conductor foil and the second conductor foil in process The material of layer.According to this structure, it can easily be done the removal of substrate.In this case, the second conductor foil can also compare First conductor foil is thick.In this way, even if partly being led in the case where eventually becoming the film thickness of the second conductor foil of the first wiring layer thickness Also step difference is not present when the carrying of body IC, therefore gap will not be generated.
The manufacturing method of semiconducter IC built-in substrate of the invention can also further comprise after carrying out the second step Form perforation second insulating layer and the first through hole and perforation second insulating layer that expose conductor foil and the end for making semiconducter IC The process for the second through-hole that sub-electrode exposes.According to this structure, it can make with built in the semiconducter IC of multi-layer wiring structure Substrate.
The effect of invention
In this way, in accordance with the invention it is possible to wiring can be configured in the back portion of semiconducter IC and glue in chip by providing Connect the semiconducter IC built-in substrate and its manufacturing method for not generating gap between material and insulating layer.
Detailed description of the invention
Fig. 1 is the sectional view for the structure for illustrating the semiconducter IC built-in substrate 10 of the preferred embodiment of the present invention.
Fig. 2 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 3 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 4 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 5 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 6 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 7 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 8 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Fig. 9 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Figure 10 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Figure 11 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Figure 12 is the process chart for illustrating the manufacturing method of semiconducter IC built-in substrate 10.
Figure 13 is the process chart for illustrating the manufacturing method of existing semiconducter IC built-in substrate.
Figure 14 is the process chart for illustrating the manufacturing method of existing semiconducter IC built-in substrate.
Specific embodiment
Hereinafter, the preferred embodiment of the present invention is described in detail referring to attached drawing.
Fig. 1 is the sectional view for the structure for illustrating the semiconducter IC built-in substrate 10 of the preferred embodiment of the present invention.
As shown in Figure 1, the semiconducter IC built-in substrate 10 of present embodiment includes first~third insulating layer 11~13, the One~the 4th wiring layer 21~24 and the semiconducter IC 40 for being embedded in inside.First~third insulating layer 11~13 is exhausted by resin etc. Edge material is constituted, and at least second insulating layer 12 is set to thicker than semiconducter IC 40.
The Wiring pattern being made of good conductors such as copper (Cu) is each formed in the first~the 4th wiring layer 21~24.Wherein, First wiring layer 21 between the first insulating layer 11 and second insulating layer 12, the second wiring layer 22 be located at second insulating layer 12 with Between third insulating layer 13.In addition, third wiring layer 23 is located at the lower surface of the first insulating layer 11, the 4th wiring layer 24 is located at the The upper surface of three insulating layers 13.
Further, in the semiconducter IC built-in substrate 10 of present embodiment, it is provided with first~third of perforation insulating layer 11 ~13 and be arranged multiple via conductors 31~34.Wherein, first through hole conductor 31 penetrates through second insulating layer 12 and connects first Wiring layer 21 and the second wiring layer 22.In addition, the second via conductors 32 penetrate through second insulating layer 12 and connect the second wiring layer 22 With the terminal electrode 42 of semiconducter IC 40.Third through-hole conductor 33 penetrates through the first insulating layer 11 and connects the first wiring layer 21 and the Three wiring layers 23.Fourth hole conductor 34 penetrates through third insulating layer 13 and connects the second wiring layer 22 and the 4th wiring layer 24.
As shown in Figure 1, the first wiring layer 21 is embedded in the first insulation in the semiconducter IC built-in substrate 10 of present embodiment Layer 11, and the upper surface 11a of the upper surface 21a of the first wiring layer 21 and the first insulating layer 11 constitutes same plane.First wiring The upper surface 21a of layer 21 exposes from the upper surface 11a of the first insulating layer 11.Moreover, being bonded with core at the back side of semiconducter IC 40 Piece is bonded (die attach) film 41, and semiconducter IC 40 configures the upper table in the first wiring layer 21 via die bonding film 41 Face 21a.
In the back side adhering chip adhering film 41 of semiconducter IC 40 not only for ensuring for the first wiring layer 21 The bonding force of upper surface 21a alsos for the process performance for improving semiconducter IC 40.Semiconducter IC 40 used in present embodiment It is thinned by back side grinding, but when by its thickness skiving to such as 50 μm or so, processing when installation becomes difficult, The breakage of chip can be generated.In order to solve the problems, in the present embodiment in the back side adhering chip of semiconducter IC 40 Adhering film 41 therefore ensures that process performance when installation.Although being not particularly limited, semiconducter IC 40 and die bonding The thickness of film 41 can be 25 μm or so.In addition, semiconducter IC 40 it is thinner in the case where and need further In the case where the process performance for improving semiconducter IC 40, the thickness of die bonding film 41 can also be set to partly lead than constituting The silicon of body IC40 is thicker.
In the present embodiment, the back side 41a of die bonding film 41 not only with the upper surface 21a phase of the first wiring layer 21 It connects, and also connects with the upper surface 11a of the first insulating layer 11.Although in this way, the back side 41a of die bonding film 41 and first Wiring layer 21 connects, but in the present embodiment, because the upper surface 11a of the first insulating layer 11 and the first wiring layer 21 is upper Surface 21a constitutes same plane, so conventional example that will not be as shown in Figure 13 and Figure 14 is such, in the back of die bonding film 41 Face 41a generates gap etc..The 2 signal wiring 21s to connect with die bonding film 41 are indicated in the example depicted in figure 1, and Actually can so that the mode that connects with the back side 41a of die bonding film 41 of more signal wiring and power supply wiring into Row arrangement (layout).
In this way, the upper surface 11a of the first insulating layer 11 of the semiconducter IC built-in substrate 10 of present embodiment matches with first The upper surface 21a of line layer 21 constitutes same plane, therefore even if carries semiconductor on the surface via die bonding film 41 IC40 will not generate gap etc..Therefore, it can be realized the slimming of entire substrate and improve the reliability of product.Moreover, Multiple signal wirings can be arranged in the part that the back side 41a with die bonding film 41 connects, therefore can also improve first The utilization efficiency of wiring layer 21.
Then, the manufacturing method of the semiconducter IC built-in substrate 10 of present embodiment is illustrated.
Fig. 2~Figure 12 is the process chart for the manufacturing method for illustrating the semiconducter IC built-in substrate 10 of present embodiment.
Firstly, preparing to be sequentially laminated with the first conductor foil 52 and the second conductor on the surface of substrate 51 as shown in Figure 2 The laminated body 50 of foil 53.Substrate 51 is made of cured resin etc., and the first and second conductor foils 52,53 are led by copper (Cu) etc. is good Body is constituted.It is provided with peeling layer (not shown) between the first conductor foil 52 and the second conductor foil 53, at the interface can hold It changes places and constitutes the mode of the two removing.In contrast, the interface of substrate 51 and the first conductor foil 52 is due to anchoring effect (fixation Effect) and ratio is more securely close to.
Then, on the second conductor foil 53 of the laminated body 50 having a structure in which, via die bonding film 41 with Face-up mode carries semiconducter IC 40.Face-up mode refers to so that the terminal electrode 42 of semiconducter IC 40 is arranged in The mode carried towards mode to the upper side.At this point, because the second conductor foil 53 it is flat, die bonding film 41 with Gap etc. is not generated between second conductor foil 53.Half is indicated alternatively, it is also possible to be formed in advance in the first and second conductor foils 52,53 The alignment mark of the loading position of conductor IC40.
Furthermore it is preferred that by being etched before carrying semiconducter IC 40 to the surface of the second conductor foil 53 or sandblasting adds Work and make its rough surface.According to this structure, the second conductor foil 53 and die bonding film 41 can be improved using anchoring effect Close property, and the close property of the second conductor foil 53 with aftermentioned second insulating layer 12 can also be improved.
Then, as shown in Figure 3, second insulating layer is formed on laminated body 50 in a manner of being embedded to semiconducter IC 40 12.Specifically, preparing the laminated body for having conductor foil in a surface mount of uncured or semi-cured state resin film A, so that the mode that uncured or semi-cured state resin film connects with the second conductor foil 53 of laminated body 50 makes the two It is overlapped, solidifies uncured or semi-cured state resin film by carrying out hot pressing.Cured resin film becomes the as a result, Two insulating layers 12, the conductor foil for pasting surface thereon become the second wiring layer 22.In addition, because resin film with uncured or Semi-cured state is by vacuum hotpressing, so the bumps due to semiconducter IC 40 will not be generated, in addition, will not be in semiconducter IC 40 Around form gap etc..
Then, as shown in Figure 4, first is formed in defined position by removing a part of the second wiring layer 22 With the second opening portion 61,62.Herein, the terminal electrode 42 with semiconducter IC 40 is arranged in terms of stacking direction in the second opening portion 62 The position of overlapping.The formation of first and second opening portions 61,62 can by using photoetching process formed mask after, via mask Second wiring layer 22 is etched to carry out.
Then, as shown in Figure 5, to be formed with the second wiring layer 22 of the first and second opening portions 61,62 as mask, The first and second through-holes 71,72 are formed in second insulating layer 12.First through hole 71 penetrates through second insulating layer 12 and reaches laminated body 50 The second conductor foil 53, the second conductor foil 53 its bottom expose.In addition, the second through-hole 72 perforation second insulating layer 12 reaches half The terminal electrode 42 of conductor IC40, terminal electrode 42 expose in its bottom.The formation of first and second through-holes 71,72 is able to use Laser processing method and sand-blast etc. carry out.
Then, as shown in Figure 6, the is formed in the inside of the first and second through-holes 71,72 by implementing electrolysis plating etc. One and second via conductors 31,32.The second wiring layer 22 is with the second conductor foil 53 of laminated body 50 through first through hole conductor as a result, 31 are connected, and the second wiring layer 22 is connected with the terminal electrode 42 of semiconducter IC 40 through the second via conductors 32.
Then, as shown in Figure 7, by shelling the interface of the first conductor foil 52 of laminated body 50 and the second conductor foil 53 From removing substrate 51 and the first conductor foil 52.As described above, because being set at the interface of the first conductor foil 52 and the second conductor foil 53 It is equipped with peeling layer, so can simply be removed.Remaining second conductor foil 53 becomes the first wiring layer 21 as a result,.
Then, as shown in Figure 8, by being patterned to the first and second wiring layers 21,22, as defined in being formed Wiring pattern.Herein, the first wiring layer 21 it is graphical in so that a part of the back side 41a of die bonding film 41 Pattern shape is carried out by the mode that the remaining part of the covering of the first wiring layer 21 and the back side 41a of die bonding film 41 is exposed At.It indicates to be formed and die bonding film 41 and being patterned the first wiring layer 21 in the example shown in Fig. 8 The situation for 2 signal wiring 21s that back side 41a connects.As described above, die bonding film 41 with the second flat conductor foil The mode that 53 surface connects is arranged, therefore very close to each other therebetween, and the upper surface 21a and chip of signal wiring 21s The back side 41a of adhering film 41 constitutes same plane.In addition, the back side 41a of die bonding film 41 and second insulating layer 12 Lower surface 12a also constitutes same plane.
Then, as shown in Figure 9, the second wiring layer of the first insulating layer 11 and covering of the first wiring layer 21 of covering is formed 22 third insulating layer 13.Specifically, preparing to have in a surface mount of uncured or semi-cured state resin film Laminated body B, C of conductor foil, in such a way that uncured or semi-cured state resin film is towards 12 side of second insulating layer, with 2 A laminated body B, C clip second insulating layer 12, by carrying out vacuum hotpressing in this state, make uncured or semi-cured state Resin film solidification.Cured resin film becomes first and third insulating layer 11,13 as a result, is pasted on its lower surface and upper The conductor foil on surface respectively becomes the third and fourth wiring layer 23,24.
The part that do not exposed as a result, by the covering of the first wiring layer 21 in the back side 41a of die bonding film 41 is by first Insulating layer 11 covers.Moreover, the lower surface 12a of the upper surface 11a of the first insulating layer 11, second insulating layer 12, the first wiring layer 21 upper surface 21a, the back side 41a of die bonding film 41 mutually constitute same plane.In addition, because resin film is not solid By vacuum hotpressing under change or semi-cured state, so the bumps due to the first wiring layer 21 are not generated, in addition, in the first wiring Gap etc. is not formed around layer 21.Equally, the bumps due to the second wiring layer 22 are not generated, in addition, in the second wiring layer Gap etc. is not formed around 22 yet.
Furthermore it is preferred that by before forming first and third insulating layer 11,13, to the first and second wiring layers 21,22 Surface be etched or sandblasting processing, make its rough surface.According to this structure, due to anchoring effect and the first wiring layer 21 with The close property of first insulating layer 11 improves, and the close property of the second wiring layer 22 and third insulating layer 13 is improved.
Then, as shown in Figure 10, by removing a part of third wiring layer 23, the is formed in defined position Three opening portions 63, and by removing a part of the 4th wiring layer 24, the 4th opening portion 64 is formed in defined position.This Place, third opening portion 63 are arranged in the position Chong Die with the first wiring layer 21 in terms of stacking direction, and the 4th opening portion 64 is from stacking Direction, which is seen, is arranged in the position Chong Die with the second wiring layer 22.The formation of third and fourth opening portion 63,64 can be by benefit After forming mask with photoetching process, the third and fourth wiring layer 23,24 is etched via mask to carry out.
Then, as shown in Figure 11, it is with the second wiring layer 23,24 for being formed with the third and fourth opening portion 63,64 Mask, forms third through-hole 73 in the first insulating layer 11, forms fourth hole 74 in third insulating layer 13.Third through-hole 73 penetrates through First insulating layer 11 reaches the first wiring layer 21, and the first wiring layer 21 exposes in its bottom.In addition, fourth hole 74 penetrates through third Insulating layer 13 reaches the second wiring layer 22, and the second wiring layer 22 exposes in its bottom.The formation energy of third and fourth through-hole 73,74 Enough carried out using laser processing method and sand-blast etc..
Then, as shown in Figure 12, by implementing electrolysis plating etc., formed in the inside of the third and fourth through-hole 73,74 Third and fourth via conductors 33,34.The first wiring layer 21 is connected with third wiring layer 23 via third through-hole conductor 33 as a result, It connects, the second wiring layer 22 is connected with the 4th wiring layer 24 via fourth hole conductor 34.
Then, by being patterned to the third and fourth wiring layer 23,24, Wiring pattern as defined in formation is thus complete At semiconducter IC built-in substrate 10 shown in FIG. 1.
Show in this way, the manufacturing method of the semiconducter IC built-in substrate 10 of present embodiment is not as shown in Figure 13 and Figure 14 Some manufacturing methods are such, carry semiconducter IC 40 via die bonding film 41 on patterned wiring layer 81, and flat Semiconducter IC 40 is carried via die bonding film 41 on smooth conductor foil 53, later, by being patterned to conductor foil 53 And the first wiring layer 21 is formed, therefore not will form the gap of the concaveconvex shape due to the first wiring layer 21.As a result, energy Enough prevent the decline into reliability caused by the expansion of moisture in gap etc..
More than, the preferred embodiment of the present invention is illustrated, but the present invention is not limited to above-mentioned implementations Mode, and can make various changes without departing from the spirit and scope of the invention, these certain changes are also contained in this hair In bright range.
For example, in the above-described embodiment, being said by taking the semiconducter IC built-in substrate with 4 layers of wiring layer as an example It is bright, but it's not limited to that for application of the invention.
In addition, in the above-described embodiment, being carried out to the example for carrying semiconducter IC 40 via die bonding film 41 Explanation, but the other die bonding material substitution die bonding films 41 such as die bonding cream also can be used.But from mentioning From the perspective of the process performance of high semiconducter IC, particularly preferably use die bonding film as die bonding material.
Further, in the above-described embodiment, the first conductor foil 52 and second is laminated with using on the surface of substrate 51 The laminated body 50 of conductor foil 53, but it's not limited to that for the structure of laminated body used in the present invention.For example, it is also possible to use The laminated body being made of substrate and single-conductor foil, can also use the laminated body being made of 2 conductor foils.In addition, in Fig. 9 institute In the process shown, laminated body B and C can also not be used, and uses uncured or semi-solid preparation resin and copper foil, and same to them Shi Yiqi carries out hot pressing.
The explanation of appended drawing reference
10 semiconducter IC built-in substrates
11~13 insulating layers
The upper surface of the first insulating layer of 11a
The lower surface of 12a second insulating layer
21~24 wiring layers
The upper surface of the first wiring layer of 21a
21s signal wiring
31~34 via conductors
40 semiconducter ICs
41 die bonding films
The back side of 41a die bonding film
42 terminal electrodes
50, A~C laminated body
51 substrates
52,53 conductor foil
61~64 opening portions
71~74 through-holes
80,90 insulating layer
81,82,91 wiring layer
The gap V

Claims (11)

1. a kind of semiconducter IC built-in substrate, which is characterized in that
Include:
First insulating layer；
It is embedded in first insulating layer, upper surface is exposed from the upper surface of first insulating layer and is insulated with described first The upper surface of layer constitutes conplane first wiring layer；
The semiconducter IC for the upper surface configured via die bonding material in first wiring layer；With
The second insulating layer of the upper surface of first wiring layer is laminated in a manner of being embedded to the semiconducter IC,
The back side of the die bonding material and the upper surface of first insulating layer and the institute of first wiring layer Upper surface both sides are stated to connect.
2. semiconducter IC built-in substrate as described in claim 1, which is characterized in that
The back side of the die bonding material connects with the multiple signal wirings for constituting first wiring layer.
3. semiconducter IC built-in substrate as described in claim 1, which is characterized in that
Further include:
In the second wiring layer that the upper surface of the second insulating layer is formed；
It penetrates through the second insulating layer and is arranged and connects the first through hole of first wiring layer and second wiring layer and lead Body；With
It penetrates through the second insulating layer and is arranged and connects the of the terminal electrode of second wiring layer and the semiconducter IC Two via conductors.
4. semiconducter IC built-in substrate as claimed in claim 3, which is characterized in that
Further include:
In the third wiring layer that the lower surface of first insulating layer is formed；With
It penetrates through first insulating layer and is arranged and connects the third through-hole of first wiring layer and the third wiring layer and lead Body.
5. semiconducter IC built-in substrate as claimed in claim 4, which is characterized in that
Further include:
The third insulating layer of the upper surface of the second insulating layer is laminated in a manner of by second wiring layer embedment；
In the 4th wiring layer that the upper surface of the third insulating layer is formed；With
It penetrates through the third insulating layer and is arranged and connects the fourth hole of second wiring layer and the 4th wiring layer and lead Body.
6. the semiconducter IC built-in substrate as described in any one of Claims 1 to 5, which is characterized in that
The die bonding material is the die bonding film for being adhered to the back side of the semiconducter IC.
7. semiconducter IC built-in substrate as claimed in claim 6, which is characterized in that
The die bonding film is thicker than the silicon for constituting the semiconducter IC.
8. a kind of manufacturing method of semiconducter IC built-in substrate, which is characterized in that
Include:
The laminated body for preparing substrate and conductor foil, the be equipped on semiconducter IC via die bonding material on the conductor foil One process；
The second step of second insulating layer is formed on the conductor foil in a manner of being embedded to the semiconducter IC；
The third step that the substrate is removed；
The fourth step of the first wiring layer is formed and being patterned to the conductor foil；With
The 5th of the first insulating layer the is formed in the lower surface of the second insulating layer in a manner of by first wiring layer embedment Process,
In the fourth step, covered with a part at the back side of the die bonding material by first wiring layer and The mode that the remainder at the back side of the die bonding material exposes is patterned the conductor foil, as a result, institute The remainder for stating the back side of die bonding material connects with first insulating layer.
9. the manufacturing method of semiconducter IC built-in substrate as claimed in claim 8, which is characterized in that
The conductor foil is made of the first and second conductor foils stacked gradually on the surface of the substrate,
In the third step, by the interface peel of first conductor foil and second conductor foil, thus by described Material of two conductor foils as first wiring layer.
10. the manufacturing method of semiconducter IC built-in substrate as claimed in claim 9, which is characterized in that
Second conductor foil is thicker than first conductor foil.
11. the manufacturing method of the semiconducter IC built-in substrate as described in any one of claim 8~10, which is characterized in that
After carrying out the second step, further include to form the perforation second insulating layer and make that the conductor foil exposes the One through-hole and the perforation second insulating layer and the process of the second through-hole for exposing the terminal electrode of the semiconducter IC.
CN201810479432.3A 2017-05-19 2018-05-18 Semiconducter IC built-in substrate and its manufacturing method Pending CN108962843A (en)

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