CN108958453B - Low-power-consumption access method and device for register file - Google Patents
Low-power-consumption access method and device for register file Download PDFInfo
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- CN108958453B CN108958453B CN201810715133.5A CN201810715133A CN108958453B CN 108958453 B CN108958453 B CN 108958453B CN 201810715133 A CN201810715133 A CN 201810715133A CN 108958453 B CN108958453 B CN 108958453B
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Abstract
The invention discloses a low-power-consumption access method and a low-power-consumption access device for a register file, wherein each register is divided in advance, a data state register for marking whether data is 0 or not is added for each register body, and control signals for writing 0 and reading 0 are added for an access port; intercepting an access request of each individual access port of the register, if the access request is write, increasing write 0 control on the basis of the write-in mode of the original register, and writing 0 control into the register when the data in the register is not 0 and updating the corresponding data state register to be in a non-0 state; if the access request is read, the read 0 control is added to the original register reading mode, and the content of the register is not read during the read 0 control, and the corresponding data output port is directly cleared from 0. The invention can reduce unnecessary register access, thereby reducing the power consumption of register file access.
Description
Technical Field
The invention relates to a power consumption optimization technology of a register file in a microprocessor system structure, in particular to a low-power-consumption access method and a low-power-consumption access device of the register file.
Background
The register file is mainly used for operand storage in the microprocessor, and the data are stored in the register file on a microprocessor chip, so that the access frequency is effectively reduced, the delay in reading the corresponding data is reduced, the energy consumption caused by the access is avoided, and the effects of improving the performance or reducing the power consumption are achieved. But due to frequent data accesses and wide data widths, the register file power consumption is high and there is a waste of energy due to invalid write operations. For example, in some architectures, general purpose registers can be accessed in both 64-bit and 32-bit ways, with the upper 32 bits of the general purpose register being cleared 0 when accessed in 32-bit ways, and reading and writing to the upper 32 bits being superfluous when the register is accessed in 32-bit ways in succession. Therefore, how to optimize the power consumption of the register file due to frequent data access and wider data width, and reduce the energy waste caused by invalid write operations has become a key technical problem to be solved.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a low-power-consumption access method and a low-power-consumption access device for a register file.
In order to solve the technical problems, the invention adopts the technical scheme that:
a low power access method for a register file, comprising the steps of:
1) splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when the actual access data of the register is invalid;
2) intercepting an access request of a register access port and judging the type of the access request, and if the type of the access request is write, skipping to execute the step 3); if the type of the access request is read, skipping to execute the step 4);
3) performing data writing operation on the register, adding 0 writing control on the basis of the writing mode of the original register, writing 0 into the register when the data in the register is not 0 under the 0 writing control, and updating the corresponding data state register to be in a non-0 state;
4) and performing data reading operation on the register, adding 0 reading control on the original register reading mode, and directly clearing 0 from the corresponding data output port without reading the content of the register during 0 reading control.
Preferably, when each register is divided in step 1), the register is divided into the width 2 of the registerNDivide by register minimum access granularity 2M(ii) an individual.
Preferably, the validity of the corresponding control signal in the step 1) when the actual access data of the register is invalid specifically means: for write operation, when the access data width is 128 bits, each register body writes non-0, when the access data width is 64 bits, two bodies corresponding to the high 64 bits of the register write 0, two bodies corresponding to the low 64 bits write non-0, when the access data width is 32 bits, 3 bodies corresponding to the high 96 bits of the register write 0, and the low 32 bits correspond to the bodies write non-0; for a read operation, the data needed for the operation is read from which register the contents of which bank are read, and the remaining registers are read 0 operations.
Preferably, the detailed steps of step 3) include:
3.1) judging whether the data writing operation performed on the register is effective or not, if not, skipping to execute the step 3.5), otherwise, skipping to execute the step 3.2);
3.2) judging whether the write operation of each group of the register is write 0 operation, if so, skipping to execute the step 3.3), otherwise, skipping to execute the step 3.4) if not, otherwise, executing the step 0);
3.3) judging whether the data in the corresponding register is 0, if so, not accessing the register, keeping the contents of the data and the data state register unchanged, and skipping to execute the step 3.5); otherwise, executing a write 0 operation, writing 0 into the register only when the data in the register is not 0, updating the corresponding data state register to be 1, and skipping to execute the step 3.5);
3.4) judging whether the data in the corresponding register is 0, if so, writing the data into the register, and simultaneously writing the data into the data state register 0, and skipping to execute the step 3.5); if not 0, writing the data into the register, keeping the data state register unchanged, and skipping to execute the step 3.5);
3.5) ending the register access and exiting.
Preferably, the detailed steps of step 4) include:
4.1) judging whether the data reading operation performed on each body of the register is effective or not, if not, skipping to execute the step 4.5), otherwise, skipping to execute the step 4.2);
4.2) judging whether the read operation of each register is read 0 operation, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3) directly clearing 0 of the corresponding data output port without reading the content of the register, and skipping to execute the step 4.5);
4.4) reading data from the register and then outputting the data to a corresponding data output port;
4.5) ending the register access and exiting.
The invention also provides a low power consumption access device of a register file, comprising:
the register splitting program unit is used for splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when the actual access data of the register is invalid;
an access request intercepting program unit for intercepting the access request of the register access port and judging the type of the access request, if the type of the access request is write, skipping to execute the step 3); if the type of the access request is read, skipping to execute the step 4);
the write-in operation program unit is used for performing data write-in operation on the register, write-in 0 control is added on the basis of the write-in mode of the original register, and when the write-in 0 control is not 0, 0 is written in the register and the corresponding data state register is updated to be in a non-0 state;
and the reading operation program unit is used for reading data of the register, adding reading 0 control to the original reading mode of the register, and directly clearing 0 of the corresponding data output port without reading the content of the register during reading 0 control.
The invention also provides a low power access arrangement for a register file comprising a microprocessor with a register file, said microprocessor being programmed to perform the steps of the low power access method for a register file according to the invention.
Compared with the prior art, the invention has the following beneficial effects: the invention adds a write 0 control component and a read 0 control component on the basis of the original register access mode, detects the register access data type and the register storage data type, and eliminates the unnecessary write 0 operation in the continuous write 0 and the access to the register in the read 0 operation process by detecting the corresponding data type when accessing the register and the type of the data stored in the register, thereby reducing the unnecessary access to the register and further reducing the access power consumption of the register file.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the implementation steps of the low power access method for a register file in this embodiment include:
1) splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when the actual access data of the register is invalid; in this embodiment, the data status register represents that the stored data is 0 when the data status register is 1, and represents that the stored data is not 0 when the data status register is 0.
2) Intercepting an access request of a register access port and judging the type of the access request, and if the type of the access request is write, skipping to execute the step 3); if the type of the access request is read, skipping to execute the step 4);
3) performing data writing operation on the register, adding 0 writing control on the basis of the writing mode of the original register, writing 0 into the register when the data in the register is not 0 under the 0 writing control, and updating the corresponding data state register to be in a non-0 state;
4) and performing data reading operation on the register, adding 0 reading control on the original register reading mode, and directly clearing 0 from the corresponding data output port without reading the content of the register during 0 reading control.
In this embodiment, when each register is split in step 1), the register is divided into registers with a width of 2NDivide by minimum access granularity of registers 2M(ii) an individual. For example, the register width is 128 bits, and the minimum access data granularity is 32 bits, which can be divided into 4 units.
In this embodiment, the validity of the corresponding control signal when each bank of the register actually accesses invalid data in step 1) specifically means: for write operation, when the access data width is 128 bits, all the banks of the register write non-0, when the access data width is 64 bits, two banks of the register corresponding to the high 64 bits of the register write 0, two banks of the register corresponding to the low 64 bits write non-0, when the access data width is 32 bits, 3 banks of the register corresponding to the high 96 bits of the register write 0, and the register corresponding to the low 32 bits write non-0; for the read operation, the data required by the operation is read from which bank of registers corresponding to which bank, and the rest of registers are read for 0 operation. For example, in an instruction for indexing an element of data, if the index signals are different, the corresponding operand is in a different bank, if the element size is 8 bits, then only one of the four cases [127:96], [95:64], [63:32] and [31:0] in 128-bit data can be read, the corresponding bank reads non-0, and the rest banks read 0.
Referring to fig. 1, the detailed steps of step 3) include:
3.1) judging whether the data writing operation performed on the register is effective or not, if not, skipping to execute the step 3.5), otherwise, skipping to execute the step 3.2);
3.2) judging whether the write operation of each bank of the register is write 0 operation (judged by a corresponding write 0 control signal), if so, skipping to execute the step 3.3), otherwise, skipping to execute the step 3.4 if not, otherwise, judging whether the write operation of each bank of the register is write 0 operation;
3.3) judging whether the data in the corresponding register is 0 (judged by a data state register), if so, not accessing the register, keeping the contents of the data and the data state register unchanged, and skipping to execute the step 3.5); otherwise, executing a write 0 operation, writing 0 into the register only when the data in the register is not 0, updating the corresponding data state register to be 1, and skipping to execute the step 3.5);
3.4) judging whether the data in the corresponding register is 0, if so, writing the data into the register, and simultaneously writing the data into the data state register 0, and skipping to execute the step 3.5); if not 0, writing the data into the register, keeping the data state register unchanged, and skipping to execute the step 3.5);
3.5) ending the register access and exiting.
Referring to fig. 1, the detailed steps of step 4) include:
4.1) judging whether the data reading operation performed on each body of the register is effective or not, if not, skipping to execute the step 4.5), otherwise, skipping to execute the step 4.2);
4.2) judging whether the read operation of the register is read 0 operation, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3) directly clearing 0 of the corresponding data output port without reading the content of the register, and skipping to execute the step 4.5);
4.4) reading data from the register and then outputting the data to a corresponding data output port;
4.5) ending the register access and exiting.
In the low-power-consumption access method for the register file in the embodiment, a write 0 control unit and a read 0 control unit are added on the basis of an original register access mode, the register access data type and the register storage data type are detected, and unnecessary write 0 operation in continuous write 0 and access to the register in the read 0 operation process are eliminated by detecting the corresponding data type in the register access and the type of data stored in the register, so that unnecessary access to the register is reduced, and the access power consumption of the register file is reduced.
The present embodiment further provides a low power access apparatus for a register file, including:
the register splitting program unit is used for splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when actual access data of each body of the register are invalid;
an access request intercepting program unit for intercepting the access request of the register access port and judging the type of the access request, if the type of the access request is write, skipping to execute the step 3); if the type of the access request is read, skipping to execute the step 4);
the write-in operation program unit is used for performing data write-in operation on the register, write-in 0 control is added on the basis of the write-in mode of the original register, and when the write-in 0 control is not 0, 0 is written in the register and the corresponding data state register is updated to be in a non-0 state;
and the reading operation program unit is used for reading data of the register, adding reading 0 control to the original reading mode of the register, and directly clearing 0 of the corresponding data output port without reading the content of the register during reading 0 control.
The present embodiment also provides a low power access device for a register file, which includes a microprocessor with a register file, and the microprocessor is programmed to execute the steps of the low power access method for the register file according to the present embodiment.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (7)
1. A method for low power access to a register file, comprising the steps of:
1) splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when the actual access data of the register is invalid;
2) intercepting an access request of a register access port and judging the type of the access request, and if the type of the access request is write, skipping to execute the step 3); if the type of the access request is read, skipping to execute the step 4);
3) performing data writing operation on the register, adding 0 writing control on the basis of the writing mode of the original register, writing 0 into the register when the data in the register is not 0 under the 0 writing control, and updating the corresponding data state register to be in a non-0 state;
4) and performing data reading operation on the register, adding 0 reading control on the original register reading mode, and directly clearing 0 from the corresponding data output port without reading the content of the register during 0 reading control.
2. The method for accessing a register file with low power consumption as claimed in claim 1, wherein when each register is divided in step 1), the register is divided into registers with width 2NDivide by register minimum access granularity 2M(ii) an individual.
3. The low-power-consumption access method of the register file according to claim 1, wherein the fact that the control signal corresponding to the invalid actual access data of the register in step 1) is valid specifically means that: for write operation, when the access data width is 128 bits, each register body writes non-0, when the access data width is 64 bits, two bodies corresponding to the high 64 bits of the register write 0, two bodies corresponding to the low 64 bits write non-0, when the access data width is 32 bits, 3 bodies corresponding to the high 96 bits of the register write 0, and the low 32 bits correspond to the bodies write non-0; for a read operation, the data needed for the operation is read from which register the contents of which bank are read, and the remaining registers are read 0 operations.
4. The method for accessing a register file with low power consumption according to claim 1, wherein the detailed step of step 3) comprises:
3.1) judging whether the data writing operation performed on the register is effective or not, if not, skipping to execute the step 3.5), otherwise, skipping to execute the step 3.2);
3.2) judging whether the write operation of each register of the registers is write 0 operation, if so, skipping to execute the step 3.3), otherwise, skipping to execute the step 3.4) if not, otherwise, executing the step 0);
3.3) judging whether the data in the corresponding register is 0, if so, not accessing the register, keeping the contents of the data and the data state register unchanged, and skipping to execute the step 3.5); otherwise, executing a write 0 operation, writing 0 into the register only when the data in the register is not 0, updating the corresponding data state register to be 1, and skipping to execute the step 3.5);
3.4) judging whether the data in the corresponding register is 0, if so, writing the data into the register, and simultaneously writing the data into the data state register 0, and skipping to execute the step 3.5); if not 0, writing the data into the register, keeping the data state register unchanged, and skipping to execute the step 3.5);
3.5) ending the register access and exiting.
5. The method for accessing a register file with low power consumption according to claim 1, wherein the detailed step of step 4) comprises:
4.1) judging whether the data reading operation performed on each body of the register is effective or not, if not, skipping to execute the step 4.5), otherwise, skipping to execute the step 4.2);
4.2) judging whether the read operation of the register is read 0 operation, if so, skipping to execute the step 4.3), otherwise, skipping to execute the step 4.4);
4.3) directly clearing 0 of the corresponding data output port without reading the content of the register, and skipping to execute the step 4.5);
4.4) reading data from the register and then outputting the data to a corresponding data output port;
4.5) ending the register access and exiting.
6. A low power access apparatus for a register file, comprising:
the register splitting program unit is used for splitting each register in advance, adding a data state register for marking data as 0 or non-0 for each body of the register, respectively adding control signals for writing 0 and reading 0 for an access port of each body of the register, and enabling the corresponding control signals to be effective when the actual access data of the register is invalid;
the access request intercepting program unit is used for intercepting the access request of the register access port and judging the type of the access request, and if the type of the access request is write, the program unit skips to execute the write operation; if the type of the access request is read, skipping to execute a read operation program unit;
the write-in operation program unit is used for performing data write-in operation on the register, write-in 0 control is added on the basis of the write-in mode of the original register, and when the write-in 0 control is not 0, 0 is written in the register and the corresponding data state register is updated to be in a non-0 state;
and the reading operation program unit is used for reading data of the register, adding reading 0 control to the original reading mode of the register, and directly clearing 0 of the corresponding data output port without reading the content of the register during reading 0 control.
7. A low power access arrangement for a register file, comprising a microprocessor with a register file, characterized in that the microprocessor is programmed to perform the steps of the low power access method for a register file according to any of claims 1-5.
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