CN103425460A - Writing back and discarding method of low-power-consumption register file - Google Patents
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Abstract
The invention belongs to the technical field of microprocessors, and particularly relates to a writing back and discarding method of a low-power-consumption register file. Based on the existing microprocessor, the method comprises the following steps: expanding an original MIPS (million instructions per second) instruction set for the microprocessor; increasing three bits of life length in an instruction with a redundancy bit, so as to show that the current register variable is used by follow-up instructions; the adjustment logic of the life length is increased at an executive level, an accessing level and an aligning level, if the current register variables are used by the follow-up instructions, 1 is reduced to the life length; once the life length of the current register variables is 0, the shielding logic based on a selector and the register is discarded; and a static speculation algorithm of the life length of the instruction register is realized by software tools. Compared with the existing framework, with the adoption of the writing back and discarding method of the low-power-consumption register file, the discardable register variables can be effectively discovered under the condition that the hardware expenditure is nearly not increased, so that the power consumption and the power consumption density of the register file are lowered.
Description
Technical field
The invention belongs to the microprocessor technology field, be specifically related to a kind of low-power consumption register file write back discarding method.
Background technology
Register file is first order storage unit in processor, it is the core component of Modern microprocessor, because the access to register file presents at a high speed, the characteristics of high frequency, the power consumption of the register file that is and power dissipation density are all quite large, to such an extent as to become the energy of microprocessor, consume critical piece and power consumption focus.High energy consumption to microprocessor particularly the microprocessor in Embedded Application field challenge has been proposed, and the power consumption focus more can cause circuit stability and life-span to descend.Therefore, research reduces the register file power consumption very important realistic meaning.
Fig. 1 has showed the microprocessor architecture figure of 6 traditional level production lines.Comprised instruction fetch stage, decode stage, execution level, visit storage level, alignment level and write back level.
In traditional microprocessor architecture design, for writing back of register file, do not have special circuit to be controlled, the useless operation that writes back may appear in the actual instruction implementation, but these operate in traditional microprocessor architecture design not can conductively-closed, thereby caused unnecessary energy consumption, for this shortcoming, need to have been controlled writing back of register file, once find that useless writing back operation will write back accordingly behaviour abandons, thereby reduce the access power consumption of register file.
Summary of the invention
The object of the present invention is to provide a kind of register file that can reduce the access power consumption to write back discarding method.
The present invention by inserting the label of the life length that characterizes the present instruction destination register in some instruction, and carry out reducing of life length in execution level, memory access level and alignment level, judge whether current destination register needs to write back (abandoning writing back for 0 if), thereby reduce register file useless write back power consumption, also reduce the power dissipation density of register file, improve stability and the life-span of circuit simultaneously.
The register file that can reduce the access power consumption provided by the invention writes back discarding method, the MIPS microprocessor of existing basic pipeline structure of take is basis, and described existing microprocessor comprises instruction fetch stage, decode stage, execution level, visit storage level, alignment level and writes back a grade (see figure 1); Concrete steps are:
(1) to this microprocessor, expand original MIPS instruction set, increase " the life length " of 3 and characterize current register variable and will be used by several subsequent instructions in the instruction that redundant digit is arranged;
In the present invention, the life length of register X is defined as follows: as register X at the E(execution level), M(memory access level), the A(level of aliging) when level, if register X has 1,2 or 3 subsequent instructions in its feedback scope need to use register X, the life length of register X is designated as 1,2 or 3 with regard to correspondence; If register X has the subsequent instructions that exceeds the feedback scope need to use register X, the life length of register X just is defined as 4.The feedback scope definition is: when certain the instruction Y at decode stage (D level) has used register X, and the instruction Z that produces register X is in E, M or A level, claim the Y instruction in the Z instruction produces the feedback scope of register X, for example, in Fig. 2, mean that it is in the feedback scope as register $ 1 during in E, M, A level, once surpass this scope, such as register $ 1 has been used in an instruction below, the subsequent instructions that is defined as register $ 1 has exceeded the feedback scope.
(2), on the basis of above-mentioned expansion MIPS instruction set, increase " life length " in execution level, memory access level and alignment level and adjust logic: if current register variable is used by follow-up instruction, its " life length " is reduced to 1; Once find that " the life length " of current register variable is 0, it abandoned by the mask logic based on selector switch-register.Concrete step is: if the instruction that the 1 current instruction destination register that is in execution level, memory access level or alignment level is positioned at decode stage is used, the tag of " the life length " in present instruction is just subtracted 1; If the value of the tag of " life length " in 2 present instructions is kept to 0, the data that pass to next stage will remain unchanged, and characterize signal that register file writes back, will be set to invalidly, thereby in the end write back level, this register variable can not write back.What deserves to be explained is, above-mentioned steps has identical structure in execution level, memory access level and alignment level.
Further, the present invention also provides the algorithm of the static speculative computation of order register life length, this algorithm is realized by Software tool, this Software tool can staticly travel through the assembly code generated, definite needs add " the life length " of the register variable in the instruction of " life length ", and it is embedded into to the redundant digit of present instruction.
The algorithm of the static speculative computation of described order register life length comprises a main algorithm and two subalgorithms, main algorithm is called for short algorithm I, two subalgorithms are respectively: life cycle calculations (inGroupLifetimeCalculation) in group, be called for short algorithm II, outer the writing of group abandons judgement calculating (outOfGroupWriteDiscardingJudgement), is called for short algorithm III; Appendix is shown in by the code of the static supposition of order register life length algorithm.
Main algorithm calls two subalgorithms, and the step of main algorithm is as follows:
(1), for every instruction in the assembly code of present procedure, at first calling algorithm II calculates the life cycle life in group and writes and abandon signal wd, if algorithm II has returned to effective wd signal (meaning that algorithm II determines that this register can be dropped in group), algorithm I just is defined as life by the life of this order register so, if life equals 4, show that the register of determining this instruction in group can not be dropped, algorithm I just is set to 4 by life, otherwise means that calling separately algorithm II can't determine whether to abandon;
(2), further called algorithm III, can abandon if algorithm III determines, the register life time of instruction has been set to the rreturn value of algorithm III, otherwise it is set to 4.
Algorithm II is supposition in group, and its step is as follows:
(1), in 3 subsequent instructions of the follow-up selection of present instruction, form groups (group), when present instruction, when postponing groove, according to branch, occur and do not occur, can obtain two groups, as shown in appendix (II-a);
(2), define three concept: distance, it is distance, the register that means present instruction will be used by follow-up instruction every how many clock period, if distance is greater than 3, be set to without exception 4, dependent, it is dependence, mean whether present instruction depends on article one instruction, relying on the meaning is the destination register of the operand of present instruction from article one instruction, rewrite, override, whether the destination register that means present instruction is consistent with article one instruction, unanimously for overriding, otherwise not for overriding; As shown in appendix (II-b);
(3), at first algorithm II obtain instruction group corresponding to present instruction, then fills in the form shown in appendix (II-b), then starts to check one by one subsequent instructions, if A finds that there is instruction and depends on article one instruction, and distance is 4, the life cycle of article one instruction is set to 4, exits; If B has dependence and distance to be less than 4, life cycle adds 1; C, if there is overriding, judge whether life cycle is 4, if words can not abandon, otherwise can abandon, return to life cycle, as shown in appendix (II-c).
Algorithm III is the outer judgement of group, because this algorithm can travel through whole program, considers the take-off point that may exist in program, has introduced a container and has carried out the take-off point in save routine.The concrete steps of algorithm III are:
(1) if judging present instruction is used by subsequent instructions, mean that the register of present instruction can not be dropped, return to 0, finish;
(2) otherwise, if judge, the register of present instruction has been override by follow-up instruction or the end that reaches program exports, and opens the judgement of next round;
(3) if lower instruction is conditional branch instructions, must judge so whether branch the Liang Tiao road occurs simultaneously, here branch node is deposited in branch's container, it should be noted that if found this branch node in branch's container, reached this take-off point before meaning, mean and ring occurred, need to reject ring, otherwise deposit branch in container, and first judge the branch road of branch's success, and then the branch road of judgement branch failure, until reach said condition in step (2), algorithm finishes.
The inventive method, after compiler generates software code, adopts the strategy of overall situation traversal, determines " life length " that some register variables are accessed by subsequent instructions.The algorithm that the present invention proposes possesses the life length of inference register variable when static state compiles, and by the support of instruction framework, embed the life length of register in instruction, when operation, dynamically adjust the life length of variable, determine whether to write back according to life length when program is moved, if life length be zero maskable to register write back.The present invention has saved the operation that writes back of unnecessary register, thereby has reduced the power consumption of register file.
With existing framework, compare, the register file of software tip provided by the invention writes back discarding method, can be in the situation that increase hardly hardware spending, the register variable that discovery can abandon effectively, thereby power consumption and the power dissipation density of reduction register file.
The accompanying drawing explanation
Fig. 1 is 6 traditional level production line microprocessor architecture designs.
Fig. 2 is the definition example of register life length.
Fig. 3 is that register file is write the concrete decision logic abandoned.
Fig. 4 is the concrete implementation strategy that instruction register life length label inserts.
Embodiment
The register file that the invention describes a kind of software tip writes back the technology of abandoning.Various example of the present invention and design philosophy have wherein below been set forth.
Fig. 2 is for the example of register life length definition is described.If have 1 in the feedback scope, 2, the destination register that 3 subsequent instructions have been used present instruction its life is defined as 1, 2, 3, if being arranged, the instruction that exceeds the feedback scope uses this register, its life is defined as 4, concrete example, in Fig. 2, if it (is subu 3 that 1 register only has its follow-up three instructions, $ 1, $ 7, lw $ 10, 4 ($ 1) and mul $ 11, $ 6, $ 1 these three instructions) use, its life is 3, but, if (the slt $ 3 of the instruction shown in redness, $ 1, $ 8) also used $ 1, this instruction has exceeded the feedback scope of $ 1, the life length of $ 1 will be set to 4.Wherein, the feedback scope is defined as: when certain the instruction Y at decode stage (D level) has used register X, and the instruction Z of generation register X is in E, M or A level, claims the Y instruction in the Z instruction produces the feedback scope of register X.
Fig. 3 has showed that register file writes the concrete decision logic abandoned.The structure traditional with Fig. 1 compared, and this structure has increased the decision logic to life cycle tag, and Fig. 3 be take the E level and is described as example, and the structure of M level and A level is just the same.Whether the register that at first judges current instruction is fed back to D level (must be that feedback hiting signal effective (being that the signal bypass-hit signal shown in Fig. 3 is effective) and d level now can not be blocked (being that the d_stall signal shown in Fig. 3 is 0)), if words current life cycle tag is carried out from subtracting, then judge whether that current tag is 0, for the life of null representation present instruction register is 0, can abandon, abandon the circuit structure adopted based on register-selector switch, the characteristics of this structure are, if life tag is 0, the register data that passes to next stage is held constant, and, the sign register file writes back signal X_wr_sig(X and represents E, M and A, in Fig. 3 with E level example, so X is E) will be set to 0, thereby writing back of mask register heap.
Fig. 4 shows the concrete implementation strategy that order register life length label inserts.In actual logical design, we are distinguished the instruction of R type and the instruction of I type, for the instruction of R type, because it always has the redundant digit of 5bit, therefore tag can be inserted into to redundant digit.For the instruction of I type, need to distinguish the scope of immediate, if the scope of immediate is between-4096 ~ 4095, tag can be inserted into to the high 3 of number field immediately, otherwise, introduce a new instruction lli, then original instruction is split as to lli instruction and the instruction of a R type, the life cycle of lli instruction is 1 and the life cycle tag of R type instruction is consistent with I type instruction before, and can have the redundant digit of 5bit to insert tag.
The algorithm of the life cycle of static determine/presumptive instruction register variable when appendix has been showed by compiling.In algorithm I, listed algorithm is overall algorithm, two subalgorithms have been called, respectively: life cycle calculations in the inGroupLifetimeCalculation(group, as shown in appendix (II)) and outer the writing of outOfGroupWriteDiscardingJudgement(group abandon judgement, as shown in appendix (III)).The step of algorithm I is: for every instruction in the assembly code of present procedure, at first calling algorithm II calculates the life cycle life in group and writes and abandon signal wd, if algorithm II has returned to effective wd signal (meaning that algorithm II determines that this register can be dropped in group), algorithm I just is defined as life by the life of this order register so, if life equals 4, show that the register of determining this instruction in group can not be dropped, algorithm I just is set to 4 by life, otherwise mean that unitary call algorithm II can't determine whether to abandon, further called algorithm III, if determining, algorithm III can abandon, the register life time of instruction is set to the rreturn value of algorithm III, otherwise it is set to 4.
Algorithm II infers in group, the steps include: to form a group (group) in 3 subsequent instructions of follow-up selection of present instruction, when present instruction, when postponing groove, according to branch, occurs and does not occur, and can obtain two groups, as shown in appendix (II-a).As shown in appendix (II-b), three concepts have been defined again: the distance(distance, the register that means present instruction will be used by follow-up instruction every how many clock period, if distance is greater than 3, be set to without exception 4), the dependent(dependence, mean whether present instruction depends on article one instruction, relying on the meaning is the destination register of the operand of present instruction from article one instruction), rewrite(overrides, whether the destination register that means present instruction is consistent with article one instruction, unanimously for overriding, otherwise not for overriding).As shown in appendix (II-c), at first algorithm II obtains instruction group corresponding to present instruction, then fill in the form shown in appendix (II-b), then start to check one by one subsequent instructions, depend on article one instruction if 1 finds that there is instruction, and distance is 4, the life cycle of article one instruction is set to 4, exits; If 2 have dependence and distance to be less than 4, life cycle adds 1; 3, if there is overriding, judge whether life cycle is 4, if words can not abandon, otherwise can abandon, return to life cycle.
Algorithm III is the outer judgement of group, because this algorithm can travel through whole program, considers the take-off point that may exist in program, has introduced a container and has carried out the take-off point in save routine.The step of algorithm III is: if 1 judge present instruction and used by subsequent instructions, mean that the register of present instruction can not be dropped, return to 0, finish; 2 otherwise, if judge, the register of present instruction has been override by follow-up instruction or the end that reaches program exports, and opens the judgement of next round; If 3 lower instructions are conditional branch instructions, must judge so whether branch the Liang Tiao road occurs simultaneously, here branch node is deposited in branch's container, it should be noted that if found this branch node in branch's container, reached this take-off point before meaning, mean and ring occurred, need to reject ring, otherwise deposit branch in container, and first judge the branch road of branch's success, and then the branch road of judgement branch failure, until reach said condition in 2, algorithm finishes.
Appendix
Algorithm: the static state of life cycle is inferred
Input: source program assembly code
Parameter: present instruction
Curr_instr, source program
Src_instr
Life cycle
Life, write back and abandon
Wd, counter
I, number of instructions instr_#
Output:The life cycle array
Life_arr
Initialization:In the middle of being converted into, assembly code expresses
00: foreach(
i∈ [
0,
instr_# ))
01:
curr_instr =
getInstr(
i );
src_instr =
curr_instr
02:
wd =
inGroupLifetimeCalculation(&
curr_instr , &
life )
03:if(
Wd )
Life_arr [
i ]=
Life ;
Continue;
Endif/ * wd is effective
, take off the bar instruction*/
04: If(
Life ==4)
Life_arr [
i ]=4;
Continue;
Endif/ * can not abandon
, lower instruction*/
05: wd =
outOfGroupWriteDiscardingJudgement(
src_instr ,
curr_instr )
06: If(
Wd )
Life_arr [
i ]=
Life ;
Continue;
Endif/ * wd is effective, take off bar instruction */
07: Life_arr [
i ]=4/* is conservative to be inferred, life cycle is 4, take off bar instruction */
08: endfor
（I）
Algorithm: life cycle calculations in group
Input: present instruction
Curr_instr ,
Life cycle life
Parameter: four instructions group
Group , accelerator
I, the distance of row ,
Dependent ,
Rewrite
Output:Write and abandon
Wd
Initialization:
Group=
GetGroup(
Curr_instr );
FillThreeColumns(
Group );
i =0;
Life =0;
Wd =0
00: while(
i ≤2 && (
dependent [
i ] || !
rewrite [
i ]))
01: if(
dependent [
i ] &&
distance [
i ] == 4)
life = 4;
wd = 0;
break;
endif
02: if(
dependent [
i ] &&
distance [
i ] != 4)
life ++;
endif;
03: if(
rewrite [
i ])
break;
endif;
i ++
04: endwhile
05: if(
rewrite [
i ] &&
life != 4)
wd = 1;
return
wd ;
endif /*
rewrite in-range detected */
06: updateCurrInstrToLastInstrOfGroup(
group );
return
wd
（c）
（II）
Algorithm: outer the writing of group abandons judgement
Input: source program
Src_instr ,
Present instruction curr_instr
Parameter: lower bar instruction
Next_instr
, the take-off point container
Bp
00: bp .
clear();
bp .
push_back(
curr_instr )
01: while(!
bp .
empty())
02:
next_instr =
getNextInstr(
bp .
pop_back())
03: while(1)
04: If(
IsConsumer(
Src_instr ,
Next_instr ))
Return0;
Endif/ *
Find writeafterread*/
05: if(
isRewrite(
src_instr ,
next_instr ) ||
isReachEnd(
next_instr ))
06: Break; Endif/ * does not have writeafterread, lower whorl supposition */
07: if(
isConditionalBranch(
next_instr ))
08: If(
Bp .
Find(
Next_instr ))
Break; Endif/ * detects ring, lower whorl supposition */
09: Bp .
Push_back(
Next_instr )/* is ring not, preserve take-off point to container */
10:
Next_instr =
GetInstrFromBranchSucc(
Next_instr )/* branch successfully infer */
11:
endif
12: else next_instr =
getNextInstr(
next_instr )
endelse
13: endwhile
14: endwhile
15: return 1
（III）
Claims (2)
1. the register file of a low-power consumption writes back discarding method, and the MIPS microprocessor of existing basic pipeline structure of take is basis, and described existing microprocessor comprises instruction fetch stage, decode stage, execution level, visit storage level, alignment level and writes back level; It is characterized in that concrete steps are:
(1) to described microprocessor, expand original MIPS instruction set, increase " the life length " of 3 and characterize current register variable and will be used by several subsequent instructions in the instruction that redundant digit is arranged;
Wherein, the life length of register X is defined as follows: as register X during in execution level (E), memory access level (M), alignment level (A) level, if register X has 1,2,3 subsequent instructions in its feedback scope need to use register X, the life length of register X is designated as 1,2,3 with regard to corresponding; If register X has the subsequent instructions that exceeds the feedback scope need to use register X, the life length of register X just is defined as 4;
(2), on the basis of above-mentioned expansion MIPS instruction set, increase " life length " in execution level, memory access level and alignment level and adjust logic: if current register variable is used by follow-up instruction, its " life length " is reduced to 1; Once find that " the life length " of current register variable is 0, it abandoned by the mask logic based on selector switch-register.
2. method according to claim 1, it is characterized in that, further carry out the static speculative computation of order register life length, this calculating is realized by Software tool, the assembly code that the static traversal of this Software tool generates, definite needs add " the life length " of the register variable in the instruction of " life length ", and it is embedded into to the redundant digit of present instruction; The algorithm of the static speculative computation of described order register life length comprises: a main algorithm and two subalgorithms, main algorithm is called for short algorithm I, two subalgorithms respectively: life cycle calculations in group, be called for short algorithm II, outer the writing of group abandons judgement calculating, is called for short algorithm III; The step of main algorithm is as follows:
(1) for every instruction in the assembly code of present procedure, at first calling algorithm II calculates the life cycle life in group and writes and abandon signal wd, if algorithm II has returned to effective wd signal, mean that algorithm II determines that this register can be dropped in group, algorithm I just is defined as life by the life of this order register so; If life equals 4, show that the register of determining this instruction in group can not be dropped, algorithm I just is set to 4 by life; Otherwise mean that calling separately algorithm II can't determine whether to abandon; So
(2) further call algorithm III, can abandon if algorithm III determines, the register life time of instruction is set to the rreturn value of algorithm III, otherwise it is set to 4;
Wherein, algorithm II step is as follows:
(1) 3 subsequent instructions of follow-up selection in present instruction form a group (group), when present instruction, when postponing groove, according to branch, occur and do not occur, and obtain two groups;
(2) define three concept: distance, distance, mean that the register of present instruction will be used by follow-up instruction every how many clock period, if distance is greater than 3, is set to without exception 4; Dependent, dependence, mean whether present instruction depends on article one instruction, relying on the meaning is the destination register of the operand of present instruction from article one instruction; Rewrite, override, and means that whether the destination register of present instruction is consistent with article one instruction, unanimously for overriding, otherwise not for overriding;
(3) at first algorithm II obtains instruction group corresponding to present instruction, then fill in step (2) form of three concept: distance, dependent, rewrite institute respective items, then start to check one by one subsequent instructions, if A finds that there is instruction and depends on article one instruction, and distance is 4, the life cycle of article one instruction is set to 4, exits; If B has dependence and distance to be less than 4, life cycle adds 1; C, if there is overriding, judge whether life cycle is 4, if words can not abandon, otherwise can abandon, return to life cycle;
Algorithm III step is as follows:
(1) if judging present instruction is used by subsequent instructions, mean that the register of present instruction can not be dropped, return to 0, finish;
(2) otherwise, if judge, the register of present instruction has been override by follow-up instruction or the end that reaches program exports, and opens the judgement of next round;
(3) if lower instruction is conditional branch instructions, must judge so whether branch the Liang Tiao road occurs simultaneously, here branch node is deposited in branch's container, if found this branch node in branch's container, reached this take-off point before meaning, mean and ring occurred, need to reject ring, otherwise deposit branch in container, and first judge the branch road of branch's success, and then the branch road of judgement branch failure, until reach said condition in step (2), algorithm finishes.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108958453A (en) * | 2018-07-03 | 2018-12-07 | 中国人民解放军国防科技大学 | Low-power-consumption access method and device for register file |
| WO2021147449A1 (en) * | 2020-01-23 | 2021-07-29 | Huawei Technologies Co., Ltd. | Method and apparatus for predicting and scheduling copy instruction for software pipelined loops |
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| CN1758229A (en) * | 2005-10-28 | 2006-04-12 | 中国人民解放军国防科学技术大学 | Local space shared memory method of heterogeneous multi-kernel microprocessor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108958453A (en) * | 2018-07-03 | 2018-12-07 | 中国人民解放军国防科技大学 | Low-power-consumption access method and device for register file |
| CN108958453B (en) * | 2018-07-03 | 2020-06-05 | 中国人民解放军国防科技大学 | Low-power-consumption access method and device for register file |
| WO2021147449A1 (en) * | 2020-01-23 | 2021-07-29 | Huawei Technologies Co., Ltd. | Method and apparatus for predicting and scheduling copy instruction for software pipelined loops |
| US11366646B2 (en) | 2020-01-23 | 2022-06-21 | Huawei Technologies Co., Ltd. | Method and apparatus for predicting and scheduling copy instruction for software pipelined loops |
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