CN108933178A - A kind of electronic synapse device and production method - Google Patents

A kind of electronic synapse device and production method Download PDF

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Publication number
CN108933178A
CN108933178A CN201810734872.9A CN201810734872A CN108933178A CN 108933178 A CN108933178 A CN 108933178A CN 201810734872 A CN201810734872 A CN 201810734872A CN 108933178 A CN108933178 A CN 108933178A
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oxide
doped
heavily
threadiness
medium
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CN108933178B (en
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赖云锋
陈凡
陈帅
程树英
林培杰
俞金玲
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Fuzhou University
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Fuzhou University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Abstract

It include heavily-doped Si/silicon dioxide substrates, oxide threadiness medium, source electrode and drain electrode the present invention relates to one kind;Heavily-doped Si/the silicon dioxide substrates, heavily-doped Si is as grid;The oxide threadiness medium is set to above heavily-doped Si/silicon dioxide substrates, as conducting channel;The source electrode and drain electrode is respectively arranged at the both ends of oxide threadiness medium, and is formed and be in electrical contact with heavily-doped Si/silicon dioxide substrates.Its resistance adjustment linearity is enhanced after the present invention is plasma treated, the weight for reducing transition process is lost, so that the device is more advantageous to and uses as electronic synapse.

Description

A kind of electronic synapse device and production method
Technical field
The present invention relates to technical field of microelectronic devices, more particularly to a kind of electronic synapse device and production method.
Background technique
For the limitation for breaking through traditional von Neumann structure system, people start to be dedicated to realize on Single Electron device The analog simulation of cynapse behavior, to obtain the class brain computing chip for having High Density Integration and low-power consumption.Using 1-dimention nano Wire material makes the reduction that device power consumption is not only contributed to based on the electronic synapse device of three end transistors, also because of device conductance tune Adjusting range is wide, read-write carries out simultaneously and the advantages such as multichannel input, is conducive to the computing architecture of building neuromorphic.
For Single Electron cynapse device, linear weight adjusting can make the plastic process of entire device be to simplify and can be pre- It surveys.But the electronic synapse device based on transistor, there are the resistance adjustment linearity is not high, transition process weight is easy to be lost Feature.Currently, being applied to improve the scheme of electronic synapse device weight tuning linearity to be few.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of electronic synapse device and production method, for electric in improving Sub- cynapse device weight tuning linearity.
To achieve the above object, the present invention adopts the following technical scheme:
A kind of electronic synapse device, it is characterised in that: including heavily-doped Si silicon dioxide substrates, oxide threadiness medium, source electrode And drain electrode;Heavily-doped Si/the silicon dioxide substrates, heavily-doped Si is as grid;The oxide threadiness medium is set to heavily doped Above silicon/silicon dioxide substrate, as conducting channel;The source electrode and drain electrode is respectively arranged at oxide threadiness medium Both ends, and formed and be in electrical contact with heavily-doped Si/silicon dioxide substrates.
Further, the material of the source electrode and drain electrode is the one of metal, metal alloy or conductive metallic compound Kind.Metal is Al, Ti, Ta, Cu, Pt, Au, W, Ni or Ag;The metal alloy is Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Cu/ Al, Ti/W or Al/Zr;The conductive compound is TiN, TiW, TaN, WSi, AZO, ITO or FTO;
Further, the oxide includes ZnO, CuO, Cu2O、NiO、Al2O3、TiO2Or MgO.
Further, the electronic synapse device manufacture method, comprising the following steps:
Step S1: plasma treatment is carried out to oxide threadiness medium;
Step S2: by treated, oxide threadiness medium is set to heavily-doped Si/silicon dioxide substrates top;
Step S3: a pair of electrodes is made at oxide both ends, makes electrode and the oxide threadiness medium and heavily-doped Si/titanium dioxide Silicon substrate forms good contact.
Further, the step S1 specifically:
Step S11: the oxide threadiness medium is placed in chamber, and is evacuated to 0.1Pa or less;
Step S12: being passed through specific gas in the cavity, and keeping chamber pressure is 0.1-100Pa;
Step S13: applying 10 ~ 300W radio-frequency power to chamber makes specific gas plasma, and keeps plasma gas to line The action time of shape oxide is 1 ~ 3600s.
Further, the specific gas is Ar, O2、NH3、H2、CHF3、CF4、SF6One or more of gas.
Further, the step S3 specifically: the oxide threadiness medium both ends by sputtering, PECVD, MOCVD, ALD, MBE, PLD or the method for evaporation make a pair of electrodes.
Compared with the prior art, the invention has the following beneficial effects:
The present invention introduces defect by corona treatment medium of oxides in the medium, and transistor is made sluggish behavior occur, from And the linearity of electronic synapse device weight adjusting is improved, the weight for reducing transition process is lost, so that the plastic process of device is more Add uniform, simplifying and predictable.In addition to this, plasma-treating technology and current process compatible, less increase at Device cynapse performance can be improved in the case where this.
Detailed description of the invention
Fig. 1 is schematic structural view of the invention;
Fig. 2 is the transfer characteristic curve of plasma-treated front and back transistor in one embodiment of the invention;
Fig. 3 is transistor not plasma-treated in one embodiment of the invention under unidirectional pulse mode, resistance it is continuous Adjustment process and its linearity statistical chart;
Fig. 4 is transistor plasma treated in one embodiment of the invention under unidirectional pulse mode, resistance it is continuous Adjustment process and its linearity statistical chart.
In figure: 01- source electrode, 02- oxide lines, 03- drain electrode, 04- heavily-doped Si/silicon dioxide substrates.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and embodiments.
Fig. 1 is please referred to, the present invention provides a kind of electronic synapse device, it is characterised in that: including heavily-doped Si/silicon dioxide liner Bottom, oxide threadiness medium, source electrode and drain electrode;Heavily-doped Si/the silicon dioxide substrates, heavily-doped Si is as grid;It is described Oxide threadiness medium is set to above heavily-doped Si/silicon dioxide substrates, as conducting channel;The source electrode and drain electrode point It is not set to the both ends of oxide threadiness medium, and is formed and is in electrical contact with heavily-doped Si/silicon dioxide substrates.
In an embodiment of the present invention, the material of the source electrode and drain electrode is metal, metal alloy or conductive metal One kind of compound.Metal is Al, Ti, Ta, Cu, Pt, Au, W, Ni or Ag;The metal alloy is Pt/Ti, Ti/Ta, Cu/ Ti, Cu/Au, Cu/Al, Ti/W or Al/Zr;The conductive compound is TiN, TiW, TaN, WSi, AZO, ITO or FTO;
In an embodiment of the present invention, further, the oxide includes ZnO, CuO, Cu2O、NiO、Al2O3、TiO2Or MgO。
In an embodiment of the present invention, the electronic synapse device manufacture method specifically includes the following steps:
Step S1: plasma treatment is carried out to oxide threadiness medium;
Step S2: by treated, oxide threadiness medium is set to heavily-doped Si/silicon dioxide substrates top;
Step S3: a pair of electrodes is made at oxide both ends, makes electrode and the oxide threadiness medium and heavily-doped Si titanium dioxide Silicon substrate forms good contact.
In an embodiment of the present invention, the step S1 specifically:
Step S11: the oxide threadiness medium is placed in chamber, and is evacuated to 0.1Pa or less;
Step S12: being passed through specific gas in the cavity, and keeping chamber pressure is 0.1-100Pa;
Step S13: applying 10 ~ 300W radio-frequency power to chamber makes specific gas plasma, and keeps plasma gas to line The action time of shape oxide is 1 ~ 3600s.
In an embodiment of the present invention, the specific gas is Ar, O2、NH3、H2、CHF3、CF4、SF6One of gas Or it is several.
In an embodiment of the present invention, the step S3 specifically: the oxide threadiness medium both ends by sputtering, PECVD, MOCVD, ALD, MBE, PLD or the method for evaporation make a pair of electrodes.
In an embodiment of the present invention, the heavily-doped Si of the substrate is p-type or N-type, and corresponding silicon dioxide thickness is 50nm, 100nm or 300nm.
Embodiment 1:
A kind of its structure of electronic synapse device as shown in Figure 1, by heavily-doped Si/silicon dioxide substrates 04, with a thickness of the Ti of 110 nm As source electrode 01, length be 10 μ m diameters be 100 nm linear zinc oxide as medium 02, make with a thickness of the Ti of 110 nm For the composition of drain electrode 03.
Plasma bombardment processing is carried out to zinc oxide nanowire, specific production step is as follows:
Firstly, being handled ZnO nano-wire 120 seconds using 100 watts of argon plasmas, then by the ZnO nano-wire after corona treatment It is sprinkling upon on heavily-doped Si/silicon dioxide substrates, then source-drain electrode is produced on ZnO nano-wire by way of magnetron sputtering.
Electrical testing is carried out to the transistor in the present embodiment, Fig. 2 is the transfer of plasma-treated front and back transistor Characteristic curve, wherein applying DC voltage sweep in grid when test, drain electrode applies read voltage and source electrode is grounded.Experiment discovery etc. Gas ions processing can make transistor sluggish behavior occur.Fig. 3 is the conductance without plasma generating device under pulse excitation (weight) continuously adjusts and adjustment process linearity statistical chart, it is found that the adjustment process is similar in biological neural cynapse and connect The adjustment process of intensity.Fig. 4 is under pulse excitation, and the weight of plasma treated device continuously adjusts and its adjustment process Linearity statistical chart.It is found that corona treatment can reduce the β value of device weight enhancing process compared with untreated device, Enhance weight tuning linearity, this makes the plastic process of entire device be more simplified and predictable.Furthermore it is also possible to It was found that the device after corona treatment, which enhances/reduce weight, adjusts the weight loss of transition process considerably less than without plasma The device of body processing, these improvement are conducive to application of the device in terms of electronic synapse.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with Modification, is all covered by the present invention.

Claims (6)

1. a kind of electronic synapse device, it is characterised in that: including heavily-doped Si/silicon dioxide substrates, oxide threadiness medium, source electricity Pole and drain electrode;Heavily-doped Si/the silicon dioxide substrates, heavily-doped Si is as grid;The oxide threadiness medium is set to weight It mixes above silicon/silicon dioxide substrate, as conducting channel;The source electrode and drain electrode is respectively arranged at oxide threadiness medium Both ends, and formed and be in electrical contact with heavily-doped Si/silicon dioxide substrates.
2. a kind of electronic synapse device according to claim 1, it is characterised in that: the material of the source electrode and drain electrode For one kind of metal, metal alloy or conductive metallic compound.
3. a kind of electronic synapse device according to claim 1, it is characterised in that: the oxide include ZnO, CuO, Cu2O、NiO、Al2O3、TiO2Or MgO.
4. a kind of production method of electronic synapse device according to claim 1, it is characterised in that: the following steps are included:
Step S1: plasma treatment is carried out to oxide threadiness medium;
Step S2: by treated, oxide threadiness medium is set to heavily-doped Si/silicon dioxide substrates top;
Step S3: a pair is made by the method for sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation at oxide both ends Electrode forms electrode with the oxide threadiness medium and heavily-doped Si/silicon dioxide substrates and well contacts.
5. a kind of production method of electronic synapse device according to claim 4, it is characterised in that: the step S1 is specific Are as follows:
Step S11: the oxide threadiness medium is placed with chamber, and is evacuated to 0.1Pa or less;
Step S12: being passed through specific gas in the cavity, and keeping chamber Kia is 0.1-100Pa;
Step S13: applying 10 ~ 300W radio-frequency power to chamber makes specific gas plasma, and keeps plasma gas to line The action time of shape oxide is 1 ~ 3600s.
6. a kind of production method of electronic synapse device according to claim 5, it is characterised in that: the specific gas is Ar、O2、NH3、H2、CHF3、CF4、SF6One or more of gas.
CN201810734872.9A 2018-07-06 2018-07-06 Electronic synapse device and manufacturing method thereof Active CN108933178B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920912A (en) * 2019-03-28 2019-06-21 江苏师范大学 A kind of bionical device of multi-functional cynapse and preparation method thereof
CN113964221A (en) * 2021-10-12 2022-01-21 闽都创新实验室 Electronic synapse device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130329499A1 (en) * 2012-06-09 2013-12-12 Seoul National University R&Db Foundation Memory cell string based on gated-diode cell and memory array using the same
CN106098936A (en) * 2016-07-26 2016-11-09 福州大学 A kind of memristor and the method strengthening its electronic synapse function
CN106653850A (en) * 2016-09-23 2017-05-10 南京大学 Artificial nerve synapse transistor based on graphene/carbon nanotube composite absorbing layer
CN106910773A (en) * 2017-02-21 2017-06-30 南京大学 Multi-gate Neuron MOS transistor and preparation method thereof and the neutral net for constituting

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130329499A1 (en) * 2012-06-09 2013-12-12 Seoul National University R&Db Foundation Memory cell string based on gated-diode cell and memory array using the same
CN106098936A (en) * 2016-07-26 2016-11-09 福州大学 A kind of memristor and the method strengthening its electronic synapse function
CN106653850A (en) * 2016-09-23 2017-05-10 南京大学 Artificial nerve synapse transistor based on graphene/carbon nanotube composite absorbing layer
CN106910773A (en) * 2017-02-21 2017-06-30 南京大学 Multi-gate Neuron MOS transistor and preparation method thereof and the neutral net for constituting

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920912A (en) * 2019-03-28 2019-06-21 江苏师范大学 A kind of bionical device of multi-functional cynapse and preparation method thereof
CN109920912B (en) * 2019-03-28 2023-02-03 江苏师范大学 Multifunctional synapse bionic device and preparation method thereof
CN113964221A (en) * 2021-10-12 2022-01-21 闽都创新实验室 Electronic synapse device and manufacturing method thereof
CN113964221B (en) * 2021-10-12 2023-09-05 闽都创新实验室 Electronic synaptic device and its making method

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