CN108933134B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN108933134B
CN108933134B CN201710375328.5A CN201710375328A CN108933134B CN 108933134 B CN108933134 B CN 108933134B CN 201710375328 A CN201710375328 A CN 201710375328A CN 108933134 B CN108933134 B CN 108933134B
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type semiconductor
semiconductor layer
carbon nanotube
conductive film
semiconductor device
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CN108933134A (zh
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张金
魏洋
姜开利
范守善
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Priority to CN201710375328.5A priority Critical patent/CN108933134B/zh
Priority to TW106121847A priority patent/TWI667191B/zh
Priority to US15/916,423 priority patent/US10424638B2/en
Priority to JP2018084921A priority patent/JP6546679B2/ja
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Abstract

一半导体器件，该半导体器件包括：一栅极及一绝缘层，所述绝缘层设置于栅极的表面；一第一碳纳米管及一第二碳纳米管，所述第一碳纳米管和第二碳纳米管间隔设置于绝缘层的表面；一P型半导体层及一N型半导体层，所述P型半导体层覆盖第一碳纳米管，并设置于绝缘层的表面，所述N型半导体层覆盖第二碳纳米管，并设置于绝缘层的表面；一导电膜，所述导电膜设置于P型半导体层和N型半导体层的表面，其中，P型半导体层位于导电膜和第一碳纳米管之间，N型半导体层位于导电膜和第二碳纳米管之间。

Description

半导体器件
技术领域
本发明涉及一种半导体器件。
背景技术
近年来，范德华异质结是最近两年的新兴研究领域。范德华异质结通过将具有不同性质(电学以及光学等)的二维材料堆到一起，可以实现对组合而成的“新”材料的性质进行人工调控；由于层间弱的范德华作用力，相邻的层间不再受晶格必须相匹配的限制；并且，由于没有成分过渡，所形成的异质结具有原子级陡峭的载流子(势场)梯度；由于以过渡金属双硫族化物为代表的非石墨烯二维层状材料通常可以形成二类能带关系，因此以它们为基础搭建的异质结具有非常强的载流子分离能力；此外，由于超薄的厚度以及特殊的二维结构，使其具有强的栅极响应能力，以及与传统微电子加工工艺和柔性基底相兼容的特性。
发明内容
本发明提供了新型的含有范德华异质结的半导体器件。
一半导体器件，该半导体器件包括：一栅极，该栅极为一层状结构；一绝缘层，所述绝缘层设置于栅极的表面；一第一碳纳米管及一第二碳纳米管，所述第一碳纳米管和第二碳纳米管间隔设置于绝缘层的表面；一P型半导体层及一N型半导体层，所述P型半导体层覆盖第一碳纳米管，并设置于绝缘层的表面，所述N型半导体层覆盖第二碳纳米管，并设置于绝缘层的表面；一导电膜，所述导电膜设置于P型半导体层和N型半导体层的表面，其中，P型半导体层位于导电膜和第一碳纳米管之间，N型半导体层位于导电膜和第二碳纳米管之间；一第一电极，该第一电极与第一碳纳米管电连接；一第二电极，该第二电极与第二碳纳米管电连接；以及一第三电极，该第三电极与导电膜电连接。
相较于现有技术，本发明提供了一种新型的半导体器件，该半导体器件在未来的纳米电子学和纳米光电子学领域具有巨大的应用潜力。
附图说明
图1为本发明实施例提供的半导体器件的立体结构示意图。
图2为本发明实施例提供的半导体器件的侧视示意图。
图3为本发明实施例提供的半导体器件在用CMOS工作时的特征曲线图。
主要元件符号说明
半导体器件 100
栅极 102
绝缘层 104
第一碳纳米管 106
第二碳纳米管 108
P型半导体层 110
N型半导体层 112
导电膜 114
第一电极 116
第二电极 118
第三电极 120
第一多层立体结构 122
第二多层立体结构 124
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
以下将结合附图及具体实施例对本发明的半导体器件作进一步的详细说明。
请参阅图1及图2，本发明第一实施例提供一种半导体器件100。该半导体器件100包括：一栅极102、一绝缘层104，一第一碳纳米管106、一第二碳纳米管108、一P型半导体层110、一N型半导体层112、一导电膜114、一第一电极116、一第二电极118及一第三电极120。所述栅极102为一层状结构。所述绝缘层104设置于栅极102的表面。所述第一碳纳米管106和第二碳纳米管108间隔设置于绝缘层104的表面。所述P型半导体层110覆盖第一碳纳米管106，并设置于绝缘层104的表面。所述N型半导体层112覆盖第二碳纳米管108，并设置于绝缘层104的表面。所述导电膜114设置于P型半导体层110和N型半导体层112的表面。所述P型半导体层110位于导电膜114和第一碳纳米管106之间。所述N型半导体层112位于导电膜114和第二碳纳米管108之间。所述第一电极116与第一碳纳米管106电连接。所述第二电极118与第二碳纳米管108电连接。所述第三电极120与导电膜114电连接。
所述栅极102由导电材料组成，该导电材料可选择为金属、ITO、ATO、导电银胶、导电聚合物以及导电碳纳米管等。该金属材料可以为铝、铜、钨、钼、金、钛、钯或任意组合的合金。本实施例中，所述栅极102为一层状结构，绝缘层104设置于栅极102的表面，所述第一碳纳米管106、第二碳纳米管108、P型半导体层110、N型半导体层112、导电膜114、第一电极116及第二电极118均设置于绝缘层104的表面，并由栅极102和绝缘层104支撑。
所述绝缘层104的材料为绝缘材料，其厚度可以为1纳米～100微米。所述绝缘层104使第一碳纳米管106、第二碳纳米管108、P型半导体层110以及N型半导体层112与所述栅极102间隔绝缘设置。本实施例中，绝缘层104的材料为氧化硅。
所述第一碳纳米管106或第二碳纳米管108为金属型的碳纳米管。第一碳纳米管106或第二碳纳米管108的直径不限，可以为0.5纳米～150纳米，在某些实施例中，第一碳纳米管106或第二碳纳米管108的直径可以为1纳米～10纳米。优选地，第一碳纳米管106和第二碳纳米管108均为单壁碳纳米管，其直径为1纳米～5纳米。本实施例中，第一碳纳米管106和第二碳纳米管108均为金属型单壁碳纳米管，其直径为1纳米。本发明中，所述第一碳纳米管106和第二碳纳米管108直接设置在绝缘层104表面，第一碳纳米管106和第二碳纳米管108靠近栅极102，导电膜114远离栅极102，导电膜114不会在P型半导体层110和栅极102之间或者N型半导体层112与栅极102之间产生屏蔽效应，影像半导体器件100的实际应用。第一碳纳米管106和第二碳纳米管108并列设置于绝缘层104的表面，其之间的距离不限，可以根据实际应用进行调整。在一些实施例中，第一碳纳米管106和第二碳纳米管108之间的距离可以为1纳米～1厘米。第一碳纳米管106和第二碳纳米管108之间的角度不限，可以相互平行或者成一定角度设置，只需确保第一碳纳米管106和第二碳纳米管108之间互不接触。
所述P型半导体层110或N型半导体层112为一二维结构的半导体层。所述二维结构即半导体层的厚度较小，半导体层的厚度为1纳米～100纳米，优选地，所述P型半导体层110或N型半导体层112的厚度为1纳米～50纳米。所述P型半导体层110或N型半导体层112可以仅包括一层半导体材料，即所述P型半导体层110或N型半导体层112为一个单层的结构。所述P型半导体层110或N型半导体层112的材料不限，可以为无机化合物半导体、元素半导体或有机半导体材料，如：砷化镓、碳化硅、多晶硅、单晶硅或萘等。N型半导体层112的材料为N型半导体材料。P型半导体层110的材料为P型半导体材料。本实施例中，N型半导体层112的材料为硫化钼(MoS2)，其厚度为37纳米，P型半导体层110的材料为硒化钨(WSe2)，其厚度为22纳米。所述P型半导体层110和N型半导体层112间隔设置，互不接触。所述P型半导体层110覆盖第一碳纳米管106后直接设置在绝缘层104的表面。所述N型半导体层112覆盖第二碳纳米管108后直接设置在绝缘层104的表面。
所述导电膜114的材料为导电材料，可以为金属、导电聚合物或ITO。导电膜114直接沉积在P型半导体层110和N型半导体层112的远离绝缘层104的表面，导电膜114跨过P型半导体层110和N型半导体层112。由于导电膜114P半导体层110和N型半导体层112间隔设置，其间隔处的导电膜114可以设置于绝缘层104的表面。即导电膜114可以看成分成三部分，一部分位于P型半导体层110远离绝缘层104的表面；一部分位于N型半导体层112远离绝缘层104的表面；另一部分位于P型半导体层110和N型半导体层112之间，设置于绝缘层104的表面。导电膜114沉积的具体方法不限，可以为离子溅射、磁控溅射或其他镀膜方法。所述导电膜114的厚度不限，可以为5纳米～100微米。在一些实施例中，导电膜114的厚度为5纳米～100纳米；在另一些实施例中，导电膜114的厚度为5纳米～20纳米。所述导电膜114的形状不限，可以为长条形、线性、方形等形状。本实施例中，所述导电膜114为长条形。
所述第一碳纳米管106、P型半导体层110和导电膜114相互层叠形成一第一多层立体结构122。由于第一碳纳米管106相对于P型半导体层110和导电膜114的尺寸较小，该第一多层立体结构122的横截面的面积由第一碳纳米管106的直径和长度决定。由于第一碳纳米管106为纳米材料，该第一多层立体结构122的横截面面积也是纳米级。所述第一多层立体结构122定义一横向截面及一竖向截面，所述横向截面即平行于P型半导体层110的方向的截面，所述纵向截面即垂直于P型半导体层110的表面的方向的截面。所述横向截面的面积由第一碳纳米管106的直径和长度决定。所述纵向截面的面积由第一碳纳米管106的长度和第一多层立体结构122的厚度决定。优选地，该第一多层立体结构122的横截面的面积为0.25nm2～1000nm2。更优选地，该第一多层立体结构122的横截面的面积为1nm2～100nm2。
所述第二碳纳米管108、N型半导体层112和导电膜114相互层叠形成一第二多层立体结构124。由于第二碳纳米管108相对于N型半导体层112和导电膜114的尺寸较小，该第二多层立体结构124的横截面的面积由第二碳纳米管108的直径和长度决定。由于第二碳纳米管108为纳米材料，该第二多层立体结构124的横截面面积也是纳米级。所述第二多层立体结构124定义一横向截面及一竖向截面，所述横向截面即平行于N型半导体层112的方向的截面，所述纵向截面即垂直于N型半导体层112的表面的方向的截面。所述横向截面的面积由第二碳纳米管108的直径和长度决定。所述纵向截面的面积由第二碳纳米管108的长度和第二多层立体结构124的厚度决定。优选地，该第二多层立体结构124的横截面的面积为0.25nm2～1000nm2。更优选地，该第二多层立体结构124的横截面的面积为1nm2～100nm2。
第一碳纳米管106和导电膜114与二维的P型半导体层110在第一多层立体结构122处形成范德华异质结构。在应用时，第一碳纳米管106和导电膜114与P型半导体层110之间形成肖特基结，电流可以穿过该第一多层立体结构122。由于第一碳纳米管106为纳米材料，该第一多层立体结构122的横截面面积也是纳米级，即形成了纳米级的半导体结构。该半导体结构具有较低的能耗、纳米级的尺寸以及更高的集成度。
第二碳纳米管108和导电膜114与二维的N型半导体层112在第二多层立体结构124处形成范德华异质结构。在应用时，第二碳纳米管108和导电膜114与N型半导体层112之间形成肖特基结，电流可以穿过该第二多层立体结构124。由于第二碳纳米管108为纳米材料，该第二多层立体结构124的横截面面积也是纳米级，即形成了纳米级的半导体结构。该半导体结构具有较低的能耗、纳米级的尺寸以及更高的集成度较高的空间分辨率以及更高的完整性。
所述第一电极116、第二电极118及第三电极120均由导电材料组成，该导电材料可选择为金属、ITO、ATO、导电银胶、导电聚合物以及导电碳纳米管等。该金属材料可以为铝、铜、钨、钼、金、钛、钯或任意组合的合金。在一些实施例中，所述第一电极116和第二电极118也可以均为一层导电薄膜，该导电薄膜的厚度为2微米～100微米。本实施例中，所述第一电极116、第二电极118为金属Au，金属Au的厚度为50纳米。本实施例中，所述第一电极116设置于第一碳纳米管106的一端并贴合于第一碳纳米管106的表面，即Au层设置于第一碳纳米管106表面；所述第二电极118与设置于第二碳纳米管108的一端并贴合于第二碳纳米管108的表面，即Au层设置于Ti层表面。所述第三电极120为一长条状导电层，其设置于导电膜114的一端，沿导电膜114的一个边设置于导电膜114的表面。所述第三电极120的材料可以与第一电极116或第二电极118相同。
本发明所提供的半导体器件100包括两个基于碳纳米管不对称范德华异质结构。当半导体器件100在应用时，范德华异质结构在相对的源极-漏极偏置处显示出不对称的输出特性。运输特性的多样性主要归因于碳纳米管费米能级易被调制和器件的不对称接触，同时碳纳米管电极适用于电子型或者空穴型导电。可调节器件功能以及侧向器件尺寸的限制使得这种包括碳纳米管的不对称范德华异质结构的半导体结构具有独特性，在未来的纳米电子学和纳米光电子学领域具有巨大的潜力。请参见图3，所述半导体器件100在用作CMOS器件时，栅极102为输出端，第三电极120为输出端，第一电极116和第二电极118接入电源，三条曲线分别对应第一电极116和第二电极118之间的电势差为0.1伏、0.2伏和0.4伏时，对应的输出曲线。从图3可以看出，所述CMOS器件具有良好的工作性能。
所述半导体器件100在应用时，第一碳纳米管106和导电膜114可以看作设置在P型半导体层110的两个相对表面上的电极，第二碳纳米管108和导电膜114看作N型半导体层112的两个相对表面上的电极。当在第一碳纳米管106、第二碳纳米管114和导电膜106上施加电压实现导通时，电流的流动路径为从第一多层立体结构122的横截面至第二多层立体结构124的横截面，所述半导体器件100的有效部分为第一多层立体结构122及第二多层立体结构124。因此，所述半导体器件100的体积只需要确保包括第一多层立体结构122和第二多层立体结构124即可，因此，半导体器件100可以具有较小的尺寸，所述半导体元件100可以为一纳米级的半导体元件。
另外，本领域技术人员还可在本发明精神内做其他变化，当然，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围之内。

Claims (10)

1.一种半导体器件，其包括:
一栅极，该栅极为一层状结构；
一绝缘层，所述绝缘层设置于栅极的表面；
两个基于碳纳米管的不对称范德华异质结构设置于所述绝缘层的表面，该两个基于碳纳米管的不对称范德华异质结构包括：
一第一碳纳米管及一第二碳纳米管，所述第一碳纳米管和第二碳纳米管间隔设置于绝缘层的表面；
一P型半导体层及一N型半导体层，所述P型半导体层覆盖第一碳纳米管，并设置于绝缘层的表面，所述N型半导体层覆盖第二碳纳米管，并设置于绝缘层的表面；
一导电膜，所述导电膜设置于P型半导体层和N型半导体层的表面，其中，P型半导体层位于导电膜和第一碳纳米管之间，N型半导体层位于导电膜和第二碳纳米管之间；
一第一电极，该第一电极与第一碳纳米管电连接；
一第二电极，该第二电极与第二碳纳米管电连接；以及
一第三电极，该第三电极与导电膜电连接。
2.如权利要求1所述的半导体器件，其特征在于，所述第一碳纳米管和第二碳纳米管为金属型碳纳米管。
3.如权利要求2所述的半导体器件，其特征在于，所述第一碳纳米管和第二碳纳米管为单壁碳纳米管。
4.如权利要求1所述的半导体器件，其特征在于，所述第一碳纳米管、P型半导体层及导电膜相互叠加形成一第一多层立体结构，该第一多层立体结构的横截面的面积为0.25nm2～1000nm2。
5.如权利要求4所述的半导体器件，其特征在于，所述第一多层立体结构的横截面的面积为1nm2～100nm2。
6.如权利要求1所述的半导体器件，其特征在于，所述第二碳纳米管、N型半导体层及导电膜相互叠加形成一第二多层立体结构，该第二多层立体结构的横截面的面积为0.25nm2～1000nm2。
7.如权利要求1所述的半导体器件，其特征在于，所述P型半导体层或N型半导体层的厚度为1nm～100nm。
8.如权利要求1所述的半导体器件，其特征在于，所述导电膜的沉积方法包括离子溅射、磁控溅射或其它镀膜方法。
9.如权利要求8所述的半导体器件，其特征在于，所述导电膜的厚度为5nm～100nm。
10.如权利要求1所述的半导体器件，其特征在于，所述导电膜跨过P型半导体层和N型半导体层，所述导电膜一部分位于P型半导体层远离绝缘层的表面；一部分位于N型半导体层远离绝缘层的表面；一部分位于P型半导体层和N型半导体层之间，设置于绝缘层的表面。
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