CN108923242B

CN108923242B - Optical soliton generation system based on black phosphorus saturable absorber

Info

Publication number: CN108923242B
Application number: CN201810888722.3A
Authority: CN
Inventors: 高博; 霍佳雨; 汝玉星; 吴戈
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2018-08-07
Filing date: 2018-08-07
Publication date: 2020-05-22
Anticipated expiration: 2038-08-07
Also published as: CN108923242A

Abstract

The invention discloses a light soliton generation system based on a black phosphorus saturable absorber, and belongs to the technical field of optoelectronic devices. The main structure of the device comprises a polarization controller (1), a1 xN optical switch (2), an optical fiber group (3), a1 xN optical coupler (4), a saturable absorber (5), a central wavelength tuning device (6) and the like. The optical soliton generating device can generate various optical solitons with different types, is convenient to use, and can output stable optical soliton center wavelength when environmental parameters change.

Description

Optical soliton generation system based on black phosphorus saturable absorber

Technical Field

The invention belongs to the technical field of optoelectronic devices, and particularly relates to a light soliton generation system based on a black phosphorus saturable absorber.

Background

An optical soliton is a special form of ultrashort optical pulse that remains unchanged in shape, amplitude, and velocity during propagation. The characteristics of the optical soliton determine that the optical soliton has wide application prospect in the communication field, and firstly, the optical soliton has large communication capacity: the transmission code rate can generally reach 20Gb/s, and can reach more than 100Gb/s at most, and then the error rate is low and the anti-jamming capability is strong: the optical solitons are kept unchanged in the transmission process and the adiabatic property of the optical solitons determines that the error rate of optical soliton transmission is greatly lower than that of conventional optical fiber communication, even error-free optical fiber communication with the error rate lower than 10-12 can be realized, and a relay station is not needed again: the optical signal can be transmitted in an extremely long distance without distortion by only carrying out gain compensation on the optical fiber loss, so that the complex processes of photoelectric conversion, reshaping amplification, error code detection, photoelectric conversion, retransmission and the like are omitted. However, it is known that the optical soliton center wavelength output by the optical soliton generation system is easily affected by external conditions such as ambient temperature, and in practical applications, the center wavelength is the most important parameter of the optical soliton, and the stability of the center wavelength directly determines the quality of the optical soliton.

The closest prior art to the present invention is an optical soliton pulse generator composed of an erbium-doped fiber laser (application number 2014102507203) applied in 2014, 7, of this subject group, and the patent realizes the purpose of generating different types of optical solitons by one device by controlling the length of a single-mode fiber through an optical switch. However, the patent generally has the disadvantage of unstable central wavelength as in other prior art for generating optical solitons. Therefore, the existing technology for generating optical solitons needs to be further improved.

Disclosure of Invention

In order to overcome the defect that the central wavelength of an optical soliton generated by the existing optical soliton generation system is easily influenced by environmental parameters to cause the central wavelength to be unstable, the invention provides the optical soliton generation system with the stable central wavelength.

The purpose of the invention is realized by the following technical scheme:

an optical soliton generation system based on a black phosphorus saturable absorber has the structure that the output end of an optical isolator 7 is connected with the common end of an optical wavelength division multiplexer 9 through an erbium-doped optical fiber 8, the 980nm end of the optical wavelength division multiplexer 9 is connected with the output end of a pump light source 10, the 1550nm end of the optical wavelength division multiplexer 9 is connected with the input end of a first optical coupler 11, 90% of the output end of the first optical coupler 11 is connected with the input end of a polarization controller 1, the output end of the polarization controller 1 is connected with the common input end of a1 xN optical switch 2, N output ends of the 1 xN optical switch 2 are respectively connected with N input ends of the 1 xN optical coupler 4 through N different single-mode optical fibers in an optical fiber group 3, the optical fiber group 3 is composed of N single-mode optical fibers with different lengths, N is an integer of 2-8, and the public output end of the 1 XN optical coupler 4 is connected with one end of the black phosphorus saturable absorber 5;

the device is characterized in that the other end of the black phosphorus saturable absorber 5 is connected with the input end of a central wavelength tuning device 6, and the output end of the central wavelength tuning device 6 is connected with the input end of an optical isolator 7; the 10% output end of the first optical coupler 11 is connected with the input end of the second optical coupler 12, the 10% output end of the second optical coupler 12 is used as the final output of the invention, the 90% output end of the second optical coupler 12 is connected with one input end of the third optical coupler 13, one output end of the third optical coupler 13 is connected with the second Faraday rotator mirror 16, the other output end of the third optical coupler 13 is connected with one end of the optical fiber wound on the piezoelectric ceramic 14, the other end of the optical fiber on the piezoelectric ceramic 14 is connected with the input end of the first Faraday rotator mirror 15, the input end of the photoelectric conversion circuit 17 is connected with the other input end of the third optical coupler 13, the output end of the photoelectric conversion circuit 17 is connected with the input end of the function conversion circuit 18, the output end of the function conversion circuit 18 is connected with the signal input end of the adaptive amplitude normalization circuit 19, the signal output end of the adaptive amplitude normalization circuit 19 is connected with one input end of the phase comparison circuit 20, the output end of the reference voltage circuit 25 is connected with the reference voltage input end of the adaptive amplitude normalization circuit 19, the output end of the adaptive amplitude normalization circuit 19 is connected with one input end of the phase comparison circuit 20, the output end of the phase comparison circuit 20 is connected with the single chip microcomputer 21, the single chip microcomputer 21 is connected with the input control end of the controllable frequency source 23, the sine signal output end of the controllable frequency source 23 is connected with the other input end of the phase comparison circuit 20 and is also connected with the input end of the piezoelectric ceramic driving circuit 24, the output end of the piezoelectric ceramic driving circuit 24 is connected with the control end of the piezoelectric ceramic 14, the single chip microcomputer 21 is connected with the temperature setting end of the temperature control circuit 22, the current output end of the temperature control circuit 22 is connected with the semiconductor thermoelectric refrigerator 64 in the center wavelength tuning device 6, the thermistor input of the temperature control circuit 22 is connected to the thermistor 63 of the center wavelength tuning device 6;

the center wavelength tuning device 6 has a structure in which a semiconductor thermoelectric cooler 64 is interposed between the lower surface of an aluminum block 61 and the upper surface of a heat sink 65; the thermistor 63 and the Bragg grating 62 are attached to the upper surface of the aluminum block 61; the thermistor 63 is connected with the thermistor input end of the temperature control circuit 22; the semiconductor thermoelectric cooler 64 is connected to the current output of the temperature control circuit 22; one end of the bragg grating 62 is connected with the second port of the optical circulator 66, the first port of the optical circulator 66 is used as the input end of the central wavelength tuning device 6 and is connected with the black phosphorus saturable absorber 5, and the third port of the optical circulator 66 is used as the output end of the central wavelength tuning device 6 and is connected with the input end of the optical isolator 7;

the structure of the function transformation circuit 18 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 18, is marked as a port ACOS _ in, and is connected with the output end of the photoelectric conversion circuit 17; the other end of the resistor R2 is grounded;

pins

2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded,

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 18, is recorded as a port ACOS _ out, and is connected with the signal input end of the adaptive amplitude normalization circuit 19; the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit 19 is structurally characterized in that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as a signal input end of the adaptive amplitude normalization circuit 19, is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit 18; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end 7 of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage input end of the adaptive amplitude normalization circuit 19 and is connected with a reference voltage output end of the reference voltage circuit 25; pin 10 of the chip U2, which is used as the signal output terminal of the adaptive amplitude normalization circuit 19 and is marked as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 20; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit 20 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 20, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 19; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparator circuit 20, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 23; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D trigger U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 20, is recorded as a port PHASE _ out and is connected with the singlechip 21;

the structure of the reference voltage circuit 25 is that one end of a resistor R27 is connected with a +5V power supply, the other end of the resistor R27 is connected with the non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode of the voltage stabilizing diode D3 is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with the output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the + 2.5V; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply end is grounded, the output end is used as the output end of the reference voltage circuit 25, is marked as a port Vref and is connected with the reference voltage input end of the adaptive amplitude normalization circuit 19;

the structure of the controllable frequency source 23 is that one end of a slide rheostat W5 is connected with a +12V power supply, and the other end and the slide end are connected with the base electrode of a triode Q2; one end of the capacitor C16 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R28 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R29 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q2; one end of the resistor R30 is connected with the emitting electrode of the triode Q2, and the other end is grounded; one end of the capacitor C17 is connected with the emitter of the triode Q2, and the other end is connected with the collector of the triode Q2; one end of the capacitor C18 is connected with the emitter of the triode Q2, and the other end is grounded; the collector of the triode Q2, which is used as the output terminal of the controllable frequency source 23 and is marked as port SineM _ out, is connected with the port PHASE _ in2 of the PHASE comparison circuit 20 and the input terminal of the piezoelectric ceramic drive circuit 24; one end of a capacitor C19 is connected with the collector of the triode Q2, the other end of the capacitor C19 is connected with one end of a capacitor C20 and one end of an inductor L1, the other end of the capacitor C20 is connected with the negative electrode of a variable-capacitance diode D4, the positive electrode of the variable-capacitance diode D4 is grounded, and the other end of the inductor L1 is grounded; one end of the capacitor C21 is grounded, and the other end is used as the input end of the controllable frequency source 23 and is marked as a port SineM _ in; one end of the resistor R31 is connected to the port SineM _ in, and the other end is connected to the cathode of the varactor.

The pump light source 10 is preferably a 980nm laser light source.

The first optical coupler 11 and the second optical coupler 12 preferably have a splitting ratio of 10: a 90 1 x 2 optical coupler.

The third optical coupler 13 preferably has a splitting ratio of 50: a 50 x 2 optical coupler.

The temperature control circuit 22 is prior art, and the specific structure can be found in the invention patent "high stability thermostatic controller" (application number: 2007100559129) applied in 2007, 7, 27 of this subject group.

The piezoceramic driving circuit 24 is the prior art, and the specific structure can be found in the invention patent of "piezoceramic driving circuit for optical fiber stress adjustment" (application number: 2007100558658) applied in 2007, 7, month and 11 of the subject group.

The photoelectric conversion circuit 17 is a conventional circuit that can convert an optical signal into an electrical signal.

Has the advantages that:

1. the invention introduces the center wavelength tuning device which can be actively adjusted, and can compensate the shift of the center wavelength caused by the environment when the environmental condition changes, thereby effectively improving the stability of the center wavelength of the optical soliton output by the system.

2. The invention adopts the self-adaptive amplitude normalization circuit to normalize the amplitude of the output signal of the function conversion circuit, provides a high-quality signal for the subsequent phase comparison circuit and improves the accuracy of the phase comparison circuit.

Description of the drawings:

fig. 1 is a block diagram of the overall architecture of the present invention.

Fig. 2 is a block diagram of a center wavelength tuning device used in the present invention.

Fig. 3 is a schematic circuit diagram of a functional conversion circuit used in the present invention.

Fig. 4 is a schematic circuit diagram of an adaptive amplitude normalization circuit used in the present invention.

Fig. 5 is a schematic circuit diagram of a phase comparison circuit used in the present invention.

Fig. 6 is a reference voltage circuit diagram of the present invention.

Fig. 7 is a schematic circuit diagram of a controllable frequency source for use with the present invention.

Detailed Description

The operation principle of the present invention is further explained with reference to the drawings, and it should be understood that the component parameters marked in the drawings are the preferred parameters used in the following embodiments, and do not limit the protection scope.

EXAMPLE 1 Overall Structure of the invention

As shown in FIG. 1, the overall structure of the present invention has an input terminal of a polarization controller 1 (HFPC-11-1064-S-9/125-3U all-fiber polarization controller manufactured by OZ-OPTICS Inc.) connected to 90% of an output terminal of a first optical coupler 11 (manufactured by OZ-OPTICS Inc., model number FUSED-12-1064-7/125-90/10-3U-3mm, splitting ratio 90:10), an output terminal of the polarization controller 1 connected to a common input terminal of a1 XN optical switch 2 (all-fiber optical switch manufactured by OZ-OPTICS Inc., model number MFOS-12-9/125-S-1060-3U), and N output terminals of the 1 XN optical switch 2 connected to a1 XN optical coupler 4 (manufactured by OZ-OPTICS Inc.) via N different single-mode fibers (ordinary single-mode fibers 1500 of FIBER SM) in an optical fiber group 3, respectively A fiber coupler with FUSED-12-1060-7/125-50/50-3U-3 mm) with N input ends connected, the fiber group 3 is composed of N common single-mode fibers with different lengths, N is an integer of 2-8, the common output end of the 1 XN optical coupler 4 is connected with one end of a black phosphorus saturable absorber 5 (a saturable absorber made of black phosphorus material), the other end of the black phosphorus saturable absorber 5 is connected with the input end of a central wavelength tuning device 6, the output end of the central wavelength tuning device 6 is connected with the input end of an optical isolator 7 (IO-H-1064B single-mode optical isolator of THORLABS company), the output end of the optical isolator 7 is connected with the common end of a light wavelength division multiplexer 9(COMCORE 980/1550nm single-mode fiber wavelength division multiplexer) through an erbium-doped fiber 8 (SM-ESF-7/125 erbium-doped fiber produced by Nufern company of America), the 980nm end of the optical wavelength division multiplexer 9 is connected with the output end of a pumping light source 10 (LC 962U type pumping source of OCLARO company, the center wavelength is 980nm, and the maximum single-mode output optical power is 750mW), and the 1550nm end of the optical wavelength division multiplexer 9 is connected with the input end of the first optical coupler 11; the 10% output of the first optical coupler 11 is connected to the input of the second optical coupler 12, the 10% output of the second optical coupler 12 (made by OZ-OPTICS, Inc., model number FUSED-12-1064-7/125-90/10-3U-3mm, with a splitting ratio of 90:10) is used as the final output of the present invention, the 90% output of the second optical coupler 12 is connected to one input of the third optical coupler 13, one output of the third optical coupler 13(1 × 2 standard single-mode optical coupler, with a splitting ratio of 50: 50) is connected to the second Faraday rotator 16 (MFI-1310 made by ThORLABS), the other output of the third optical coupler 13 is connected to one end of an optical fiber wound on a piezoelectric ceramic 14 (cylindrical piezoelectric ceramic, outer diameter of 50mm, inner diameter of 40mm, and height of 50mm), and the other end of the optical fiber on the piezoelectric ceramic 14 is connected to a first Faraday rotator 15 (MFI-1310 made by ThORLABS) 1310) An input terminal of the photoelectric conversion circuit 17 is connected to another input terminal of the third optical coupler 13, an output terminal of the photoelectric conversion circuit 17 is connected to an input terminal of the function conversion circuit 18, an output terminal of the function conversion circuit 18 is connected to a signal input terminal of the adaptive amplitude normalization circuit 19, a signal output terminal of the adaptive amplitude normalization circuit 19 is connected to one input terminal of the phase comparison circuit 20, an output terminal of the reference voltage circuit 25 is connected to a reference voltage input terminal of the adaptive amplitude normalization circuit 19, an output terminal of the adaptive amplitude normalization circuit 19 is connected to one input terminal of the phase comparison circuit 20, an output terminal of the phase comparison circuit 20 is connected to a single chip microcomputer 21(STC89C51), the single chip microcomputer 21 is connected to an input control terminal of the controllable frequency source 23, a sine signal output terminal of the controllable frequency source 23 is connected to another input terminal of the phase comparison circuit 20, and the input end of a piezoelectric ceramic driving circuit 24 (a device manufactured by the subject group, and the specific structure is shown in patent ZL200710055865.8), the output end of the piezoelectric ceramic driving circuit 24 is connected with the control end of the piezoelectric ceramic 14, the single chip microcomputer 21 is connected with the temperature setting end of the temperature control circuit 22, the current output end of the temperature control circuit 22 is connected with the semiconductor thermoelectric cooler 64 in the central wavelength tuning device 6, and the thermistor input end of the temperature control circuit 22 is connected with the thermistor 63 of the central wavelength tuning device 6.

EXAMPLE 2 center wavelength tuning device

As shown in fig. 2, the center wavelength tuning device 6 has a structure in which a semiconductor thermoelectric cooler 64(TEC12705) is interposed between the lower surface of an aluminum block 61 and the upper surface of a heat sink 65; a thermistor 63(10k omega @25 degrees) and a Bragg grating 62(JH-FGA-A101) are attached to the upper surface of the aluminum block 61; the thermistor 63 is connected with the thermistor input end of the temperature control circuit 22; the semiconductor thermoelectric cooler 64 is connected to the current output of the temperature control circuit 22; one end of the bragg grating 62 is connected to a second port of an optical circulator 66 (PIOC 3-15 optical circulator manufactured by THORLABS), a first port of the optical circulator 66 is used as an input end of the central wavelength tuning device 6 and is connected to the black phosphorus saturable absorber 5, and a third port of the optical circulator 66 is used as an output end of the central wavelength tuning device 6 and is connected to an input end of the optical isolator 7. When the system detects that the central wavelength of the output optical soliton changes, the central wavelength tuning device 6 can be used for carrying out reverse adjustment, and further the central wavelength of the output optical soliton is stabilized.

Embodiment 3 function conversion circuit

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 18, is recorded as a port ACOS _ out, and is connected with the signal input end of the adaptive amplitude normalization circuit 19; the type of the trigonometric function converter U1 is AD 639. The circuit has an inverse cosine transform function, and performs inverse cosine processing on a signal output from the photoelectric conversion circuit 17.

Embodiment 4 adaptive amplitude normalization circuit

Because the signal amplitudes output by the function conversion circuit 18 under different conditions are also different, and the time is large and small, so that the phase comparison circuit 20 is convenient to process, and the phase comparison precision is improved, the invention also designs the adaptive amplitude normalization circuit 19, and the specific structure is as shown in fig. 4, wherein one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as a signal input end of the adaptive amplitude normalization circuit 19, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of the function conversion circuit 18; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end 7 of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage input end of the adaptive amplitude normalization circuit 19 and is connected with a reference voltage output end of the reference voltage circuit 25; pin 10 of the chip U2, which is used as the signal output terminal of the adaptive amplitude normalization circuit 19 and is marked as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 20; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1(2N4117), the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip with model number AD 8367. The circuit makes the amplitude of the signal output from the function conversion circuit 18 uniform to a proper magnitude (frequency, phase unchanged) so as to be suitable for the phase comparison circuit 20 to process, thereby improving the accuracy of phase comparison.

Example 5 phase comparison Circuit

The structure of the PHASE comparison circuit 20 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 20, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 19; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparator circuit 20, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 23; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D trigger U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 20, is recorded as a port PHASE _ out and is connected with the singlechip 21; the circuit compares the phase of the standard sine wave output by the controllable frequency source 23 with the phase of the sine wave output by the adaptive amplitude normalization circuit 19, and the compared result is sent to the single chip microcomputer.

EXAMPLE 6 reference Voltage Circuit

The structure of the reference voltage circuit 25 is that one end of a resistor R27 is connected with a +5V power supply, the other end is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the +2.5V power supply in the self-adaptive amplitude normalization circuit 19 is provided by the output end; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply end is grounded, the output end is used as the output end of the reference voltage circuit 25, is marked as a port Vref and is connected with the reference voltage input end of the adaptive amplitude normalization circuit 19; this circuit provides the adaptive amplitude normalization circuit 19 with a reference voltage and a +2.5V voltage.

EXAMPLE 7 controllable frequency Source

The structure of the controllable frequency source 23 is that one end of a slide rheostat W5 is connected with a +12V power supply, and the other end and the slide end are connected with the base electrode of a triode Q2; one end of the capacitor C16 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R28 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R29 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q2; one end of the resistor R30 is connected with the emitting electrode of the triode Q2, and the other end is grounded; one end of the capacitor C17 is connected with the emitter of the triode Q2, and the other end is connected with the collector of the triode Q2; one end of the capacitor C18 is connected with the emitter of the triode Q2, and the other end is grounded; the collector of the triode Q2, which is used as the output terminal of the controllable frequency source 23 and is marked as port SineM _ out, is connected with the port PHASE _ in2 of the PHASE comparison circuit 20 and the input terminal of the piezoelectric ceramic drive circuit 24; one end of a capacitor C19 is connected with the collector of the triode Q2, the other end of the capacitor C19 is connected with one end of a capacitor C20 and one end of an inductor L1, the other end of the capacitor C20 is connected with the negative electrode of a variable-capacitance diode D4, the positive electrode of the variable-capacitance diode D4 is grounded, and the other end of the inductor L1 is grounded; one end of the capacitor C21 is grounded, and the other end is used as the input end of the controllable frequency source 23 and is marked as a port SineM _ in; one end of the resistor R31 is connected to the port SineM _ in, and the other end is connected to the cathode of the varactor. The module outputs a standard sine wave with adjustable frequency to provide the required modulation signal for the piezoelectric ceramic driving circuit 24 and also provides a reference phase reference for the phase comparison circuit 20.

Example 8 working principle of the invention

The working principle of the present invention will be described with reference to the above embodiments and the accompanying drawings.

In the overall block diagram shown in fig. 1, a polarization controller 1, a1 xn optical switch 2, an optical fiber group 3 to a first optical coupler 11 form a basic resonant cavity for generating optical solitons, when optical fibers with different lengths are selected from the optical fiber group 3 through the 1 xn optical switch 2 and the 1 xn optical coupler 4, the resonant cavity generates optical solitons of different types, a part of signals of the generated optical solitons enters a michelson interferometer formed by a third optical coupler 13, a piezoelectric ceramic 14, a piezoelectric ceramic driving circuit 24, a first faraday rotator mirror 15 and a second faraday rotator mirror 16 through a second optical coupler 12 for interference, and a controllable frequency source 23 provides a control signal sin (ω t) for the michelson interferometer, which is influenced by the central wavelength of the optical solitons in the interferometer, is converted into electrical signals through an optoelectronic conversion circuit 17 and is converted into electrical signals through an inverse cosine conversion circuit 18 to obtain a sin (ω t + Δ θ), the amplitude of the signal is adjusted to a fixed value after passing through the adaptive amplitude normalization circuit 19, the phase of the signal is changed when the signal is compared with a sine signal sin (ω t) generated by the controllable frequency source 23, the phase difference between the signal and the sine signal sin (ω t) is detected by the phase comparison circuit 20 and is sent to the single chip microcomputer 21, the phase difference is determined by the central wavelength of the optical soliton generated by the basic resonant cavity, when the single chip microcomputer 21 detects that the central wavelength is changed from the preset central wavelength, the temperature of the Bragg grating in the central wavelength tuning device 6 is adjusted by the temperature control circuit 22 so as to reversely influence the central wavelength of the optical soliton in the basic resonant cavity, the purpose of stabilizing the central wavelength is further achieved, and the final optical soliton signal is output from the 10% output end of the second optical coupler 12.

Claims

1. An optical soliton generation system based on a black phosphorus saturable absorber is structurally characterized in that an output end of an optical isolator (7) is connected with a common end of an optical wavelength division multiplexer (9) through an erbium-doped optical fiber (8), a 980nm end of the optical wavelength division multiplexer (9) is connected with an output end of a pump light source (10), a 1550nm end of the optical wavelength division multiplexer (9) is connected with an input end of a first optical coupler (11), 90% of an output end of the first optical coupler (11) is connected with an input end of a polarization controller (1), an output end of the polarization controller (1) is connected with a common input end of a1 xN optical switch (2), N output ends of the 1 xN optical switch (2) are respectively connected with N input ends of a1 xN optical coupler (4) through N different single-mode optical fibers in an optical fiber group (3), the optical fiber group (3) is composed of N single mode optical fibers with different lengths, n is an integer of 2-8, and the common output end of the 1 XN optical coupler (4) is connected with one end of the black phosphorus saturable absorber (5);

the structure is characterized in that the other end of the black phosphorus saturable absorber (5) is connected with the input end of a central wavelength tuning device (6), the output end of the central wavelength tuning device (6) is connected with the input end of an optical isolator (7), 10% of the output end of a first optical coupler (11) is connected with the input end of a second optical coupler (12), 10% of the output end of the second optical coupler (12) is used as final output, 90% of the output end of the second optical coupler (12) is connected with one input end of a third optical coupler (13), one output end of the third optical coupler (13) is connected with a second Faraday rotator mirror (16), the other output end of the third optical coupler (13) is connected with one end of an optical fiber wound on a piezoelectric ceramic (14), and the other end of the optical fiber on the piezoelectric ceramic (14) is connected with the input end of a first Faraday rotator mirror (15), the input end of the photoelectric conversion circuit (17) is connected with the other input end of the third optical coupler (13), the output end of the photoelectric conversion circuit (17) is connected with the input end of the function conversion circuit (18), the output end of the function conversion circuit (18) is connected with the signal input end of the adaptive amplitude normalization circuit (19), the signal output end of the adaptive amplitude normalization circuit (19) is connected with one input end of the phase comparison circuit (20), the output end of the reference voltage circuit (25) is connected with the reference voltage input end of the adaptive amplitude normalization circuit (19), the output end of the adaptive amplitude normalization circuit (19) is connected with one input end of the phase comparison circuit (20), the output end of the phase comparison circuit (20) is connected with the single chip microcomputer (21), the single chip microcomputer (21) is connected with the input control end of the controllable frequency source (23), the sine signal output end of the controllable frequency source (23) is connected with the other input end of the phase comparison circuit (20) The temperature control circuit is also connected with the input end of a piezoelectric ceramic driving circuit (24), the output end of the piezoelectric ceramic driving circuit (24) is connected with the control end of the piezoelectric ceramic (14), the singlechip (21) is connected with the temperature setting end of the temperature control circuit (22), the current output end of the temperature control circuit (22) is connected with a semiconductor thermoelectric cooler (64) in the central wavelength tuning device (6), and the thermistor input end of the temperature control circuit (22) is connected with a thermistor (63) of the central wavelength tuning device (6);

the structure of the central wavelength tuning device (6) is that a semiconductor thermoelectric cooler (64) is clamped between the lower surface of an aluminum block (61) and the upper surface of a radiating fin (65); the thermistor (63) and the Bragg grating (62) are attached to the upper surface of the aluminum block (61); the thermistor (63) is connected with the thermistor input end of the temperature control circuit (22); the semiconductor thermoelectric cooler (64) is connected with the current output end of the temperature control circuit (22); one end of the Bragg grating (62) is connected with a second port of the optical circulator (66), a first port of the optical circulator (66) is used as the input end of the central wavelength tuning device (6) and is connected with the saturable absorber (5), and a third port of the optical circulator (66) is used as the output end of the central wavelength tuning device (6) and is connected with the input end of the optical isolator (7);

the structure of the function conversion circuit (18) is that one end of a capacitor C3 is connected with a pin 12 of a trigonometric function converter U1 and one end of a resistor R2, and the other end of a capacitor C3 is used as an input end of the function conversion circuit (18), is recorded as a port ACOS _ in and is connected with the output end of the photoelectric conversion circuit (17); the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of a sliding rheostat W1, one end of a sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a pin 14 of a trigonometric function converter U1, and the sliding end of a sliding rheostat W1 is used as the output end of a function transformation circuit (18), is recorded as a port ACOS _ out and is connected with the signal input end of an adaptive amplitude normalization circuit (19); the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit (19) is structurally characterized in that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as a signal input end of the adaptive amplitude normalization circuit (19), is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit (18); pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end 7 of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage input end of the adaptive amplitude normalization circuit (19) and is connected with a reference voltage output end of the reference voltage circuit (25); a pin 10 of the chip U2 is used as a signal output end of the adaptive amplitude normalization circuit (19), is recorded as a port ADAPT _ out, and is connected with one input end of the phase comparison circuit (20); a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit (20) is that one end of a capacitor C12 is connected with the non-inverting input end of an operational amplifier U9 and one end of a resistor R23, the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit (20), is recorded as a port PHASE _ in1 and is connected with a port ADAPT _ out of the self-adaptive amplitude normalization circuit (19); the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected with the non-inverting input end of the operational amplifier U11 and one end of the resistor R25, the other end of the capacitor C14 is used as the other input end of the PHASE comparison circuit (20), is recorded as a port PHASE _ in2 and is connected with a port Sinem _ out of the controllable frequency source (23); the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D trigger U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit (20), is recorded as a port PHASE _ out and is connected with the singlechip (21);

the structure of the reference voltage circuit (25) is that one end of a resistor R27 is connected with a +5V power supply, the other end of the resistor R27 is connected with the non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode of the voltage stabilizing diode D3 is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with the output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end of the operational amplifier U13 is the +2.5V power supply, and the +2.5V power; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is used as the output end of the reference voltage circuit (25), is marked as a port Vref and is connected with the reference voltage input end of the self-adaptive amplitude normalization circuit (19);

the structure of the controllable frequency source (23) is that one end of a slide rheostat W5 is connected with a +12V power supply, and the other end and the slide end are connected with the base electrode of a triode Q2; one end of the capacitor C16 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R28 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R29 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q2; one end of the resistor R30 is connected with the emitting electrode of the triode Q2, and the other end is grounded; one end of the capacitor C17 is connected with the emitter of the triode Q2, and the other end is connected with the collector of the triode Q2; one end of the capacitor C18 is connected with the emitter of the triode Q2, and the other end is grounded; the collector of the triode Q2 is used as the output end of the controllable frequency source (23) and is marked as a port SineM _ out, and is connected with the port PHASE _ in2 of the PHASE comparison circuit (20) and the input end of the piezoelectric ceramic driving circuit (24); one end of a capacitor C19 is connected with the collector of the triode Q2, the other end of the capacitor C19 is connected with one end of a capacitor C20 and one end of an inductor L1, the other end of the capacitor C20 is connected with the negative electrode of a variable-capacitance diode D4, the positive electrode of the variable-capacitance diode D4 is grounded, and the other end of the inductor L1 is grounded; one end of the capacitor C21 is grounded, and the other end of the capacitor C21 is used as the input end of the controllable frequency source (23) and is recorded as a port SineM _ in; one end of the resistor R31 is connected to the port SineM _ in, and the other end is connected to the cathode of the varactor.

2. An optical soliton generation system based on a black phosphorus saturable absorber as claimed in claim 1, wherein the pump light source (10) is a 980nm laser source.

3. A black phosphorus saturable absorber-based optical soliton generation system as claimed in claim 1, wherein the first optical coupler (11) and the second optical coupler (12) both have a splitting ratio of 10: a 90 1 x 2 optical coupler; the third optical coupler (13) has a splitting ratio of 50: a 50 x 2 optical coupler.