CN109039466B - High-stability optical soliton generator based on erbium-doped fiber laser - Google Patents
High-stability optical soliton generator based on erbium-doped fiber laser Download PDFInfo
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- CN109039466B CN109039466B CN201810889094.0A CN201810889094A CN109039466B CN 109039466 B CN109039466 B CN 109039466B CN 201810889094 A CN201810889094 A CN 201810889094A CN 109039466 B CN109039466 B CN 109039466B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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- H04B10/508—Pulse generation, e.g. generation of solitons
Abstract
The invention discloses a high-stability optical soliton generator based on an erbium-doped fiber laser, and belongs to the technical field of optoelectronic equipment. The main structure of the device comprises a polarization controller (1), a1 xN optical switch (2), an optical fiber group (3), a1 xN optical coupler (4), a saturable absorber (5), a central wavelength tuning device (6) and the like. The optical soliton generating device can generate various optical solitons with different types, is convenient to use, and can output stable optical soliton center wavelength when environmental parameters change.
Description
Technical Field
The invention belongs to the technical field of optoelectronic devices, and particularly relates to a high-stability optical soliton generator based on an erbium-doped fiber laser.
Background
An optical soliton is a special form of ultrashort optical pulse that remains unchanged in shape, amplitude, and velocity during propagation. The characteristics of the optical soliton determine that the optical soliton has wide application prospect in the communication field, and firstly, the optical soliton has large communication capacity: the transmission code rate can generally reach 20Gb/s, and can reach more than 100Gb/s at most, and then the error rate is low and the anti-jamming capability is strong: the optical solitons are kept unchanged in the transmission process and the adiabatic property of the optical solitons determines that the error rate of optical soliton transmission is greatly lower than that of conventional optical fiber communication, even error-free optical fiber communication with the error rate lower than 10-12 can be realized, and a relay station is not needed again: the optical signal can be transmitted in an extremely long distance without distortion by only carrying out gain compensation on the optical fiber loss, so that the complex processes of photoelectric conversion, reshaping amplification, error code detection, photoelectric conversion, retransmission and the like are omitted. . However, it is known that the optical soliton center wavelength output by the optical soliton generation system is easily affected by external conditions such as ambient temperature, and in practical applications, the center wavelength is the most important parameter of the optical soliton, and the stability of the center wavelength directly determines the quality of the optical soliton.
The closest prior art to the present invention is an optical soliton pulse generator composed of an erbium-doped fiber laser (application number 2014102507203) applied in 2014, 7, of this subject group, and the patent realizes the purpose of generating different types of optical solitons by one device by controlling the length of a single-mode fiber through an optical switch. However, the patent generally has the disadvantage of unstable central wavelength as in other prior art for generating optical solitons. Therefore, the existing technology for generating optical solitons needs to be further improved.
Disclosure of Invention
In order to overcome the defect that the central wavelength of an optical soliton generated by the existing optical soliton generation system is easily influenced by environmental parameters to cause the central wavelength to be unstable, the invention provides the optical soliton generation system with the stable central wavelength.
The purpose of the invention is realized by the following technical scheme:
a high-stability optical soliton generator based on an erbium-doped fiber laser structurally comprises an optical isolator 7, a pump light source 10, a pump light source 9 and a first optical coupler 11, wherein the output end of the optical isolator is connected with the common end of the optical wavelength division multiplexer 9 through an erbium-doped fiber 8, the 980nm end of the optical wavelength division multiplexer 9 is connected with the output end of the pump light source 10, and the 1550nm end of the optical wavelength division multiplexer 9 is connected with the input end of the first optical coupler 11; 90% of the output end of the first optical coupler 11 is connected with the input end of the polarization controller 1, the output end of the polarization controller 1 is connected with the common input end of the 1 xN optical switch 2, N output ends of the 1 xN optical switch 2 are respectively connected with N input ends of the 1 xN optical coupler 4 through N different single-mode optical fibers in an optical fiber group 3, the optical fiber group 3 is composed of N single-mode optical fibers with different lengths, N is an integer of 2-8, and the common output end of the 1 xN optical coupler 4 is connected with one end of the saturable absorber 5;
the structure is characterized in that the other end of the saturable absorber 5 is connected with the input end of a center wavelength tuning device 6, the output end of the center wavelength tuning device 6 is connected with the input end of an optical isolator 7, 10% of the output end of a first optical coupler 11 is connected with the input end of a second optical coupler 12, 10% of the output end of the second optical coupler 12 is used as the final output of the optical fiber coupler, 90% of the output end of the second optical coupler 12 is connected with the input end of a third optical coupler 13, one output end of the third optical coupler 13 is connected with one input end of a fourth optical coupler 15, the other output end of the third optical coupler 13 is connected with one end of an optical fiber wound on a piezoelectric ceramic 14, the other end of the optical fiber wound on the piezoelectric ceramic 14 is connected with the other input end of the fourth optical coupler 15, one output end of the fourth optical coupler 15 is connected with the input end of a first, the other output end of the fourth optical coupler 15 is connected with the input end of the second optical detector 17, the output end of the first optical detector 16 is connected with one input end of the differential amplifying circuit 18, the output end of the second optical detector 17 is connected with the other input end of the differential amplifying circuit 18, the output end of the differential amplifying circuit 18 is connected with the input end of the function converting circuit 19, the output end of the function converting circuit 19 is connected with the signal input end of the adaptive amplitude normalizing circuit 20, the signal output end of the adaptive amplitude normalizing circuit 20 is connected with one input end of the phase comparing circuit 21, the output end of the phase comparing circuit 21 is connected with the single chip microcomputer 22, the single chip microcomputer 22 is connected with the input control end of the controllable frequency source 24, the sine signal output end of the controllable frequency source 24 is connected with the other input end of the phase comparing circuit 21 and is also connected with the input end of the piezoelectric ceramic driving circuit, the output end of the piezoelectric ceramic driving circuit 25 is connected with the control end of the piezoelectric ceramic 14, the singlechip 22 is connected with the temperature setting end of the temperature control circuit 23, the current output end of the temperature control circuit 23 is connected with a semiconductor thermoelectric cooler 64 in the central wavelength tuning device 6, and the thermistor input end of the temperature control circuit 23 is connected with a thermistor 63 of the central wavelength tuning device 6;
the center wavelength tuning device 6 has a structure in which a semiconductor thermoelectric cooler 64 is interposed between the lower surface of an aluminum block 61 and the upper surface of a heat sink 65; the thermistor 63 and the Bragg grating 62 are attached to the upper surface of the aluminum block 61; the thermistor 63 is connected with the thermistor input end of the temperature control circuit 23; the semiconductor thermoelectric cooler 64 is connected with the current output end of the temperature control circuit 23; one end of the bragg grating 62 is connected with a second port of the optical circulator 66, a first port of the optical circulator 66 is used as an input end of the central wavelength tuning device 6 and is connected with the saturable absorber 5, and a third port of the optical circulator 66 is used as an output end of the central wavelength tuning device 6 and is connected with an input end of the optical isolator 7;
the structure of the function transformation circuit 19 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 19, is recorded as a port ACOS _ in, and is connected with the output end of the differential amplification circuit 18; the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 19, is recorded as a port ACOS _ out, and is connected with the input end of the adaptive amplitude normalization circuit 20; the model of the trigonometric function converter U1 is AD 639;
the adaptive amplitude normalization circuit 20 has a structure that one end of a capacitor C9 is connected with one end of a resistor R3 and a pin 3 of a chip U2, the other end of the resistor R3 is grounded, and the other end of the capacitor C9 is used as an input end of the adaptive amplitude normalization circuit 20, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of a function conversion circuit 19; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R12 and a resistor R11, the other end of the resistor R12 is grounded, the other end of the resistor R11 is connected with the output end of the operational amplifier U4 and one end of a capacitor C8, the positive power supply end of the operational amplifier U4 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C8 is connected with one end of a resistor R10, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the sliding end of the sliding rheostat W3, one end of the sliding rheostat W3 is connected with a +5V power supply, and the other end of the sliding rheostat W3 is grounded; one end of a capacitor C7 is connected with one end of a resistor R9 and the non-inverting input end of the operational amplifier U4, the other end of the capacitor C7 is grounded, the other end of the resistor R9 is connected with one end of a resistor R7 and the output end of the operational amplifier U3A, and the other end of the resistor R7 is connected with the inverting input end of the operational amplifier U3A; one end of the resistor R8 is connected with the non-inverting input end of the operational amplifier U3A, and the other end is grounded; the positive power supply end of the operational amplifier U3A is connected with a +5V power supply, and the negative power supply end is grounded; pin 10 of the chip U2 is used as the output terminal of the adaptive amplitude normalization circuit 20, which is denoted as port ADAPT _ out, and is connected to one input terminal of the phase comparison circuit 21; a pin 10 of the chip U2 is connected with the anode of a diode D1, the cathode of a diode D1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with one end of a resistor R5 and the inverted input end of an operational amplifier U3A, the other end of the resistor R5 is connected with the anode of the diode D2, and the cathode of a diode D2 is connected with the sliding end of a sliding rheostat W2; one end of the slide rheostat W2 is connected with the cathode of the diode D3 and is grounded, the other end of the slide rheostat W2 is connected with one end of the resistor R6 and the anode of the diode D3, and the other end of the resistor R6 is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;
the structure of the PHASE comparison circuit 21 is that one end of a capacitor C10 is connected with the non-inverting input end of the operational amplifier U5 and one end of a resistor R13, and the other end of the capacitor C10 is used as one input end of the PHASE comparison circuit 21, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 20; the other end of the resistor R13 is grounded; the positive power supply end of the operational amplifier U5 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6A; the D port of the D flip-flop U6A is grounded; one end of the capacitor C11 is grounded, and the other end of the capacitor C11 is connected with the PR end of the D flip-flop U6A; one end of the resistor R14 is connected with the PR end of the D flip-flop U6A, and the other end is connected with the Q end of the D flip-flop U6A; the CLR end of the D flip-flop U6A is connected with a +5V power supply, and the Q end of the D flip-flop U6A is not connected with the PR end of the D flip-flop U8A; one end of the capacitor C12 is connected to the non-inverting input terminal of the operational amplifier U7 and one end of the resistor R15, and the other end of the capacitor C12 is used as the other input terminal of the PHASE comparator circuit 21, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 24; the other end of the resistor R15 is grounded; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6B; the D port of the D flip-flop U6B is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U6B; one end of the resistor R16 is connected with the PR end of the D flip-flop U6B, and the other end is connected with the Q end of the D flip-flop U6B; the CLR end of the D trigger U6B is connected with a +5V power supply, and the Q end of the D trigger U6B is not connected with the CLR end of the D trigger U8A; the D end and the CLK end of the D trigger U8A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 21, is recorded as a port PHASE _ out and is connected with the input end of the singlechip 22;
the structure of the controllable frequency source 24 is that one end of the thermistor Rt1 is connected with the inverting input end of the operational amplifier U9, and the other end is connected with the output end of the operational amplifier U9; one end of the resistor R17 is connected with the inverting input end of the operational amplifier U9, and the other end is grounded; the non-inverting input end of the operational amplifier U9 is connected with a pin 2 of a chip U11, the positive power supply is connected with a +5V power supply, the negative power supply is connected with a-5V power supply, and the output end of the operational amplifier U9 is connected with a pin 2 of a chip U10; one end of the capacitor C14 is connected with a pin 3 of the chip U10, and the other end is connected with a pin 2 of the chip U11; one end of the capacitor C15 is connected with pin 2 of the chip U11, and the other end is grounded; one end of the capacitor C16 is connected with a pin 5 of the chip U10, and the other end of the capacitor C16 is grounded; one end of the capacitor C17 is connected with a pin 5 of the chip U11, and the other end of the capacitor C17 is grounded; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R18, pin 8 is connected with one end of a resistor R19, and pin 7 is connected with one end of a resistor R20; the other end of the resistor R18 is used as an input port of the controllable frequency source and is marked as a port Sinem _ in 1; the other end of the resistor R19 is used as the other input port of the controllable frequency source and is marked as a port Sinem _ in2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 22; the other end of the resistor R20 is connected with a +5V power supply; pin 1 and pin 10 of the chip U11 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R21, pin 8 is connected with one end of a resistor R22, and pin 7 is connected with one end of a resistor R23; the other end of the resistor R21 is connected with a port SineM _ in 1; the other end of the resistor R22 is connected with a port SineM _ in2; the other end of the resistor R23 is connected with a +5V power supply; pin 2 of the chip U10 is used as an output port of the controllable frequency source and is marked as SineM _ out;
the pump light source 10 is preferably a 980nm laser light source.
The first optical coupler 11 and the second optical coupler 12 preferably have a splitting ratio of 10: a 90 1 x 2 optical coupler.
The third optical coupler 13 has a splitting ratio of 50:50, and the fourth optical coupler 15 has a splitting ratio of 50: a 50 x 2 optical coupler.
The temperature control circuit 23 is prior art, and the specific structure can be found in the invention patent "high stability thermostatic controller" (application number: 2007100559129) applied in 2007, 7, 27 of this subject group.
The piezoceramic driving circuit 25 is the prior art, and the specific structure can be found in the invention patent of 'piezoceramic driving circuit for optical fiber stress adjustment' (application number: 2007100558658) applied in 2007, 7, month and 11 of the subject group.
Has the advantages that:
1. the invention introduces the center wavelength tuning device which can be actively adjusted, and can compensate the shift of the center wavelength caused by the environment when the environmental condition changes, thereby effectively improving the stability of the center wavelength of the optical soliton output by the system.
2. The invention adopts the self-adaptive amplitude normalization circuit to normalize the amplitude of the output signal of the function conversion circuit, provides a high-quality signal for the subsequent phase comparison circuit and improves the accuracy of the phase comparison circuit.
Drawings
Fig. 1 is an overall schematic block diagram of the present invention.
Fig. 2 is a block diagram of a center wavelength tuning device used in the present invention.
Fig. 3 is a schematic circuit diagram of a function conversion circuit used in the present invention.
Fig. 4 is a schematic circuit diagram of an adaptive amplitude normalization circuit used in the present invention.
Fig. 5 is a schematic circuit diagram of a phase comparison circuit used in the present invention.
Fig. 6 is a schematic circuit diagram of a controllable frequency source for use with the present invention.
Detailed Description
The operation principle of the present invention is further explained with reference to the drawings, and it should be understood that the component parameters marked in the drawings are the preferred parameters used in the following embodiments, and do not limit the scope of the present invention.
EXAMPLE 1 Overall Structure of the invention
As shown in FIG. 1, the overall structure of the present invention has an input terminal of a polarization controller 1 (HFPC-11-1064-S-9/125-3U all-fiber polarization controller manufactured by OZ-OPTICS Inc.) connected to 90% of an output terminal of a first optical coupler 11 (manufactured by OZ-OPTICS Inc., model number FUSED-12-1064-7/125-90/10-3U-3mm, split ratio 90:10), an output terminal of the polarization controller 1 connected to a common input terminal of a1 xN optical switch 2 (an all-fiber optical switch manufactured by OZ-OPTICS Inc., model number MFOS-12-9/125-S-1060-3U), and N output terminals of the 1 xN optical switch 2 connected to a1 xN optical coupler 4 (manufactured by OZ-OPTICS Inc., model number 1060 SED-12-FU- 7/125-50/50-3U-3mm optical fiber coupler), the optical fiber group 3 is composed of N single-mode fibers (SM 1500 type common single-mode fiber of FIBERCORE), N is an integer of 2-8, the common output end of the 1 XN optical coupler 4 is connected with one end of a saturable absorber 5 (SA-1064-25-2 ps-FC/PC saturable absorber of BATOP company, Germany), the other end of the saturable absorber 5 is connected with the input end of a central wavelength tuning device 6, the output end of the central wavelength tuning device 6 is connected with the input end of an optical isolator 7 (IO-H-1064B single-mode optical isolator of THIORLABS company), the output end of the optical isolator 7 is connected with a light wave division multiplexer 9 (CORE 980/1550nm single-mode fiber) through an erbium-doped optical fiber 8 (SM-ESF-7/125 erbium-doped fiber of Nun company, USA) Wavelength division multiplexer), the 980nm end of the wavelength division multiplexer 9 is connected with the output end of a pumping light source 10 (LC 962U type pumping source of OCLARO company, the center wavelength is 980nm, the maximum single-mode output light power is 750mW), and the 1550nm end of the wavelength division multiplexer 9 is connected with the input end of a first optical coupler 11; the 10% output of the first optical coupler 11 is connected to the input of a second optical coupler 12 (manufactured by OZ-OPTICS, model number FUSED-12-1064-7/125-90/10-3U-3mm, split ratio 90:10), the 10% output of the second optical coupler 12 being the final output of the present invention, the 90% output of the second optical coupler 12 is connected to the input of a third optical coupler 13 (manufactured by OZ-OPTICS, model number FUSED-12-1060-7/125-50/50-3U-3mm, split ratio 50:50 1 x 2 fiber coupler), one output of the third optical coupler 13 is connected to one input of a fourth optical coupler 15(2 x 2 standard single mode optical coupler, split ratio 50: 50), the other output of the third optical coupler 13 is connected to a piezoelectric ceramic 14 (cylindrical piezoelectric ceramic, outer diameter 50mm, inner diameter 40mm, height 50mm), the other end of the optical fiber wound on the piezoelectric ceramic 14 is connected to the other input terminal of a fourth optical coupler 15, one output terminal of the fourth optical coupler 15 is connected to the input terminal of a first optical detector 16 (LSIPD-LD 50 type optical detector of beijing photosensitive optical technology ltd), the other output terminal of the fourth optical coupler 15 is connected to the input terminal of a second optical detector 17 (LSIPD-LD 50 type optical detector of beijing photosensitive optical technology ltd), the output terminal of the first optical detector 16 is connected to one input terminal of a differential amplifier circuit 18, the output terminal of the second optical detector 17 is connected to the other input terminal of the differential amplifier circuit 18, the output terminal of the differential amplifier circuit 18 is connected to the input terminal of a function converter circuit 19, the output terminal of the function converter circuit 19 is connected to the signal input terminal of an adaptive amplitude normalization circuit 20, the signal output end of the adaptive amplitude normalization circuit 20 is connected with one input end of a phase comparison circuit 21, the output end of the phase comparison circuit 21 is connected with a single chip microcomputer 22(STC89C51 single chip microcomputer), the single chip microcomputer 22 is connected with the input control end of a controllable frequency source 24, the sine signal output end of the controllable frequency source 24 is connected with the other input end of the phase comparison circuit 21 and is also connected with the input end of a piezoelectric ceramic driving circuit 25 (a device manufactured by a subject group, the specific structure is shown in patent ZL200710055865.8), the output end of the piezoelectric ceramic driving circuit 25 is connected with the control end of piezoelectric ceramic 14, the single chip microcomputer 22 is connected with a temperature control circuit 23, and the temperature control circuit 23 is also connected with a central wavelength tuning device 6; the single chip microcomputer 22 is connected with the temperature setting end of the temperature control circuit 23, the current output end of the temperature control circuit 23 is connected with the semiconductor thermoelectric cooler 64 in the center wavelength tuning device 6, and the thermistor input end of the temperature control circuit 23 is connected with the thermistor 63 of the center wavelength tuning device 6.
The center wavelength tuning device 6 has a structure in which a semiconductor thermoelectric cooler 64(TEC12705) is interposed between the lower surface of the aluminum block 61 and the upper surface of the heat sink 65; a thermistor 63(10k omega @25 degrees) and a Bragg grating 62(JH-FGA-A101) are attached to the upper surface of the aluminum block 61; the thermistor 63 is connected with the thermistor input end of the temperature control circuit 23; the semiconductor thermoelectric cooler 64 is connected with the current output end of the temperature control circuit 23; one end of the bragg grating 62 is connected to a second port of an optical circulator 66 (a PIOC3-15 type optical circulator from shanghai vastly corporation), a first port of the optical circulator 66 is connected to the saturable absorber 5 as an input terminal of the center wavelength tuning device 6, and a third port of the optical circulator 66 is connected to an input terminal of the optical isolator 7 as an output terminal of the center wavelength tuning device 6. When the system detects that the central wavelength of the output optical soliton changes, the central wavelength tuning device 6 can be used for carrying out reverse adjustment, and further the central wavelength of the output optical soliton is stabilized.
The structure of the function transformation circuit 19 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 19, is recorded as a port ACOS _ in, and is connected with the output end of the differential amplification circuit 18; the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 19, is recorded as a port ACOS _ out, and is connected with the input end of the adaptive amplitude normalization circuit 20; the type of the trigonometric function converter U1 is AD 639. The circuit has an inverse cosine transform function, and performs inverse cosine processing on a signal output by the differential amplification circuit 18.
Because the signal amplitudes output by the function conversion circuit 19 under different conditions are also different, and the time is large and small, so that the phase comparison circuit 21 is convenient to process, and the phase comparison precision is improved, the invention also designs the adaptive amplitude normalization circuit 20, and the specific structure is as shown in fig. 4, one end of a capacitor C9 is connected with one end of a resistor R3 and a pin 3 of a chip U2, the other end of the resistor R3 is grounded, and the other end of the capacitor C9 is used as the input end of the adaptive amplitude normalization circuit 20, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of the function conversion circuit 19; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R12 and a resistor R11, the other end of the resistor R12 is grounded, the other end of the resistor R11 is connected with the output end of the operational amplifier U4 and one end of a capacitor C8, the positive power supply end of the operational amplifier U4 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C8 is connected with one end of a resistor R10, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the sliding end of the sliding rheostat W3, one end of the sliding rheostat W3 is connected with a +5V power supply, and the other end of the sliding rheostat W3 is grounded; one end of a capacitor C7 is connected with one end of a resistor R9 and the non-inverting input end of an operational amplifier U4, the other end of the capacitor C7 is grounded, the other end of the resistor R9 is connected with one end of a resistor R7 and the output end of an operational amplifier U3, and the other end of the resistor R7 is connected with the inverting input end of the operational amplifier U3; one end of the resistor R8 is connected with the non-inverting input end of the operational amplifier U3, and the other end of the resistor R8 is grounded; the positive power supply end of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply end is grounded; pin 10 of the chip U2 is used as the output terminal of the adaptive amplitude normalization circuit 20, which is denoted as port ADAPT _ out, and is connected to one input terminal of the phase comparison circuit 21; pin 10 of the chip U2 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with one end of the resistor R5 and the inverting input end of the operational amplifier U3, the other end of the resistor R5 is connected with the anode of the diode D2, and the cathode of the diode D2 is connected with the sliding end of the sliding rheostat W2; one end of the slide rheostat W2 is connected with the cathode of the diode D3 and is grounded, the other end of the slide rheostat W2 is connected with one end of the resistor R6 and the anode of the diode D3, and the other end of the resistor R6 is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip with model number AD 8367. The circuit makes the amplitude of the signal output from the function conversion circuit 19 uniform to a proper magnitude (frequency, phase unchanged) so as to be suitable for the phase comparison circuit 21 to process, thereby improving the accuracy of phase comparison.
Example 5 phase comparison Circuit
The structure of the PHASE comparison circuit 21 is shown in fig. 5, wherein one end of a capacitor C10 is connected to the non-inverting input terminal of the operational amplifier U5 and one end of a resistor R13, and the other end of the capacitor C10 is used as an input terminal of the PHASE comparison circuit 21, is recorded as a port PHASE _ in1, and is connected to a port ADAPT _ out of the adaptive amplitude normalization circuit 20; the other end of the resistor R13 is grounded; the positive power supply end of the operational amplifier U5 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6A; the D port of the D flip-flop U6A is grounded; one end of the capacitor C11 is grounded, and the other end of the capacitor C11 is connected with the PR end of the D flip-flop U6A; one end of the resistor R14 is connected with the PR end of the D flip-flop U6A, and the other end is connected with the Q end of the D flip-flop U6A; the CLR end of the D flip-flop U6A is connected with a +5V power supply, and the Q end of the D flip-flop U6A is not connected with the PR end of the D flip-flop U8A; one end of the capacitor C12 is connected to the non-inverting input terminal of the operational amplifier U7 and one end of the resistor R15, and the other end of the capacitor C12 is used as the other input terminal of the PHASE comparator circuit 21, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 24; the other end of the resistor R15 is grounded; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6B; the D port of the D flip-flop U6B is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U6B; one end of the resistor R16 is connected with the PR end of the D flip-flop U6B, and the other end is connected with the Q end of the D flip-flop U6B; the CLR end of the D trigger U6B is connected with a +5V power supply, and the Q end of the D trigger U6B is not connected with the CLR end of the D trigger U8A; the D end and the CLK end of the D flip-flop U8A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 21, which is recorded as the port PHASE _ out, and is connected to the input end of the single chip microcomputer 22. The circuit compares the phase of the standard sine wave output by the controllable frequency source 24 with the phase of the sine wave output by the adaptive amplitude normalization circuit 20, and the compared result is sent to the single chip microcomputer.
EXAMPLE 6 controllable frequency Source
The structure of the controllable frequency source 24 is that one end of the thermistor Rt1 is connected with the inverting input end of the operational amplifier U9, and the other end is connected with the output end of the operational amplifier U9; one end of the resistor R17 is connected with the inverting input end of the operational amplifier U9, and the other end is grounded; the non-inverting input end of the operational amplifier U9 is connected with a pin 2 of a chip U11, the positive power supply is connected with a +5V power supply, the negative power supply is connected with a-5V power supply, and the output end of the operational amplifier U9 is connected with a pin 2 of a chip U10; one end of the capacitor C14 is connected with a pin 3 of the chip U10, and the other end is connected with a pin 2 of the chip U11; one end of the capacitor C15 is connected with pin 2 of the chip U11, and the other end is grounded; one end of the capacitor C16 is connected with a pin 5 of the chip U10, and the other end of the capacitor C16 is grounded; one end of the capacitor C17 is connected with a pin 5 of the chip U11, and the other end of the capacitor C17 is grounded; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R18, pin 8 is connected with one end of a resistor R19, and pin 7 is connected with one end of a resistor R20; the other end of the resistor R18 is used as an input port of the controllable frequency source and is marked as a port Sinem _ in 1; the other end of the resistor R19 is used as the other input port of the controllable frequency source and is marked as a port Sinem _ in2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 22; the other end of the resistor R20 is connected with a +5V power supply; pin 1 and pin 10 of the chip U11 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R21, pin 8 is connected with one end of a resistor R22, and pin 7 is connected with one end of a resistor R23; the other end of the resistor R21 is connected with a port SineM _ in 1; the other end of the resistor R22 is connected with a port SineM _ in2; the other end of the resistor R23 is connected with a +5V power supply; pin 2 of chip U10 serves as the output port of controllable frequency source 24 and is denoted as SineM _ out. The module outputs a standard sine wave with adjustable frequency, provides a required modulation signal for the piezoelectric ceramic driving circuit 25, and provides a reference phase reference for the phase comparison circuit 21.
Example 7 working principle of the invention
The working principle of the present invention will be described with reference to the above embodiments and the accompanying drawings.
In the overall block diagram shown in fig. 1, a polarization controller 1, a1 xn optical switch 2, an optical fiber group 3 to a first optical coupler 11 form a basic resonant cavity for generating optical solitons, when optical fibers with different lengths are selected from the optical fiber group 3 through the 1 xn optical switch 2 and the 1 xn optical coupler 4, the resonant cavity generates optical solitons of different types, a part of signals of the generated optical solitons enter a mach zehnder interferometer formed by a third optical coupler 13, a piezoelectric ceramic 14, a piezoelectric ceramic driving circuit 25 and a fourth optical coupler 15 through 90% of output ends of the second optical coupler 12 for interference, and a controllable frequency source 24 provides a control signal sin (ω t) for the mach zehnder interferometer, which is influenced by the central wavelength of the optical solitons in the interferometer, converted into electrical signals through a first optical detector 16 and a second optical detector 17 and differentiated through a differential amplifier circuit 18, Sin (ω t + Δ θ) is obtained after the inverse cosine transformation by the function transformation circuit 19, which signal, after passing through the adaptive amplitude normalization circuit 20, is amplitude adjusted to a fixed magnitude, when the phase of the signal is changed compared to the sine signal sin (ω t) generated by the controllable frequency source 24, the phase difference between the two signals is detected by a phase comparison circuit 21 and sent to a singlechip 22, the phase difference is determined by the central wavelength of the optical soliton generated by the basic resonant cavity, when the singlechip 22 detects that the central wavelength is changed from the preset central wavelength, the temperature of the bragg grating in the central wavelength tuning device 6 is adjusted by the temperature control circuit 23 to influence the central wavelength of the optical solitons in the basic cavity in the opposite direction, further, the purpose of stabilizing the center wavelength is achieved, and the final optical soliton signal is output from the 10% output end of the second optical coupler 12.
Claims (4)
1. A high-stability optical soliton generator based on an erbium-doped fiber laser structurally comprises an optical isolator (7), a pump light source (10), a pump light source (9), a pump light source (8), a pump light source (9) and a first optical coupler (11), wherein the output end of the optical isolator (7) is connected with the common end of the optical wavelength division multiplexer (9) through an erbium-doped fiber (8); the optical coupler comprises a first optical coupler (11), wherein 90% of the output end of the first optical coupler is connected with the input end of a polarization controller (1), the output end of the polarization controller (1) is connected with the common input end of a1 xN optical switch (2), N output ends of the 1 xN optical switch (2) are respectively connected with N input ends of a1 xN optical coupler (4) through N different single-mode optical fibers in an optical fiber group (3), the optical fiber group (3) is composed of N single-mode optical fibers with different lengths, N is an integer of 2-8, and the common output end of the 1 xN optical coupler (4) is connected with one end of a saturable absorber (5);
the optical coupler is characterized in that the other end of the saturable absorber (5) is connected with the input end of a central wavelength tuning device (6), the output end of the central wavelength tuning device (6) is connected with the input end of an optical isolator (7), 10% of the output end of a first optical coupler (11) is connected with the input end of a second optical coupler (12), 10% of the output end of the second optical coupler (12) is used as final output, 90% of the output end of the second optical coupler (12) is connected with the input end of a third optical coupler (13), one output end of the third optical coupler (13) is connected with one input end of a fourth optical coupler (15), the other output end of the third optical coupler (13) is connected with one end of an optical fiber wound on a piezoelectric ceramic (14), and the other end of the optical fiber wound on the piezoelectric ceramic (14) is connected with the other input end of the fourth optical coupler (15), one output end of a fourth optical coupler (15) is connected with the input end of a first optical detector (16), the other output end of the fourth optical coupler (15) is connected with the input end of a second optical detector (17), the output end of the first optical detector (16) is connected with one input end of a differential amplification circuit (18), the output end of the second optical detector (17) is connected with the other input end of the differential amplification circuit (18), the output end of the differential amplification circuit (18) is connected with the input end of a function conversion circuit (19), the output end of the function conversion circuit (19) is connected with the signal input end of an adaptive amplitude normalization circuit (20), the signal output end of the adaptive amplitude normalization circuit (20) is connected with one input end of a phase comparison circuit (21), the output end of the phase comparison circuit (21) is connected with a single chip microcomputer (22), and the single chip microcomputer (22) is connected with the input control end of a controllable frequency source (24), the sine signal output end of a controllable frequency source (24) is connected with the other input end of the phase comparison circuit (21) and is also connected with the input end of a piezoelectric ceramic driving circuit (25), the output end of the piezoelectric ceramic driving circuit (25) is connected with the control end of piezoelectric ceramic (14), a singlechip (22) is connected with the temperature setting end of a temperature control circuit (23), the current output end of the temperature control circuit (23) is connected with a semiconductor thermoelectric cooler (64) in a central wavelength tuning device (6), and the thermistor input end of the temperature control circuit (23) is connected with a thermistor (63) of the central wavelength tuning device (6);
the structure of the central wavelength tuning device (6) is that a semiconductor thermoelectric cooler (64) is clamped between the lower surface of an aluminum block (61) and the upper surface of a radiating fin (65); the thermistor (63) and the Bragg grating (62) are attached to the upper surface of the aluminum block (61); the thermistor (63) is connected with the thermistor input end of the temperature control circuit (23); the semiconductor thermoelectric cooler (64) is connected with the current output end of the temperature control circuit (23); one end of the Bragg grating (62) is connected with a second port of the optical circulator (66), a first port of the optical circulator (66) is used as the input end of the central wavelength tuning device (6) and is connected with the saturable absorber (5), and a third port of the optical circulator (66) is used as the output end of the central wavelength tuning device (6) and is connected with the input end of the optical isolator (7);
the structure of the function conversion circuit (19) is that one end of a capacitor C3 is connected with a pin 12 of a trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function conversion circuit (19), is recorded as a port ACOS _ in and is connected with the output end of the differential amplification circuit (18); the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of a sliding rheostat W1, one end of a sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a pin 14 of a trigonometric function converter U1, and the sliding end of a sliding rheostat W1 is used as the output end of a function transformation circuit (19), is recorded as a port ACOS _ out and is connected with the input end of an adaptive amplitude normalization circuit (20); the model of the trigonometric function converter U1 is AD 639;
the adaptive amplitude normalization circuit (20) is structurally characterized in that one end of a capacitor C9 is connected with one end of a resistor R3 and a pin 3 of a chip U2, the other end of the resistor R3 is grounded, and the other end of the capacitor C9 is used as an input end of the adaptive amplitude normalization circuit (20), is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit (19); pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R12 and a resistor R11, the other end of the resistor R12 is grounded, the other end of the resistor R11 is connected with the output end of the operational amplifier U4 and one end of a capacitor C8, the positive power supply end of the operational amplifier U4 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C8 is connected with one end of a resistor R10, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the sliding end of the sliding rheostat W3, one end of the sliding rheostat W3 is connected with a +5V power supply, and the other end of the sliding rheostat W3 is grounded; one end of a capacitor C7 is connected with one end of a resistor R9 and the non-inverting input end of the operational amplifier U4, the other end of the capacitor C7 is grounded, the other end of the resistor R9 is connected with one end of a resistor R7 and the output end of the operational amplifier U3A, and the other end of the resistor R7 is connected with the inverting input end of the operational amplifier U3A; one end of the resistor R8 is connected with the non-inverting input end of the operational amplifier U3A, and the other end is grounded; the positive power supply end of the operational amplifier U3A is connected with a +5V power supply, and the negative power supply end is grounded; a pin 10 of the chip U2 is used as an output end of the adaptive amplitude normalization circuit (20), is recorded as a port ADAPT _ out, and is connected with one input end of the phase comparison circuit (21); a pin 10 of the chip U2 is connected with the anode of a diode D1, the cathode of a diode D1 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with one end of a resistor R5 and the inverted input end of an operational amplifier U3A, the other end of the resistor R5 is connected with the anode of the diode D2, and the cathode of a diode D2 is connected with the sliding end of a sliding rheostat W2; one end of the slide rheostat W2 is connected with the cathode of the diode D3 and is grounded, the other end of the slide rheostat W2 is connected with one end of the resistor R6 and the anode of the diode D3, and the other end of the resistor R6 is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;
the structure of the PHASE comparison circuit (21) is that one end of a capacitor C10 is connected with the non-inverting input end of an operational amplifier U5 and one end of a resistor R13, the other end of the capacitor C10 is used as one input end of the PHASE comparison circuit (21), is recorded as a port PHASE _ in1 and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit (20); the other end of the resistor R13 is grounded; the positive power supply end of the operational amplifier U5 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6A; the D port of the D flip-flop U6A is grounded; one end of the capacitor C11 is grounded, and the other end of the capacitor C11 is connected with the PR end of the D flip-flop U6A; one end of the resistor R14 is connected with the PR end of the D flip-flop U6A, and the other end is connected with the Q end of the D flip-flop U6A; the CLR end of the D flip-flop U6A is connected with a +5V power supply, and the Q end of the D flip-flop U6A is not connected with the PR end of the D flip-flop U8A; one end of the capacitor C12 is connected with the non-inverting input end of the operational amplifier U7 and one end of the resistor R15, the other end of the capacitor C12 is used as the other input end of the PHASE comparison circuit (21), is recorded as a port PHASE _ in2 and is connected with a port Sinem _ out of the controllable frequency source (24); the other end of the resistor R15 is grounded; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D flip-flop U6B; the D port of the D flip-flop U6B is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U6B; one end of the resistor R16 is connected with the PR end of the D flip-flop U6B, and the other end is connected with the Q end of the D flip-flop U6B; the CLR end of the D trigger U6B is connected with a +5V power supply, and the Q end of the D trigger U6B is not connected with the CLR end of the D trigger U8A; the D end and the CLK end of the D trigger U8A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit (21), is recorded as a port PHASE _ out and is connected with the input end of the singlechip (22);
the structure of the controllable frequency source (24) is that one end of the thermistor Rt1 is connected with the inverting input end of the operational amplifier U9, and the other end is connected with the output end of the operational amplifier U9; one end of the resistor R17 is connected with the inverting input end of the operational amplifier U9, and the other end is grounded; the non-inverting input end of the operational amplifier U9 is connected with a pin 2 of a chip U11, the positive power supply is connected with a +5V power supply, the negative power supply is connected with a-5V power supply, and the output end of the operational amplifier U9 is connected with a pin 2 of a chip U10; one end of the capacitor C14 is connected with a pin 3 of the chip U10, and the other end is connected with a pin 2 of the chip U11; one end of the capacitor C15 is connected with pin 2 of the chip U11, and the other end is grounded; one end of the capacitor C16 is connected with a pin 5 of the chip U10, and the other end of the capacitor C16 is grounded; one end of the capacitor C17 is connected with a pin 5 of the chip U11, and the other end of the capacitor C17 is grounded; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R18, pin 8 is connected with one end of a resistor R19, and pin 7 is connected with one end of a resistor R20; the other end of the resistor R18 is used as an input port of the controllable frequency source and is marked as a port Sinem _ in 1; the other end of the resistor R19 is used as the other input port of the controllable frequency source and is recorded as a port SineM _ in2, and the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip (22); the other end of the resistor R20 is connected with a +5V power supply; pin 1 and pin 10 of the chip U11 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R21, pin 8 is connected with one end of a resistor R22, and pin 7 is connected with one end of a resistor R23; the other end of the resistor R21 is connected with a port SineM _ in 1; the other end of the resistor R22 is connected with a port SineM _ in2, and the other end of the resistor R23 is connected with a +5V power supply; pin 2 of the chip U10 is used as an output port of the controllable frequency source and is denoted as SineM _ out.
2. An erbium-doped fiber laser-based high-stability optical soliton generator as claimed in claim 1, wherein said pump light source (10) is a 980nm laser light source.
3. An erbium-doped fiber laser-based high-stability optical soliton generator according to claim 1, wherein the first optical coupler (11) and the second optical coupler (12) are both split in a ratio of 10: a 90 1 x 2 optical coupler.
4. An erbium-doped fiber laser-based high-stability optical soliton generator as claimed in claim 1, wherein said third optical coupler (13) has a splitting ratio of 50:50, and the fourth optical coupler (15) has a splitting ratio of 50: a 50 x 2 optical coupler.
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