CN108880560A - A kind of matrix keyboard reversal process scanning circuit - Google Patents
A kind of matrix keyboard reversal process scanning circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
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Abstract
A kind of matrix keyboard reversal process scanning circuit, the X root line and Y root alignment of matrix keyboard are connected to pull-up resistor, are replaced by sampling pulse control X root line with Y root alignment and are in low level state；Y root alignment state latch when X root line is in low level obtains Y and ranks status signal, and X root line state latch when Y root alignment is in low level obtains X row status signals；X row status signals and Y rank the N bit keyboard status signal that status signal collectively constitutes matrix keyboard output.The circuit scans the reversal process of matrix keyboard to be realized using sequential logical circuit, not using microcontrollers such as single-chip microcontroller, ARM, does not have to operation program, reliable operation.
Description
Present patent application is divisional application, and application No. is 201610003404.5, the applying date is in January, 2016 for original bill
5 days, entitled matrix keyboard scanning circuit and scanning encoding method.
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard reversal process scanning circuit.
Background technique
With the continuous development of embedded technology, current each electronic product generallys use microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by operation microcontroller in program come into
Row, encounters interference, program is caused to run fast, and scanner program is by cisco unity malfunction.
Application No. is the patents of invention of CN201010153560.2 " a kind of fast scanning and positioning method of matrix keyboard " to adopt
The Scan orientation process for entering keyboard with the mode that keyboard interrupt triggers is judged using the method that keyboard scan step is repeated several times
Whether key is effective, and carries out state judgement to key assignments obtained；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then enters singly-bound tupe；Combination key operation in this way then enters Macintosh tupe.Described in the patent
Method solves the shake of the keyboard as caused by the mechanical property of keyboard itself and causes the Problem-Errors such as wrong key, continuous touching,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with key operation is combined；
Not accounting for keyboard state maintains a period of time just to execute the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to modify keyboard scan finder structure.
Summary of the invention
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard reversal process scanning circuit, by X row-Y column key-press matrix, row three state buffer, column three state buffer, row status register,
Column-shaped state register group at.The line of all key-press matrixs is respectively connected to the output end of row three state buffer, all to press bond moment
The alignment of battle array is respectively connected to the output end of column three state buffer；All input terminals of row three state buffer and column three state buffer
It is connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all key-press matrixs
Alignment is respectively connected to the input terminal of column status register；The output end of the row status register is defeated with column status register
Outlet exports N bit keyboard status signal jointly；The N bit keyboard status signal is level signal；The N=X+Y.
Replaced by sampling pulse control row three state buffer with column three state buffer and is enabled effectively.Row three state buffer is taking
The low level of sample pulse is enabled effectively, column three state buffer is enabled effective in the high level of sampling pulse；Column status register exists
The rising edge of sampling pulse carries out data latch, and row status register carries out data latch in the failing edge of sampling pulse.Or
It is that row three state buffer is enabled in the low level of sampling pulse in high flat enabled effective, the column three state buffer of electricity of sampling pulse
Effectively；Column status register carries out data latch, rising of the row status register in sampling pulse in the failing edge of sampling pulse
Along progress data latch.
Further, the problem of positioning for the keyboard scan of solving matrix formula, matrix keyboard reversal process scanning circuit also wraps
The scanning encoding circuit of the first shift register, the second shift register, state Code memory, encoder composition is included, scanning is compiled
Code circuit synchronizes control by scanning pulse and shift pulse.
First shift register has the function of the input of N parallel-by-bit, the output of N parallel-by-bit and Serial output；Described second
Shift register has serial input, N parallel-by-bit output function.
The N parallel-by-bit input terminal of first shift register is connected to N bit keyboard status signal output；Second displacement
The serial input terminal of register is connected to the serial output terminal of the first shift register；First shift register, the second displacement are posted
The shift pulse input terminal of storage is connected to shift pulse, and the presetting pulse input terminal of the first shift register is connected to scanning
Pulse.The presetting pulse of first shift register is used to carry out the N parallel-by-bit input data of the first shift register defeated
Enter to latch.
The state Code memory is 2 × N binary registers；N position data input pin in state Code memory connects
It is connected to the N parallel-by-bit output end of the first shift register, in addition N data input pins are connected to the position N of the second shift register
Parallel output terminal；The reception pulse input end of the state Code memory is connected to scanning pulse.
The encoder has 2 × N coding input ends, and the coding input end 2 × N is connected to state Code memory
2 × N data output ends.The scanning pulse, shift pulse timing meet it is claimed below：Scanning pulse is shift pulse
Fractional-N frequency signal, and be positive burst pulse or negative burst pulse.The period of the scanning pulse is 20~100ms.
First shift register, the second shift register are shifted in the rising edge of shift pulse simultaneously, scanning pulse
Positive burst pulse or negative burst pulse be between the rising edge of former and later two shift pulses；Either, first displacement is posted
Storage, the second shift register are shifted in the failing edge of shift pulse simultaneously, the positive burst pulse or negative burst pulse of scanning pulse
Between failing edge in former and later two shift pulses.
The presetting pulse of first shift register be edge effectively and scanning pulse be positive burst pulse when, it is desirable that first
The presetting pulse of shift register is that rising edge is effective, and the reception pulse of state Code memory is that failing edge is effective；Described first
The presetting pulse of shift register be edge effectively and scanning pulse be negative burst pulse when, it is desirable that the first shift register it is preset
Pulse is that failing edge is effective, and the reception pulse of state Code memory is that rising edge is effective；First shift register it is preset
When pulse is that high level is effective, it is desirable that scanning pulse is positive burst pulse, and the reception pulse of state Code memory is that failing edge is effective；
When the presetting pulse of first shift register is that low level is effective, it is desirable that scanning pulse is negative burst pulse, status code deposit
The reception pulse of device is that rising edge is effective.
2 × N position data output end of the state Code memory exports 2 × N status codes；The status code is by effective
Status code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；It is described effective
Status code is generated by effective keyboard operation or state, and it is corresponding effective that encoder inputs corresponding output when each effective status code
Key number；The invalid state code is generated by invalid keyboard operation or state, and encoder inputs all corresponding when all invalid state codes
Export invalid key number.
The encoder has M key output ends, and the selection of M value should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The matrix keyboard reversal process scanning circuit further includes that keyboard state change pulse generates unit, for judging square
Whether the key number of configuration keyboard output changes, and when the key number of matrix keyboard output changes, exports keyboard state
Change pulse.
The keyboard state change pulse generate unit by or door, M delay buffer and M XOR gate form；M are prolonged
Slow buffer for carrying out signal delay to the position the M key number that matrix keyboard exports respectively；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The position N, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：The reversal process of matrix keyboard is scanned and realizes do not have using sequential logical circuit
Have using microcontrollers such as single-chip microcontroller, ARM, does not have to operation program, reliable operation.Keyboard localization method will be to single key stroke, group
Close key operation, the Scan orientation that keyboard maintains state to operate, by meeting the scanning pulse of specific time sequence requirement, shift pulse controls
Be converted into the status code of same binary length, handled by the way of Unified coding, single key stroke, combination key operation,
Keyboard maintains state operation to be only embodied in not being same as above for status code；If necessary to increase and decrease button operation function or adjust key
Operating function does not need modification circuit structure, only need to more be adapted according to the status code after increase and decrease and the corresponding relationship between key number
The encoded content of code device, the storage content for remodifying write-in read-only memory.
Detailed description of the invention
Fig. 1 is the matrix keyboard reversal process scanning circuit functional block diagram for including scanning encoding circuit；
Fig. 2 is matrix keyboard reversal process scanning circuit embodiment；
Fig. 3 is the scanning encoding circuit diagram of the embodiment of the present invention；
Fig. 4 is the first shift-register circuit figure of the embodiment of the present invention；
Fig. 5 is the pulse sequence figure of the embodiment of the present invention；
Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 8 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is the matrix keyboard scanning circuit functional block diagram for including scanning encoding circuit.Matrix keyboard reversal process is swept
Scanning circuit can be individually composed by the matrix keyboard 400 in Fig. 1, or further include the first shift register 100 in Fig. 1,
Second shift register 200, state Code memory 500, encoder 300.First shift register 100, the second shift register
200, state Code memory 500, encoder 300 form scanning encoding circuit.
Fig. 2 is the matrix keyboard reversal process scanning circuit embodiment being individually composed by matrix keyboard 400, i.e. matrix form
The embodiment of keyboard 400 shares 2 rows, 2 column, and totally 4 keys, by key S1, key S2, key S3, key S4 and are connected to electricity
Pull-up resistor R1, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4 and row three state buffer 401, the column three of source+VCC
State buffer 402, row status register 403, column status register 404 form.2 output end Y1 of row three state buffer 401,
Y2 is respectively connected to 2 lines, and 2 output ends Y3, Y4 of column three state buffer 402 are respectively connected to 2 alignments；Row tri-state is slow
All input terminal X1~X4 for rushing device 401 and column three state buffer 402 are connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of column status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output ends Q41, Q42 of row status register 403 export row state
Signal I1, I2,2 output ends Q43, Q44 of column status register 404 export column status signal I3, I4；Row status register
403 2 output ends and 2 output ends of column status register 404 collectively constitute 4 bit keyboard status signal outputs, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low level of row three state buffer 401 is effective, and column three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the sampling pulse CK output end of oscillator 500.Row status register 403
It is exported with reception pulse input end CLK3, CLK4 of column status register 404 sampling pulse CK for being connected to oscillator 500
End, failing edge of the row status register 403 in sampling pulse CK carry out data latch, and column status register 404 is in sampling pulse
The rising edge of CK carries out data latch.
When row three state buffer 401 and column three state buffer 402 are using the three state buffer with model, for example, making simultaneously
When with three state buffer 74HC241, the enabled input of 74HC241 is that high level is effective, therefore, sampling pulse CK output end with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With column status register 404 using the data register with model, for example, row status register 403 and column status register 404
When using double D trigger 74HC74 composition data register, the triggering input of 74HC74 is that rising edge is effective, therefore, is being taken
Between sample pulse CK output end and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
The first shift register 100, the second shift register 200, state Code memory 500, encoder 300 in Fig. 1
Scanning encoding circuit is formed, embodiment circuit diagram is as shown in Figure 3.The status signal of 400 embodiment of matrix keyboard output has 4
Position, therefore, the first shift register 100, the second shift register 200 are all 4 binary shift registers, wherein first
Shift register 100 has the function of that input, parallel output and Serial output parallel, the second shift register 200 have serial defeated
Enter, parallel output function；4 parallel input terminal L0~L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4,
The serial input terminal D2 of second shift register 200 is connected to the serial output terminal Q13 of the first shift register 100.First moves
Bit register 100, the second shift register 200 shift pulse input terminal CLK1, CLK2 be connected to shift pulse CP2,
The presetting pulse input terminal CLK0 of one shift register 100 is connected to scanning pulse CP1.
State Code memory 500 requires 8 bit binary datas of deposit, 4 companies in 8 data input pin D57~D50
Be connected to parallel output terminal Q13~Q10 of the first shift register 100, in addition 4 be connected to the second shift register 200 and
Row output end Q23~Q20；In embodiment, D57~D54 is connected to Q23~Q20, and D53~D50 is connected to Q13~Q10.State
The reception pulse input end CLK5 of Code memory 500 is connected to scanning pulse CP1.
8 input terminal A7~A0 of encoder 300 be connected to 8 data output end Q57 of state Code memory 500~
Q50.Encoder 300, which exports, is scanned 4 determining binary system keys number of coding.
In Fig. 3 embodiment, the second shift register 200 can choose to be made of various medium-scale integration shift registers,
Or it is made of edge triggered flip flop；When forming the second shift register 200 by edge triggered flip flop, preferably touched by the D of edging trigger
Send out device composition.State Code memory 500 is made of edge triggered flip flop, is preferably made of the d type flip flop of edging trigger, for example, choosing
Selecting double D trigger CD4013, perhaps 4D trigger 74HC175 or 8D trigger 74HC273 is formed.
Fig. 4 is the circuit diagram of the first shift register 100 of the embodiment of the present invention, by the high electricity of 4 set, reset function
101~104,8 nor gates 105~112 of effective d type flip flop are put down to form.In embodiment, d type flip flop 101~104 selects double D
Trigger CD4013, trigger pulse rising edge are effective.Scanning pulse CP1 controls d type flip flop by 8 nor gates 105~112
101~104 set, reset function.By taking d type flip flop 101 as an example, when scanning pulse CP1 is high level, nor gate 105 or non-
Door 106 exports low level, and the set of d type flip flop 101, reset function are invalid；When scanning pulse CP1 is low level and L0=0, or
The output of NOT gate 105 isThe output of nor gate 106 is L0, i.e., the set function of d type flip flop 101 is invalid, reset function has
Effect, makes Q10=0；When scanning pulse CP1 is low level and L0=1, the output of nor gate 105 isThe output of nor gate 106
For L0, i.e. the set function of d type flip flop 101 is effective, reset function is invalid, makes Q10=1.The work of d type flip flop 102~104 is former
Reason is as d type flip flop 101, when scanning pulse CP1 is low level, Q10=L0, Q11=L1, Q12=L2, Q13=L3；When
Scanning pulse CP1 be high level when, due to trigger pulse input terminal CLK10, CLK11 of d type flip flop 101~104, CLK12,
CLK13 is connected to CP2, and therefore, in the rising edge of each shift pulse CP2, the first shift register 100 moves primary position, i.e.,
Q13=Q12, Q12=Q11, Q11=Q10, Q10=0.
In Fig. 3 embodiment, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output end C3~C0 of encoder 300.
The working principle of matrix keyboard reversal process scanning circuit is as follows：
Scanning encoding circuit scanning pulse CP1, shift pulse CP2 control under work, relevant pulse sequence such as Fig. 5
It is shown.
The timing of CP1, CP2 meet claimed below in embodiment：The 4 frequency dividing letters that scanning pulse CP1 is shift pulse CP2
Number, and be positive burst pulse or negative burst pulse and in shift pulse CP2 control front and back secondary displacement movement between.Matrix form
When the status signal of keyboard reversal process scanning circuit output is N, scanning pulse CP1 is the Fractional-N frequency signal of shift pulse CP2.
Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention, by oscillator 801, frequency divider 802, monostable generator
803 compositions.CP2 pulse in Fig. 5 is generated by oscillator, and CP2 send to frequency divider 802 and carries out 4 frequency dividings, the output of frequency divider 802
It send to the input of monostable generator 803, monostable generator 803 exports CP1 pulse.
Oscillator 801 is multivibrator.The period of scanning pulse CP1 is 20~100ms.CP1, CP2 can also be by squares
Circuit or device except configuration keyboard scan coding circuit provide.
In Fig. 2,4 keys of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard reversal process scanning circuit is controlled by sampling pulse CK, is obtained using reversal process
Keyboard state signal I4, I3, I2, I1.For example, the keyboard state signal of key pressing is not the keyboard state that 1111, S1 is pressed
Signal is 1010, and the keyboard state signal that S1, S2 are pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key
Value.Sampling pulse CK can choose one in scanning pulse CP1, shift pulse CP2, preferably make shift pulse CP2 simultaneously
For sampling pulse CK.
Sampling pulse CK control carries out the method that key assignments is read in sampling to matrix keyboard：In the low electricity of sampling pulse CK
It is flat, all lines are controlled by row three state buffer 401 and export low level, column three state buffer 402 exports the open column of high-impedance state
Line；It is sampled in the rising edge of sampling pulse CK by column status register 404 and reads alignment state as the 2 high of key assignments；It is taking
The high level of sample pulse CK controls all alignments by column three state buffer 402 and exports low level, and row three state buffer 401 is defeated
The open line of high-impedance state out；It is sampled in the failing edge of sampling pulse CK by row status register 403 and reads line state as key
Low 2 of value；In cycles, 4 key assignments that column status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from sampling pulse CK control and reads the method for key assignments it is found that row three state buffer
401 when the low level of sampling pulse CK enables effective, while requiring column status register 404 in the rising edge of sampling pulse CK
Carry out data latch, column three state buffer 402 is taking in enabled effective, the row status register 403 of the high level of sampling pulse CK
The failing edge of sample pulse CK carries out data latch.In turn, if high level of the row three state buffer 401 in sampling pulse CK makes
When can be effective, while column status register 404 being required to carry out data latch, column three state buffer in the failing edge of sampling pulse CK
402 sampling pulse CK low level is enabled effectively, rising edge that row status register 403 is in sampling pulse CK carries out data lock
It deposits.
During above-mentioned sampling pulse CK controls sampling and reads key assignments, row status register 403, column status register
404 precisely column three state buffers 402 and at the time of the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or column status register 404 can be sampled correctly.If it is required that having in certain timing
Allowance, then can be to being connected to column three state buffer 402 and the sampling pulse CK of row three state buffer 401 postpones, method
Be enable sampling pulse CK by RC retardation ratio circuit be then connected to row three state buffer 401 and column three state buffer 402 EN1,
EN2, delay time are determined by RC retardation ratio circuit, determine that the principle of the delay time of RC retardation ratio circuit is, the sampling pulse of delay
CK phase is no more than 90 °；Either sampling pulse CK is then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of column three state buffer 402, delay time at this time is the overall delay time of several gate circuits.
First shift register 100 exports matrix keyboard reversal process scanning circuit under the control of scanning pulse CP1
Status signal I1, I2, I3, I4 carry out data latch, the output of the first shift register 100 at this time be known as now state key assignments；The
Upper periodic scanning pulses CP1, via the control of 4 CP2 pulses, was latching to first in a upper period by two shift registers 200
The output of shift register 100 is displaced to 200 output end of the second shift register, therefore, second shift register 200 at this time
State key assignments before output is known as.
Scanning pulse CP1 exports the existing state key assignments that the first shift register 100 exports, the second shift register 200
Preceding state key assignments is latched in the output end of state Code memory 500, and the output of state Code memory 500 is similarly preceding state key assignments and shows
State key assignments.
The displacement of first shift register 100, the second shift register 200 carries out at the same edge of shift pulse CP2.
In embodiment, the first shift register 100, the second shift register 200 are shifted in the rising edge of shift pulse CP2 simultaneously.
Scanning pulse CP1 be positive burst pulse when, rising edge be forward position, failing edge be rear edge；Scanning pulse CP1 is negative narrow
When pulse, failing edge is forward position, and rising edge is rear edge.
First shift register 100, the second shift register 200 in the rising edge displacement of shift pulse CP2, are swept simultaneously
The forward position and rear edge for retouching pulse CP1 are between the rising edge of former and later two shift pulses CP2, as shown in figure 5, scanning pulse
CP1 is negative burst pulse, and the forward position (failing edge) of the negative burst pulse of each of CP1 is in the falling edge of shift pulse CP2, this bears narrow
The rear edge (rising edge) of pulse is controlled by monostable generator 803, before next shift pulse CP2 rising edge, control
The forward position of scanning pulse CP1 processed and rear edge are between the rising edge of former and later two shift pulses CP2；First shift register
100, the second shift register 200 is simultaneously in the failing edge displacement of shift pulse CP2, the forward position of scanning pulse CP1 and rear edge
Between failing edge in former and later two shift pulses CP2.
The presetting pulse of first shift register 100 be edge effectively and scanning pulse CP1 be positive burst pulse when, it is desirable that the
The presetting pulse of one shift register 100 is that rising edge is effective, and the reception pulse of state Code memory 500 is that failing edge is effective；
The presetting pulse of first shift register 100 be edge effectively and scanning pulse CP1 be negative burst pulse when, it is desirable that first displacement post
The presetting pulse of storage 100 is that failing edge is effective, and the reception pulse of state Code memory 500 is that rising edge is effective.First displacement
When the presetting pulse of register 100 is that high level is effective, it is desirable that scanning pulse CP1 is positive burst pulse, state Code memory 500
Receiving pulse is that failing edge is effective；When the presetting pulse of first shift register 100 is that low level is effective, it is desirable that scanning pulse
CP1 is negative burst pulse, and the reception pulse of state Code memory 500 is that rising edge is effective.In embodiment, the first shift register
100 presetting pulse is that low level is effective, the burst pulse so scanning pulse CP1 is negative, the reception pulse of state Code memory 500
It is effective for rising edge.
In embodiment, the 4 existing state key assignments and 4 preceding state key assignments of 500 data output end of state Code memory output are common
Form 8 status codes.The current state and mode of operation of 8 status codes matrix keyboard for identification.For example, this reality
It applies in example, the status code of no key pressing is 11111111；The status code of S1 key singly-bound pushing operation is 11111010；S1 key singly-bound
It presses and the status code maintained is 10101010；The status code of S1 key singly-bound release operation is 10101111；S2 key singly-bound is pressed
The status code of operation is 11110110；The status code of S4 key singly-bound pushing operation is 11110101；The S1 of S2+S1 combination operation is pressed
Lower operation after expression first presses S2, presses the operation of S1 in the state that S2 maintenance is pressed, the status code of the operation is again
01100010。
Encoder 300 is used to status code being converted to key number.In embodiment, it is equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound pushing operation of key S1, key number are 0000；
Operation 1：The singly-bound pushing operation of key S2, key number are 0001；
Operation 2：The singly-bound pushing operation of key S3, key number are 0010；
Operation 3：Key S3 singly-bound press after maintenance state, key number be 0011；
Operation 4：After key S4 singly-bound is pressed, then the combination key operation of S2 is pressed the button, key number is 0100；
Operation 5：The singly-bound of key S1 discharges operation, and key number is 0101.
The status code and key number obtained according to above-mentioned regulation is shown in coding schedule 1：
1 coding schedule of table
| Keyboard operation | Status code (address) | Key number (storing data) |
| S1 singly-bound is pressed | 11111010 | 0000 |
| S2 singly-bound is pressed | 11110110 | 0001 |
| S3 singly-bound is pressed | 11111001 | 0010 |
| S3 singly-bound presses maintenance | 10011001 | 0011 |
| S4+S2 combination operation | 01010100 | 0100 |
| The release of S1 singly-bound | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, and the coding circuit of design meets the logical relation of table 1.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations and state have 6 effective status codes, corresponding 6 effective keys number；By state
Address A7~A0 of the code as read-only memory, in storage unit corresponding with 6 effective status codes, by corresponding key number
It is written as storing data.The status code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 1
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When read-only memory has piece selected control system, data output slow
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can according to need increase, or subtract
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M value is answered
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboard status signal
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
The N parallel-by-bit input terminal of first shift register is connected to N bit keyboard status signal output；Second displacement
The serial input terminal of register is connected to the serial output terminal of the first shift register；First shift register, the second displacement are posted
The shift pulse input terminal of storage is connected to shift pulse, and the presetting pulse input terminal of the first shift register is connected to scanning
Pulse.
The state Code memory is 2 × N.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to modify table 1 as needed, it will
Modified content re-writes the storage content of read-only memory.
The edge of scanning pulse CP1 at the time of state Code memory 500 is carried out data latch is known as state latch edge,
It is the rising edge of CP1 in embodiment.In embodiment, when matrix keyboard S1 singly-bound is pressed, after, latch preset by CP1, from
The state latch edge of CP1 starts, and until the state latch edge of next CP1, encodes output end C3~C0 run-out key number 0000；
When matrix keyboard S2 singly-bound is pressed, after, latch preset by CP1, since the state latch of CP1 along, until next CP1
Until state latch edge, run-out key number 0001；After matrix keyboard first presses S4, then S2 is pressed, encoder 300 is combined in S2
Key pressing, after, latch preset by CP1, since the state latch of CP1 along, until the state latch edge of next CP1,
Run-out key number 0100；When matrix keyboard S1 singly-bound discharges, after, latch preset by CP1, since the state latch of CP1 along,
Until the state latch edge of next CP1, run-out key number 0101；Therefore, it can be seen that when what is identified is matrix keyboard
When effective button operation, the state latch edge of CP1 of the encoder 300 after effective button operation starts, until next CP1
Until state latch edge, output duration is effective key number of a CP1 periodic width.
In embodiment, when matrix keyboard S3 singly-bound is pressed, encoder 300 is pressed in S3 singly-bound, preset by CP1,
After latch, since the state latch of CP1 along, until the state latch edge of next CP1, run-out key number 0010；In the case where connecing
The state latch edge of the CP1 come starts, until S3 singly-bound, which presses maintenance state, to be terminated, after, latch preset by CP1, from the shape of CP1
State latches edge and starts, until the state latch edge of next CP1,300 run-out key number 0011 of encoder；Therefore, it can be seen that
When identification be the maintenance state of matrix keyboard when, encoder 300 export effective key number duration and the maintenance state
Duration be adapted.
When except the state of keyboard or operation being 6 effective keyboard operations described in table 1 and state, encoder
300 output invalid keys number 1111.Effective key number, or output invalid key number are either exported, encoder 300 changes output content
At the time of for CP1 state latch edge；In embodiment, encoder 300 changes rising edge at the time of exporting content for CP1.
The period of CP1 is the scan period of matrix keyboard.The keyboard scan period in 20ms or more, can effectively keep away
The influence of key point disk key jitter；The keyboard scan period in 100ms or less, is unlikely to omit keyboard operation；Therefore, CP1
Period should control in 20~100ms.
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
When effective button operation of keyboard, the state latch edge of CP1 of the encoder 300 after effective button operation starts, until next
Until the state latch edge of a CP1, output duration is effective key number of a CP1 periodic width.Receive the matrix form
The device of keyboard output signal needs to inquire the output of matrix keyboard constantly, obtains key number.The period distances of inquiry must be small
In the period of CP1.
Whether key number of the circuit shown in Fig. 7 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse, the reception device receiving matrix formula for auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 7 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.Delay buffer 601 is made of 4 edge triggered flip flops only with Trigger Function, the touching of 4 edge triggered flip flops
The reception pulse input end that input terminal is delay buffer 601 is sent out, CP1 is connected to；State of the delay buffer 601 in CP1
It latches along progress data latch.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output end of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output end C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is by delay buffering
After the first-level buffer of device 601, signal ratio C3~C0 postpones a CP1 pulse period, and Fig. 8 show the key of the embodiment of the present invention
The waveform correlation schematic diagram that disk effectively operates.It is located at the section T1 of CP1 pulse, matrix keyboard has primary effectively operation, real
Apply example it is effective operation include：S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S1 of S4+S1 combination operation is pressed, S4+
The S2 of S2 combination operation is pressed, S1 singly-bound discharges.On the next state latch edge once effectively operated, i.e. CP1 pulse in Fig. 8
Rising edge after the section T1, coding C3~C0 that encoder 300 exports change；In the section T2, the output of encoder 300 one
Efficient coding C3~C0 of a CP1 pulse period；In T3, T4 and section later, coding C3~C0 that encoder 300 exports is another
Secondary to change and enter maintenance state, which may be that such as S1 singly-bound presses subsequent maintenance state, export invalid key
Number, it is also possible to S3 singly-bound presses subsequent maintenance state, exports effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulse in Fig. 8 schematically illustrates the output of encoder 300 is not become in maintenance state
Change, still change, the D6 pulse is not present in actual circuit.As shown in figure 8, D6 pulse is low level, schematic table
Show that coding C3~C0 that encoder 300 exports is not changed in maintenance state；D6 pulse is high level, schematically illustrates volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 8 reflected is the situation of change of C31~C01, it is clear that
Q6 ratio D6 postpones a CP1 pulse period.Equally, the Q6 pulse is not present in actual circuit.
In Fig. 8, coding C3~C0 that encoder 300 exports is not changed, still changes in maintenance state,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
At logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output end C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 ratio C0 postpone a CP1 pulse period, and therefore, when C0 changes, XOR gate 602 exports 1 CP1 pulse week
The positive pulse of phase width；When C0 is a CP1 pulse period change width signal, XOR gate 602 exports 2 CP1 pulse weeks
The positive pulse of phase width.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 changes respectively, principle with
It is identical to judge whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 output end connect respectively
It is connected to or whether the input terminal of door 606 or door 606 changes for comprehensive descision C0~C3, as long as C0~C3 changes,
Or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D trigger 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuit, using 4 RC circuits respectively to C0
~C3 is postponed；If less than the one CP1 pulse period of the delay time of RC circuit, encoder 300 exports a cycle
Efficient coding C3~C0 when, output efficient coding C3~C0 start and export efficient coding C3~C0 terminate all generation one
The width of keyboard state change pulse, keyboard state change pulse is equal to RC circuit delay time；If when the delay of RC circuit
Between be more than or equal to a CP1 pulse period, then encoder 300 export a cycle efficient coding C3~C0 when, have in output
Effect coding C3~C0 generates a keyboard state change pulse when starting, which is more than or equal to 2 CP1 pulse periods.
It is required that the delay time of RC circuit is no more than 2 CP1 pulse periods, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by full
2 pulse controls that sufficient specific time sequence requires are converted into the status code of same binary length, by the way of Unified coding into
Row processing, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for status code；If necessary to increase
Subtract button operation function and either adjust button operation function, does not need modification keyboard scanning circuit structure, it only need to be according to increase and decrease
State code table afterwards updates encoder 300, re-writes the storage content for updating read-only memory.The invention circuit
Not using microcontrollers such as single-chip microcontroller, ARM, operation program, reliable operation are not had to.
Claims (10)
1. a kind of matrix keyboard reversal process scanning circuit, it is characterised in that：By X row-Y column key-press matrix, row three state buffer,
Column three state buffer, row status register, column-shaped state register group at.
2. matrix keyboard reversal process scanning circuit according to claim 1, it is characterised in that：The row of all key-press matrixs
Line is respectively connected to the output end of row three state buffer, and the alignment of all key-press matrixs is respectively connected to the defeated of column three state buffer
Outlet；All input terminals of row three state buffer and column three state buffer are connected to low level；The line of all key-press matrixs
It is respectively connected to the input terminal of row status register, the alignment of all key-press matrixs is respectively connected to the input of column status register
End；The output end of the row status register and the output end of column status register export N bit keyboard status signal jointly；
The N=X+Y.
3. matrix keyboard reversal process scanning circuit according to claim 2, it is characterised in that：It is controlled and is gone by sampling pulse
Three state buffer replaces enabled effective with column three state buffer.
4. matrix keyboard reversal process scanning circuit according to claim 3, it is characterised in that：Row three state buffer is taking
The low level of sample pulse is enabled effectively, column three state buffer is enabled effective in the high level of sampling pulse；Column status register exists
The rising edge of sampling pulse carries out data latch, and row status register carries out data latch in the failing edge of sampling pulse.
5. matrix keyboard reversal process scanning circuit according to claim 3, it is characterised in that：Row three state buffer is taking
High flat enabled effective, the column three state buffer of the electricity of sample pulse is enabled effective in the low level of sampling pulse；Column status register exists
The failing edge of sampling pulse carries out data latch, and row status register carries out data latch in the rising edge of sampling pulse.
6. matrix keyboard reversal process scanning circuit according to any one of claims 1-5, it is characterised in that：Further include
First shift register, the second shift register, state Code memory, encoder；First shift register, the second displacement
Register, state Code memory synchronize control by scanning pulse and shift pulse.
7. matrix keyboard reversal process scanning circuit according to claim 6, it is characterised in that：First shift LD
Device has the function of the input of N parallel-by-bit, the output of N parallel-by-bit and Serial output；Second shift register has serial input, N
Parallel-by-bit output function；The N parallel-by-bit input terminal of first shift register is connected to N bit keyboard status signal output；
The serial input terminal of second shift register is connected to the serial output terminal of the first shift register；First shift register,
The shift pulse input terminal of two shift registers is connected to shift pulse, and the presetting pulse input terminal of the first shift register connects
It is connected to scanning pulse；
The state Code memory is 2 × N binary registers；The position N data input pin in state Code memory is connected to
The N parallel-by-bit output end of first shift register, in addition N data input pins are connected to the N parallel-by-bit of the second shift register
Output end；The reception pulse input end of the state Code memory is connected to scanning pulse；
The encoder has 2 × N coding input ends, and the coding input end 2 × N is connected to 2 × N of state Code memory
Position data output end.
8. matrix keyboard reversal process scanning circuit according to claim 7, which is characterized in that the scanning pulse, shifting
The timing of digit pulse meets claimed below：Scanning pulse is the Fractional-N frequency signal of shift pulse；Scanning pulse be positive burst pulse or
Negative burst pulse；First shift register, the second shift register are shifted in the rising edge of shift pulse simultaneously, scanning pulse
Positive burst pulse or negative burst pulse be between the rising edge of former and later two shift pulses；Either, first displacement is posted
Storage, the second shift register are shifted in the failing edge of shift pulse simultaneously, the positive burst pulse or negative burst pulse of scanning pulse
Between failing edge in former and later two shift pulses.
9. matrix keyboard reversal process scanning circuit according to claim 8, it is characterised in that：First shift LD
The presetting pulse of device be edge effectively and scanning pulse be positive burst pulse when, it is desirable that the presetting pulse of the first shift register be it is upper
It rises along effective, the reception pulse of state Code memory is that failing edge is effective；The presetting pulse of first shift register is side
When being negative burst pulse along effective and scanning pulse, it is desirable that the presetting pulse of the first shift register is that failing edge is effective, status code
The reception pulse of register is that rising edge is effective；When the presetting pulse of first shift register is that high level is effective, it is desirable that
Scanning pulse is positive burst pulse, and the reception pulse of state Code memory is that failing edge is effective；First shift register it is pre-
When to set pulse be that low level is effective, it is desirable that scanning pulse is negative burst pulse, and the reception pulse of state Code memory has for rising edge
Effect.
10. matrix keyboard reversal process scanning circuit according to claim 9, it is characterised in that：The status code deposit
2 × N position data output end of device exports 2 × N status codes；The status code is by effective status code and invalid state code character
At；The key number of the encoder output is made of effective key number and invalid key number；The effective status code is by effective keyboard operation
Or state generates, encoder inputs the corresponding effectively key number of corresponding output when each effective status code；The invalid state code
It is generated by invalid keyboard operation or state, encoder inputs all corresponding output invalid key number when all invalid state codes；The volume
Code device has M key output ends, and the selection of M value should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
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| CN201810455310.0A CN108880560B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard reversal method scanning circuit |
| CN201610003404.5A CN105680874B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanning circuit and scanning encoding method |
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| CN105680874B (en) | 2018-06-26 |
| CN108880560B (en) | 2022-03-18 |
| CN105680874A (en) | 2016-06-15 |
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