CN108878369A - A kind of compound semiconductor device and preparation method thereof based on epitaxial growth - Google Patents
A kind of compound semiconductor device and preparation method thereof based on epitaxial growth Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
A kind of compound semiconductor device and preparation method thereof based on epitaxial growth, belongs to compound semiconductor device technical field more particularly to a kind of power integrated circuit chip.The chip structure is arranged successively from bottom to top including SOI substrate, SiC epitaxial layer, GaN epitaxial layer, metal electrode.The GaN epitaxial layer can be GaN, AlN, InN and its thin-film material of ternary, quaternary alloy composition；The GaN epitaxial layer can be two or more power unit structures such as HEMT, HBT；The metal electrode is the Ohm contact electrode on power unit structure；The power device is completely isolated by trench isolation process formation lattice-shaped isolation band structure.The highly integrated of power electronic device chip can be achieved in the present invention, and chip-resistance can be effectively reduced, and suppression device parasitic inductance reduces chip size, reduces circuit area and increases design flexibility, the power integrated circuit chip of high reliability is obtained with low cost.
Description
Technical field：
The present invention relates to a kind of compound semiconductor device and preparation method thereof based on epitaxial growth belongs to compound half
Conductor device technical field.
Background technique
Modern power integrated circuit just gradually develops to high-power, low-power consumption, high reliability, high integration direction, half-and-half
More stringent requirements are proposed for conductor substrate material and device performance.
With the diminution of device feature size and the raising of circuit level, silicon-on-insulator (SOI, Silicon On
Insulator high speed, low-power consumption advantage) is obvious.Dielectric buried layer between top layer silicon and backing bottom, can be by the total parasitic electricity of substrate
Appearance is effectively reduced 15%~30%, and material carries on the back the disappearance of substrate current, can effectively reduce device creepage, minimum to reach 1pA/ μ
M realizes lower power consumption nearly 30%~70% under identity unit performance.Moreover, the mutual conductance also with higher of SOI material, subtract
Weak channelling effect and more steep sub-threshold slope, device performance are substantially better than body silicon device.
Compared with first generation semiconductor material Si and the second generation semiconductor material GaAs, InP, GaN semiconductor material conduct
Third generation semiconductor material, with direct band gap, forbidden band is wider, electron saturation velocities and drift speed are bigger, breakdown voltage
It is higher, chemical property is more stable, high temperature resistant, the characteristics such as corrosion-resistant, make high electron mobility transistor, bipolar transistor extensively
The microelectronic components such as pipe, field effect transistor are highly suitable for working under high frequency, high temperature, high-power and adverse circumstances.
SOI substrate GaN base material, thinner than epitaxial layer using top layer silicon flexible substrate on SOI, extension island and top layer silicon are soft
Property substrate between atom active force it is weak, during the growth process easily top layer silicon face generate " sliding " property, can substantially reduce
Dislocation density, growth stress in epitaxial layer growth process, obtain the high epitaxial structure layer of crystal quality, production high frequency, high temperature,
HIGH-POWERED MICROWAVES IC chip.
In the research for carrying out GaN base power device, MMIC circuit and module, realize Highgrade integration, high reliability and
Low manufacturing cost is particularly important.Motion patent document CN 200710003898.8 as solution is by substrate
Different size of recess portion is etched, selective assembly is carried out with the IC chip for being suitable for recess portion, forms IC chip, provide
The semiconductor devices and its manufacturing method of a kind of high universalizable, but it need to carry out IC one by one to the recess portion on substrate and fill
Assembly, the more dilatory complexity of manufacturing process, and this method are bonding pattern；Motion patent document CN 201510822308.9 is mentioned
A kind of Si base GaN Bi-HEMT chip and preparation method thereof has been supplied, highly integrated epitaxial structure effectively reduces chip-resistance,
The power added efficiency under low-power mode is increased, but it uses GaN HBT epitaxial layer to be located on GaN HEMT epitaxial layer
Structure, will cause HBT power device with very big ghost effect, chip reliability caused to reduce.
The present invention provides a kind of compound semiconductor devices based on epitaxial growth, particularly provide a kind of based on SOI
GaN base power integrated circuit chip of substrate and preparation method thereof passes through the substrates such as the SOI of selection low cost, extension high quality
GaN epitaxial layer realize highly integrated, high reliability, low manufacturing cost MMIC circuit in conjunction with trench isolation process.
Summary of the invention：
It is an object of the invention to overcome the deficiencies in the prior art and defect, provide a kind of compound based on epitaxial growth
Semiconductor devices, especially provides a kind of based on substrate GaN-based power integrated circuit chips such as SOI and preparation method thereof, can have
Effect reduces chip-resistance, and suppression device parasitic inductance reduces chip size, reduces circuit area and increases design flexibility, with
Low cost obtains the power integrated circuit chip of high reliability., the extension thinner than epitaxial layer using SOI top material layer silicon flexible substrate
Atom active force is weak between island and top layer silicon flexible substrate, is also easy to produce during the growth process " sliding phenomenon ", and using outside SiC
Prolong layer as buffer layer, avoids lattice mismatch bring defect between GaN epitaxial layer and substrate, while passing through trench isolation process
It forms lattice-shaped isolation band structure the progress of different capacity device architecture is completely isolated, chip is improved while realizing highly integrated
Reliability reduce manufacturing cost.
To achieve the above object, the present invention provides a kind of power integrated circuit chip based on SOI substrate GaN base, special
Sign is to include the SOI substrate being arranged successively from below to up, SiC epitaxial layer, GaN device structure epitaxial layers, metal electrode.It is described
GaN device structure epitaxial layers can be GaN, AlN, InN and its thin-film material of ternary, quaternary alloy composition；The GaN epitaxial layer
Upper is one or more power unit structures such as HEMT, HBT；The metal electrode is power device on GaN device structure epitaxial layers
Ohm contact electrode in part structure；Forming lattice-shaped isolation strip by etching groove on the GaN device structure epitaxial layers makes
Different capacity device architecture is arranged in level-crossing.
The present invention provides a kind of compound semiconductor device preparation method based on epitaxial growth, which is characterized in that the party
Method includes step in detail below：
S1 choose needed for semi-insulating substrate (1), semi-insulating substrate (1) its can for Si substrate, SOI substrate, SiC substrate,
GeSi substrate, GaAs substrate, GaN substrate or quartz substrate, glass substrate；It is preferred that SOI substrate, wherein 101 be backing bottom,
102 it is intermediate medium buried layer, 103 is top layer silicon；
S2 is sequentially prepared SiC epitaxial layer (2), AlN buffer layer (3), GaN buffer layer on the semi-insulating substrate (1)
(4)；
S3 is using dry method ICP lithographic technique to having grown SiC epitaxial layer (2), AlN buffer layer (3), GaN buffer layer (4)
Semi-insulating substrate (1) carries out groove (18) etching from top to bottom and forms lattice-shaped isolation strip (B), etching depth to semi-insulating substrate
(1)；It is preferred that etching into the dielectric buried layer (102) of SOI substrate when semi-insulating substrate is SOI substrate；
S4 in above-mentioned steps S3 semi-insulating substrate (1), by channel design lattice-shaped isolation strip (B) by it is to be prepared not
Structure with chip is kept apart, and is formed grid, is constituted the extension window region of different chips；Then in the extension window of different chips
It distinguishes step and carries out different capacity device architecture outer layer growth, spacing (the i.e. lattice-shaped isolation strip between adjacent extension window region
Width) be 20 μm~100 μm, final difference chip structures are alternatively arranged in level-crossing；
It is corresponding in the extension window region of all different chips when substep carries out different capacity device architecture outer layer growth
Using PECVD deposition one layer mask (19) on GaN buffer layer (4)；Then at the first power unit structure A to be prepared pair
The extension window region at grid is answered to utilize the mask (19) of ICP dry etching selective etch substrate surface deposition to GaN buffering
Layer (4) exposes, and then carries out the first power unit structure A outer layer growth；The first power unit structure A extension is prepared
A layer mask (19) are deposited on the first power unit structure A epitaxial layer using PECVD again after layer；Then to be prepared
The extension window region at grid is corresponded at second of power unit structure B utilizes ICP dry etching selective etch substrate surface
The mask (19) of deposition to GaN buffer layer (4) are exposed, and second of power unit structure B outer layer growth is then carried out；It has prepared
Again using PECVD in second of power unit structure B outer layer growth after second of power unit structure B outer layer growth
One layer mask of upper deposition (19), and so on, until having prepared the epitaxial layer of required all different capacity device architectures；Then
It is etched using dry method ICP, removes the mask (19) of the epi-layer surface deposition of all different capacity device architectures, carry out chip electricity
Pole preparation.
It is preferred that the extension window region in the different chips prepares different capacity device architecture unit, such as different capacity
Device architecture unit is HEMT, HBT structure unit, and arrangement mode is alternatively arranged for level-crossing, between adjacent structural units
Spacing be 20 μm~100 μm；It is characterized in that, preparation method includes step in detail below：
1) when preparing different capacity device architecture, in the corresponding GaN buffer layer of extension window region of all different chips
(4) used on PECVD deposition thickness for~2 μm of mask (19), the mask can be SiO2Or SiNxFilm；
2) it is deposited in the extension window region area (L1) of HEMT to be prepared using ICP dry etching selective etch substrate surface
Mask (19) to GaN buffer layer (4) expose, carry out HEMT chip epitaxial layer structure growth；In HEMT extension window region (L1)
Place's growth HEMT chip structure layer, the HEMT chip structure, which is characterized in that successively grown on the GaN buffer layer (4)
GaN channel layer (5), AlGaN potential barrier (6), GaN contact layer (7)；
3) after the growth of HEMT chip structure layer, the deposition mas (19) at HEMT chip extension window (L1), to protect
Protect HEMT chip structure layer；
4) ICP dry etching selective etch substrate table then is utilized in the extension window region area (L2) of HBT to be prepared again
The mask (19) of face deposition to GaN buffer layer (4) are exposed, and it is raw that HBT chip epitaxial layer is carried out at the extension window region (L2) of HBT
Long, HBT chip epitaxial layer is that GaN lower collector layer (8), GaN collector layer (9), GaN are successively grown on GaN buffer layer (4)
Base layer (10), GaN emitter layer (11)；
5) it after the completion of all power device chip epitaxial layer structures are grown, is etched using dry method ICP, removes all extensions
The mask (19) of window surface deposition, carries out chip electrode preparation；GaN source electrode (13), GaN are prepared on GaN contact layer (7)
Drain electrode (14), and GaN gate electrode (12) are prepared on GaN contact layer (7) or GaN channel layer (5)；In GaN lower collector layer
(8) GaN lower collector electrode (15) are prepared on, prepare base layer electrode (16), in GaN emitter layer in GaN base pole layer (10)
(11) emitter electrode (17) are prepared；Complete the Ohm contact electrode preparation on each cellular construction.
Carry out GaN buffer layer (4) growth on the semi-insulating substrate (1), GaN buffer layer (4), which can be replaced, to be removed
Other iii-vs outside GaN material, Group II-VI semiconductor material, such as GaN material, GaAs material, InP material, life
Length can pass through the modes such as MBE, MOCVD, UHV-CVD；
Selective etch technology is used on substrate layer, is carried out channel (18) etching and is formed lattice-shaped isolation strip (B), makes not
It is grown in not homepitaxy window region with the isolation of chip epitaxial layer structure, realizes the one or more power of epitaxial growth on same substrate
Device structure layer；The lattice-shaped isolation strip (B) can be by modes such as etching channel, ion implantings, and isolation strip depth extremely serves as a contrast
Bottom (1) surface；
The substrate (1) upper epitaxial layer (4) in carry out semiconductor device structure preparation, can for MOSFET,
Two or more in the IC chips structure such as MISFET, HBT, HEMT, LDMOS, BiCMOS；
In different chip epitaxial layer growth process, in conjunction with chip deposition and lithographic technique to different semiconductor device structures
Carry out insulation blocking growth；Mask used in the insulation blocking (19) can be SiO2、SiNx, organic resin etc. is non-conductive and is easy to
The material of deposition and removing, will not impact power electronic device performance；
After the completion of the growth of all power device chip epitaxial layer structures, the Ohmic contact electricity on each cellular construction is completed
Pole preparation；The metal electrode material is one of Ti/Al/Ti/Au/Ni/Au, Ni/Au；
The present invention has the following advantages that：
In method provided by the invention, using epitaxy technology and chip deposition technique, lithographic technique, channel isolation technique skill
Art combines, on the same substrate extension different capacity electronic device structure layer, and it is parasitic that chip-resistance, suppression device is effectively reduced
Inductance reduces chip size, reduces circuit area and increases design flexibility, realize highly integrated, high reliability, low manufacture at
This smart-power IC chip.
Detailed description of the invention：
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, wherein：
Attached drawing 1 is the overlooking structure diagram in the present invention after substrate deposition mask；
Attached drawing 2 is overlooking structure diagram when growing chip epitaxial layer at a certain extension window (L1) area in the present invention；
Attached drawing 3 is a kind of plan structure signal of the power integrated circuit chip based on SOI substrate GaN base in the present invention
Figure；
Attached drawing 4 is substrate epitaxial layer sectional structure chart in the present invention；
Attached drawing 5 is the schematic diagram of the section structure of selective channel etching in the present invention；
Attached drawing 6 is the schematic diagram of the section structure in the present invention after substrate deposition mask；
The schematic diagram of the section structure when HEMT chip epitaxial layer at the area extension window (L1) is grown in 7 present invention of attached drawing；
Attached drawing 8 is the schematic diagram of the section structure when growing HBT chip epitaxial layer at the area extension window (L2) in the present invention；
Attached drawing 9 is a kind of cross-section structure signal of the power integrated circuit chip based on SOI substrate GaN base in the present invention
Figure；
Attached drawing 10 is a kind of highly integrated, high reliability, low manufacturing cost compound semiconductor device in the present invention
The flow chart of preparation method.
Semi-insulating substrate 1, SiC epitaxial layer 2, AlN buffer layer 3, GaN buffer layer 4, GaN HEMT channel layer 5, GaN HEMT
Current collection layer pole 8 under barrier layer 6, GaN HEMT contact layer 7, GaN HBT, GaN HBT collector layer 9, GaN HBT base layer 10,
GaN HBT emitter layer 11, GaN HEMT gate electrode 12, GaN HEMT source electrode 13, GaN HEMT drain electrode 14, GaN HBT
Lower collector layer electrode (15), GaN HBT base layer electrode 16, GaN HBT emitter layer electrode 17 and isolation channel 18 are covered
Mould 19, backing bottom 101, intermediate buried layer 102, top layer silicon 103.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses a kind of compound semiconductor device and preparation method thereof based on epitaxial growth, and a kind of based on SOI lining
The power integrated circuit chip and preparation method thereof of bottom GaN base.It should be appreciated that specific embodiment described herein is only to solve
The present invention is released, the ordinary person of technical field can carry out any type of change in the case where not departing from present inventive concept and its range
Change, belongs to the scope of the present invention.
It is a kind of the schematic diagram of the section structure of power integrated circuit chip based on SOI substrate GaN base shown in attached drawing 1-9,
Attached drawing 3 be its overlooking structure diagram, the chip include semi-insulating substrate (1) preferably SOI substrate (including：Backing bottom 101,
Intermediate buried layer 102, top layer silicon 103), SiC epitaxial layer (2), AlN buffer layer (3), GaN buffer layer (4), GaN HEMT channel layer
(5), current collection layer pole (8), GaN HBT collector layer under GaN HEMT barrier layer (6), GaN HEMT contact layer (7), GaN HBT
(9), GaN HBT base layer (10), GaN HBT emitter layer (11), GaN HEMT gate electrode (12), GaN HEMT source electrode
(13), GaN HEMT drain electrode (14), GaN HBT lower collector layer electrode (15), GaN HBT base layer electrode (16), GaN
HBT emitter layer electrode (17) and isolation channel (18)；It is SOI substrate (101,102,103), outside SiC wherein shown in attached drawing 4
Prolong the substrate layer of layer (2), AlN buffer layer (3), GaN buffer layer (4) composition；Shown in attached drawing 5, is etched and be isolated using lithographic technique
Channel (18), etching depth to SOI substrate buried layer (102)；The substrate layer that attached drawing 6 show after forming lattice-shaped isolation strip is adopted
Protection mask (19) is deposited with chip deposition technique, overlooking structure diagram is as shown in Fig. 1；Attached drawing 7 is growth HEMT function
The schematic diagram of the section structure when rate device structure layer, using the deposition mas in lithographic technique removing area HEMT extension window (L1)
(19), outer layer growth is carried out, overlooking structure diagram is as shown in Fig. 2；Attached drawing 8 is growth HBT power unit structure layer
When the schematic diagram of the section structure, will growth complete HEMT epitaxial layer structure using chip deposition technique deposition protection mask
(19), using the deposition mas (19) in lithographic technique removing area HBT extension window (L2), outer layer growth is carried out, overlooks knot
Structure schematic diagram is as shown in Fig. 2；In particular, mask (19) non-one kind that preferably not homepitaxy window region is deposited is covered
Mould；After all power device epitaxial structure layer growths, using the mask of lift-off technology removal all surface deposition, Europe is carried out
Nurse contacts electrode preparation, and GaN HEMT source electrode (13), GaN HEMT drain electrode (14) preparation are in GaN HEMT contact layer (7)
On, and the epitaxial layer of GaN HEMT contact layer (7) above is removed by lithographic technique, GaN HEMT gate electrode (12) preparation exists
On GaN HEMT contact layer (7) or GaN HEMT channel layer (5), and the GaN HEMT contact layer (7) or GaN HEMT channel layer
(5) epitaxial layer above is removed by lithographic technique, and GaN HBT lower collector electrode (15) is prepared in GaN HBT lower collector
On layer (8), and the epitaxial layer of GaN HBT lower collector layer (8) above is removed by lithographic technique, GaN HBT base layer electrode
(16) preparation is in GaN HBT base layer (10), and the epitaxial layer of GaN HBT base layer (10) above is gone by lithographic technique
It removing, GaN HBT emitter layer electrode (17) is prepared on GaN HBT emitter layer (11), and on GaN HBT emitter layer (11)
The epitaxial layer in face is removed by lithographic technique.
The present invention provides a kind of preparation methods of compound semiconductor device based on epitaxial growth, referring to Fig. 10,
Include the following steps：
Step 1：Select a kind of semi-insulating substrate, the substrate can for Si substrate, SOI substrate, SiC substrate, GeSi substrate,
GaAs substrate, GaN substrate or quartz substrate, glass substrate；After deionized water repeated flushing 10 times, be placed in hydrochloric acid,
Mixed solution (the HCl of hydrogen peroxide:H2O2:H2O=7:1:1), heating water bath 5 minutes at 80 DEG C.Take out the substrate, spend from
Sub- water repeated flushing 10 times is placed in the mixed solution (H of sulfuric acid, hydrogen peroxide2SO4:H2O2:H2O=4:1:1), 80 DEG C of water-baths add
Heat 5 minutes after taking out the substrate, with deionized water repeated flushing 10 times, recycles ultrasonic cleaning technique, cleans the lining
Bottom is finally taken out the substrate, is dried with nitrogen；
Step 2:After the semi-insulating substrate is cleaned according to step 1, it is put into MBE, MOCVD, UHV- according to demand
The reaction chamber of the equipment such as CVD, CVD carries out iii-v, Group II-VI semiconductor material, such as GaN material, GaAs material, InP
The growth of material homepitaxy layer.When carrying out the iii-v, Group II-VI semiconductor material outer layer growth, in line with reduce substrate with
The principle of lattice mismatch and thermal mismatching between epitaxial layer introduces corresponding buffer layer, such as high-temperature AlN, low temperature AI N, Si；
When growing the GaN epitaxial layer, in MOCVD reaction chamber, control reaction temperature is 1050~1750 DEG C, pressure
For 50~200mbar, the big SiH of reaction source450~300sccm, C3H830~100sccm, originally by the preparation of control growth conditions
Levy SiC epitaxial layer；SiC epitaxial layer growth after the completion of, control reaction chamber temperature be 1000~1300 DEG C, pressure be 50~
300mbar, reaction source are 20~100sccm of TMGa, TMAl 20~100sccm and NH38000~20000sccm passes through control
Growth conditions processed prepares intrinsic AlN buffer layer and GaN buffer layer；
When growing the GaAs epitaxial layer, in UHV-CVD reaction chamber, maintain vacuum (4~5) × 10-6Pa, control are anti-
750 DEG C~850 DEG C of room temperature are answered, with Si2H6(disilane) is source, grows Si buffer layer；After Si buffer growth, control
450~600 DEG C of reaction chamber temperature, Si2H6(disilane) and GeH4(germane) is source, grows GexSi(1-x)Gradual transition layer；
GexSi(1-x)After the completion of the growth of gradual transition layer, in MOCVD reaction chamber, 500~850 DEG C of reaction temperature are controlled, with carrier gas
H2In 10% TMGa (trimethyl gallium), AsH3(arsine) is source, and flow is respectively TMGa 60sccm~100sccm and AsH3
500sccm~650sccm carries out GaAs buffer growth by control growth conditions；Or in GexSi(1-x)Gradual transition layer is raw
After the completion of length, in MBE reaction chamber, 500~700 DEG C of reaction temperature are controlled, vacuum pressure 3 × 109Torr, with As, Ga steaming
Vapour is source, and the growth of GaAs buffer layer is carried out by control growth conditions；
When growing the InP epitaxial layer, using CVD method, the Au film of thermal evaporation 1nm thickness first in semi-insulating substrate,
Suitable high-purity InP powder is placed in ceramic boat and is placed in quartz ampoule center in CVD reaction chamber, is 100sccm with flow
High-purity H2For carrier gas, using InP steam as source, setting reaction temperature is 750~850 DEG C, keeps the temperature 1h, is deposited in substrate surface
InP nanostructure, about 3~5 μm of thickness.
Step 3：After completing iii-v, Group II-VI semiconductor material outer layer growth according to step 2, etching skill is utilized
The substrate layer that art completes step 2 carries out isolation channel etching, it is intended to utilize lattice-shaped isolation strip by different epitaxial structure devices
Part is completely isolated；The lithographic technique can be the technologies such as dry method ICP etching, energetic ion injection, etching depth to semi-insulating lining
Bottom surface；
Step 4：After completing channel isolation described in step 3, chip is carried out to the epitaxial wafer for having formed lattice-shaped isolation strip
Deposition technique deposits certain thickness protection mask, it is intended to which protection is when a certain power unit structure outer layer growth outside other
It is unaffected to prolong window region；The mask can be SiO2、SiNxOr organic resin etc. is non-conductive and is easy to the material of deposition and removing
Material, it is pointed out that non-one kind of mask used in different capacity device architecture epitaxial region realizes deposition technique and lift-off technology not
Conflict and all masking regimes that does not influence and power electronic device performance will not be impacted；
Deposit the SiO2When mask, channel isolation back substrate described in step 3 will be completed and be put into PECVD reaction chamber, controlled
Reaction temperature processed is 300~350 DEG C, with N2O is source, and flow is 1000~1500sccm, deposits 1~2 μ m-thick film；
Deposit the SiNxWhen mask, channel isolation back substrate described in step 3 will be completed and be put into PECVD reaction chamber, controlled
Reaction temperature processed is 200~300 DEG C, with NH3For source, flow is 10~50sccm, deposits 1~2 μ m-thick film；
Step 5：It completes after sinking to the bottom layer surface masked-deposition described in step 4, utilizes deposition technique and lift-off technology phase
In conjunction in extension on piece, homepitaxy window region does not carry out the growth of different capacity device epitaxial structure layer, grows a certain power device
The area structure epitaxial layers Shi Duigai extension window mask carries out removing and exposes substrate layer progress outer layer growth, other extension window regions
It is protected using mask, after the completion of extension window region epitaxial structure layer growth, using deposition technique deposition mas for protecting
Its epitaxial structure is protected, then removing outer layer growth is masked to next extension window region, and so on, complete all extensions
The growth of window region epitaxial structure layer；
When step 2 is grown to GaN buffer layer, different capacity electronic device structure can be HEMT, HBT, setting thereon
HEMT structure extension window region is the area (L1), and the area Ze Chu L1 outer-lining bottom all extension window regions surface deposition protection mask is in extension
The area window L1 controls 1000~1100 DEG C of reaction temperature, and pressure is 60~200mbar, TMGa, TMAl, NH3For source, flow difference
For 40~100scmm, 40~100sccm, 5000~10000sccm, GaN HEMT channel layer, GaN HEMT potential barrier are successively grown
Layer, GaN HEMT contact layer；After the extension area window L1 completes HEMT structure outer layer growth, using PEVCD equipment, control is anti-
Answering temperature is 300~350 DEG C, with N2O is source, and flow is 1000~1500sccm, deposits 1~2 μ m-thick SiO2Mask；It is right later
HBT extension window region L2 carries out epitaxial structures growth, etches the removal area L2 using dry method ICP and protects mask, controls reaction temperature
1000~1100 DEG C, pressure is 60~200mbar, TMGa, TMAl, NH3For source, flow be respectively 40~100sccm, 40~
100sccm, 5000~10000sccm successively grow GaN HBT collector layer, GaN HBT base layer, GaN HBT emitter
Layer；After the extension area window L2 completes HBT structure outer layer growth, using PEVCD equipment, control reaction temperature be 200~
300 DEG C, with NH3For source, flow is 10~50sccm, deposits 1~2 μ m-thick SiNxMask, and using under dry method ICP etching removal
One extension window region protects mask, carries out the growth of corresponding epitaxial structure.
When step 2 is grown to GaAs buffer layer, thereon different capacity electronic device structure can be PHEMT, MOSFET,
It is similarly combined using deposition technique and lift-off technology, carries out different capacity device extension in the not homepitaxy window region of extension on piece
Structure sheaf growth；
When step 2 is grown to InP buffer layer, thereon different capacity electronic device structure can for n-MOS, PHEMT,
HEMT, HBT are similarly combined using deposition technique and lift-off technology, carry out different function in the not homepitaxy window region of extension on piece
The growth of rate device epitaxial structure layer；
Step 6：After outer layer growth described in step 5, lift-off technology, removal substrate surface protection are used to substrate
Mask used carries out Ohm contact electrode preparation to all power unit structures, and utilizes lift-off technology removal production electrode layer
On epitaxial layer, complete the preparation of entire chip.
When step 2 is grown to GaN buffer layer, using lithographic technique, the GaN HEMT and GaN of partial region are removed
The epitaxial layer of HBT chip, by GaN HEMT source electrode, the preparation of GaN HEMT drain electrode on GaN HEMT contact layer, GaN
HEMT gate electrode is prepared on GaN HEMT contact layer or GaN HEMT channel layer, and GaN HBT lower collector electrode is prepared in GaN
On HBT lower collector layer, GaN HBT base layer electrode prepares the GaN HBT emitter layer electrode system in GaN HBT base layer
For on GaN HBT emitter layer；
When step 2 is grown to GaAs buffer layer, using lithographic technique, PHEMT, MOSFET core of partial region are removed
The epitaxial layer of piece, and by Ohm contact electrode preparation on corresponding epitaxial structure layer；
When step 2 is grown to InP buffer layer, using lithographic technique, remove partial region n-MOS, PHEMT,
The epitaxial layer of HEMT, HBT chip, and by Ohm contact electrode preparation on corresponding epitaxial structure layer.
The above, specific implementation only of the invention.Scope of protection of the present invention is not limited thereto, any ripe
Knowing those skilled in the art, various improvements and modifications may be made without departing from the principle of the present invention, this
A little improvement and wetting also should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of compound semiconductor device preparation method based on epitaxial growth, which is characterized in that this method includes following tool
Body step：
S1 chooses required semi-insulating substrate (1)；
S2 is sequentially prepared SiC epitaxial layer (2), AlN buffer layer (3), GaN buffer layer (4) on the semi-insulating substrate (1)；
S3 using dry method ICP lithographic technique to grown SiC epitaxial layer (2), AlN buffer layer (3), GaN buffer layer (4) half absolutely
Edge substrate (1) carries out groove (18) etching from top to bottom and is formed lattice-shaped isolation strip (B), etching depth to semi-insulating substrate (1)；
S4 forms lattice-shaped isolation strip (B) for difference to be prepared in above-mentioned steps S3 semi-insulating substrate (1), through channel etching
The structure of device is kept apart, and different grid extension window regions is formed；Then it is carried out in each grid extension window region substep different
Device architecture outer layer growth, the spacing between adjacent extension window region are 20 μm~100 μm, and final different components structure is in flat
The arrangement of face transpostion interval；
When substep carries out the growth of different components structure epitaxial layers, in all corresponding GaN buffer layers (4) of grid extension window region
It is upper that a layer mask (19) are deposited using PECVD；Then the extension window at grid is corresponded at the first device architecture A to be prepared
Mouth region using ICP dry etching selective etch substrate surface deposition mask (19) to GaN buffer layer (4) expose, then into
Row the first device architecture A outer layer growth；It has prepared after the first device architecture A epitaxial layer again using PECVD the
A layer mask (19) are deposited on a kind of device architecture A epitaxial layer；Then it is corresponded at grid at second of device architecture B to be prepared
Extension window region using ICP dry etching selective etch substrate surface deposition mask (19) to GaN buffer layer (4) reveal
Out, second of device architecture B outer layer growth is then carried out；Second of device architecture B outer layer growth has been prepared to adopt again later
A layer mask (19) are deposited on second of device architecture B outer layer growth with PECVD, and so on, until having prepared institute
The epitaxial layer of all different components structures needed；Then it is etched using dry method ICP, removes the epitaxial layer of all different components structures
The mask (19) of surface deposition, carries out chip electrode preparation.
2. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
In semi-insulating substrate (1) is selected from Si substrate, SOI substrate, SiC substrate, GeSi substrate, GaAs substrate, GaN substrate or quartz
Substrate, glass substrate；It is preferred that SOI substrate, is followed successively by backing bottom, intermediate medium buried layer, top layer silicon from bottom to top.
3. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
When, S3 carries out groove (18) etching, when semi-insulating substrate is SOI substrate, the dielectric buried layer (102) of SOI substrate is etched into.
4. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
Other iii-vs in addition to GaN material, Group II-VI semiconductor material are replaced in, GaN buffer layer (4), are grown through
MBE, MOCVD, UHV-CVD mode.
5. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
In, prepare different components structural unit in the different grid extension window regions, such as different components structural unit be HEMT,
HBT structure unit, arrangement mode are alternatively arranged for level-crossing, and the spacing between adjacent structural units is 20 μm~100 μm；
It is characterized in that, preparation method includes step in detail below：
1) when preparing different components structure, PECVD is used on the corresponding GaN buffer layer (4) of all grid extension window regions
Method deposition thickness isMask (19)；
2) it is covered in the extension window region area (L1) of HEMT to be prepared using what ICP dry etching selective etch substrate surface deposited
Mould (19) to GaN buffer layer (4) are exposed, and the growth of HEMT chip epitaxial layer structure is carried out；It is raw at HEMT extension window region (L1)
Long HEMT chip structure layer, the HEMT chip structure, which is characterized in that successively grow GaN on the GaN buffer layer (4)
Channel layer (5), AlGaN potential barrier (6), GaN contact layer (7)；
3) after the growth of HEMT chip structure layer, the deposition mas (19) at HEMT chip extension window (L1), with protection
HEMT chip structure layer；
4) then heavy using ICP dry etching selective etch substrate surface in the extension window region area (L2) of HBT to be prepared again
Long-pending mask (19) to GaN buffer layer (4) are exposed, and HBT chip outer layer growth is carried out at the extension window region (L2) of HBT,
HBT chip epitaxial layer is that GaN lower collector layer (8), GaN collector layer (9), GaN base are successively grown on GaN buffer layer (4)
Pole layer (10), GaN emitter layer (11)；
5) it after the completion of all device chip epitaxial layer structures are grown, is etched using dry method ICP, removes all extension window surfaces
The mask (19) of deposition carries out chip electrode preparation；GaN source electrode (13), GaN drain electrode are prepared on GaN contact layer (7)
(14), GaN gate electrode (12) and on GaN contact layer (7) or GaN channel layer (5) are prepared；It is made on GaN lower collector layer (8)
Standby GaN lower collector electrode (15) is prepared in GaN base pole layer (10) preparation base layer electrode (16), in GaN emitter layer (11)
Emitter electrode (17)；Complete the Ohm contact electrode preparation on each cellular construction.
6. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
In mask (19) is SiO2、SiNx, one of organic resin or which plant material that is non-conductive and being easy to deposit and remove.
7. a kind of compound semiconductor device preparation method based on epitaxial growth described in accordance with the claim 1, feature exist
In, all power device chip epitaxial layer structures growth after the completion of, complete the Ohm contact electrode system on each cellular construction
It is standby；The metal electrode material is one of Ti/Al/Ti/Au/Ni/Au, Ni/Au.
8. the compound semiconductor device being prepared according to the described in any item methods of claim 1-7.
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| US5567961A (en) * | 1992-08-21 | 1996-10-22 | Hitachi, Ltd. | Semiconductor device |
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| US20140231876A1 (en) * | 2012-06-01 | 2014-08-21 | Win Semiconductors Corp. | pHEMT and HBT integrated epitaxial structure |
| CN105355627A (en) * | 2015-11-23 | 2016-02-24 | 中山德华芯片技术有限公司 | Si-based GaN Bi-HEMT chip and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5051372A (en) * | 1989-04-12 | 1991-09-24 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a semiconductor optoelectric integrated circuit device, having a pin, hemt, and hbt, by selective regrowth |
| US5567961A (en) * | 1992-08-21 | 1996-10-22 | Hitachi, Ltd. | Semiconductor device |
| CN1131819A (en) * | 1994-11-02 | 1996-09-25 | Trw公司 | Method of fabricating monolithic multifunction integrated circuit devices |
| CN1728395A (en) * | 2004-07-26 | 2006-02-01 | 电子科技大学 | Method for producing photoelectric integration circuit in single chip |
| US20140231876A1 (en) * | 2012-06-01 | 2014-08-21 | Win Semiconductors Corp. | pHEMT and HBT integrated epitaxial structure |
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Application publication date: 20181123 |