CN108878294A - Lateral double-diffused transistor and its manufacturing method - Google Patents
Lateral double-diffused transistor and its manufacturing method Download PDFInfo
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- CN108878294A CN108878294A CN201810612805.XA CN201810612805A CN108878294A CN 108878294 A CN108878294 A CN 108878294A CN 201810612805 A CN201810612805 A CN 201810612805A CN 108878294 A CN108878294 A CN 108878294A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 352
- 230000000903 blocking effect Effects 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 21
- 238000000034 method Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of lateral double-diffused transistor and its manufacturing methods, are included among source electrode and drain electrode and form stair-stepping first medium layer, and the first medium layer is relatively thin in close source electrode, thicker close to draining；The first medium layer is formed by more alternating depositions of dielectric layer A and dielectric layer B, to control the step-thickness of the first medium layer.Oxide layer is layered by the present invention using silicon oxynitride layer, it is utilized respectively different etch rate etching oxidation layer and silicon oxynitride layer, keep it mutually unaffected in etching, pass through multiple isotropism and anisotropic etching, to which drift region oxide layer forms the controllable step structure of multistage thickness, so that the zone oxidation layer for the close source electrode that enhancing exhausts is relatively thin, and the grain boundaries oxide layer in limitation off-BV is sufficiently thick, thus high off-BV and low Rdson is obtained simultaneously, it can control the thickness in ladder each stage simultaneously, so that device property is more stable.
Description
Technical field
The present invention relates to technical field of electronic devices, more specifically, being related to a kind of lateral double-diffused transistor and its system
Make method.
Background technique
With the extensive use of lateral double-diffused transistor (LDMOS) in integrated circuits, for the performance requirement of LDMOS
Also higher and higher.In order to obtain higher shutdown breakdown voltage (off-BV) and lower conduction impedance (Rdson), need floating
It moves between area's doping concentration and drift region oxidated layer thickness and does a compromise, to obtain than better suited off-BV and Rdson.
As shown in Figure 1, being the NLDMOS of the prior art, the oxidated layer thickness of entire drift region is consistent.Existing skill
The processing step of art, first in drift region surface deposition oxide layer, is coated as shown in Fig. 2,3,4 and 5 in the oxide layer of drain region
Photoresist protection will be removed at the oxidation film quarter in other regions using anisotropic etching, and deposit is used for shape after then removing photoresist
At the polysilicon of grid, photoresist protection is finally coated above area of grid, carves the crystalline silicon and oxide layer for removing other regions.
In the above-mentioned prior art, since the thickness of drift region oxide layer is consistent, so can not obtain simultaneously compared with
High shutdown breakdown voltage (off-BV) and lower conduction impedance (Rdson), it is necessary to which the two does a compromise.
Summary of the invention
In view of this, the present invention, which provides one kind, can obtain higher shutdown breakdown voltage (off-BV) and lower conducting
The lateral double-diffused transistor and its manufacturing method of impedance (Rdson), it is brilliant for solving lateral double diffusion of the existing technology
Body pipe can not obtain the problem of higher off-BV and lower Rdson simultaneously.
The present invention provides a kind of manufacturing methods of lateral double-diffused transistor, including：It is formed among source electrode and drain electrode
Stair-stepping first medium layer, the first medium layer is relatively thin in close source electrode, thicker close to draining；
The first medium layer is formed by more alternating depositions of dielectric layer A and dielectric layer B, to control the first medium layer
Step-thickness.
Optionally, the manufacturing method of lateral double-diffused transistor, includes the following steps：
Step 1：Successively deposit first medium layer and second dielectric layer on drift region surface, the first medium layer by
Dielectric layer A, dielectric layer B and dielectric layer A are successively deposited, and the thickness of underlying dielectric layers A is at least top dielectric layer A thickness
2 times, glue-line is coated in drain region, using glue-line as blocking, carves the second dielectric layer for removing other regions；
Step 2：Glue-line is removed, using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then will
The dielectric layer B not stopped is etched away；
Step 3：Using isotropic etching will second dielectric layer carve remove first thickness, the isotropic etching with
It silicon face vertical direction and is performed etching with silicon face layer parallel direction；
Step 4：Stopped using second dielectric layer, the top dielectric layer A not stopped all is etched away, will not had
There is the thickness of the underlying dielectric layers A etching top dielectric layer A of blocking, then the dielectric layer B not stopped is etched away；
Step 5：Using isotropic etching will second dielectric layer carve remove second thickness, the isotropic etching with
It silicon face vertical direction and is performed etching with silicon face layer parallel direction；
Step 6：Stopped using second dielectric layer, the top dielectric layer A not stopped all is etched away, will not had
There are the thickness of the underlying dielectric layers A etching top dielectric layer A of blocking, all first medium layers of etching channel region；
Step 7：It carves and removes all second dielectric layer, gate oxide is grown in silicon face, then in first medium layer and grid
Deposit forms the third dielectric layer of grid in oxide layer；
Step 8：It carves using glue-line as blocking in the third dielectric layer applied atop glue-line of area of grid and removes other areas
Third dielectric layer, dielectric layer A and the dielectric layer B in domain.
Optionally, the manufacturing method of lateral double-diffused transistor, includes the following steps：The number of segment of step structure is N, N
More than or equal to 2,
Step 1：First medium layer and second dielectric layer are successively deposited on drift region surface, the first medium layer is by N
A dielectric layer A, N-1 dielectric layer B are successively deposited, and wherein top layer and lowest level are dielectric layer A, are applied in drain region
Glue-line is covered, using glue-line as blocking, carves the second dielectric layer for removing other regions, and remove glue-line；
Step 2：Using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then will not stop
Dielectric layer B etch away；
Step 3：Using isotropic etching will second dielectric layer carve remove certain thickness, the isotropic etching with
It silicon face vertical direction and is performed etching with silicon face layer parallel direction；
Step 4：Step 2 and step 3 carry out N-1 times in turn, so that first medium layer shows N sections of ladder-like knot
Structure；
Step 5：Stopped using second dielectric layer, the top dielectric layer A not stopped is etched away, then will not have
The dielectric layer B of blocking is etched away, all dielectric layer A of etching channel region；
Step 6：It carves and removes all second dielectric layer, gate oxide is grown in silicon face, then in first medium layer and grid
Deposit forms the third dielectric layer of grid in oxide layer；
Step 7：It carves using glue-line as blocking in the dielectric layer B applied atop glue-line of area of grid and removes other regions
Third dielectric layer, dielectric layer A and dielectric layer B.
Optionally, the N is equal to 3, and the first medium layer is by dielectric layer A, dielectric layer B, dielectric layer A, dielectric layer B
It is successively deposited with dielectric layer A.
Optionally, the etching mode used in etch media layer A, it is fast to the etch rate of medium A and to the quarter of medium B
It is slow to lose rate；The etching mode used in etch media layer B, it is fast to the etch rate of medium B and to the etch rate of medium A
Slowly.
Optionally, the dielectric layer A is oxide layer, and the dielectric layer B is silicon oxynitride layer, and the second dielectric layer is nitrogen
SiClx layer, the third dielectric layer are polysilicon layer.
Optionally, the dielectric layer A and dielectric layer B are formed using thermal growth mode.
Optionally, the lateral double-diffused transistor can be N-type or p-type.
The present invention also provides a kind of lateral double-diffused transistors, are fabricated by a kind of manufacturing method of any of the above.
Compared with prior art, the technical solution of the present invention has the following advantages that：The present invention, which is directed to, in the prior art can not
The problem of obtaining higher shutdown breakdown voltage (off-BV) and lower conduction impedance (Rdson) simultaneously, proposes a kind of cross
To double-diffused transistor manufacturing method, oxide layer is layered using silicon oxynitride layer, is utilized respectively different etch rates
Etching oxidation layer and silicon oxynitride layer keep it mutually unaffected in etching, by utilizing multiple isotropism and each to different
Property etching, so that drift region oxide layer forms the controllable step structure of multistage thickness, so that the close source electrode that enhancing exhausts
Zone oxidation layer is relatively thin, and the grain boundaries oxide layer in limitation off-BV is sufficiently thick, thus obtains high off- simultaneously
BV and low Rdson, while can control the thickness in ladder each stage, so that device property is more stable.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of prior art N-type transverse direction double-diffused transistor；
Fig. 2 is the schematic diagram of the deposited oxide layer on the surface of drift region in the prior art；
Fig. 3 is to coat the schematic diagram for removing other zone oxidation layers at glue-line protection quarter in drain region in the prior art；
Fig. 4 is that deposit forms the schematic diagram of the polysilicon of grid in oxide layer after removing glue-line in the prior art；
Fig. 5 is to coat glue-line protection on area of grid in the prior art to carve showing except other region polysilicons and oxide layer
It is intended to；
Fig. 6 is the structural schematic diagram of N-type transverse direction double-diffused transistor embodiment one of the present invention；
Fig. 7 is that the embodiment of the present invention one deposited oxide layer, silicon oxynitride layer and silicon nitride layer on the surface of drift region show
It is intended to；
Fig. 8 is the embodiment of the present invention one in drain region coating glue-line protection, carves and removes other region silicon nitride layers, and etches
Fall the schematic diagram of no barrier zones oxide layer and silicon oxynitride layer；
Fig. 9 is the one certain thickness schematic diagram of isotropic etching silicon nitride layer of the embodiment of the present invention；
Figure 10 is the embodiment of the present invention one using silicon nitride layer as blocking, and anisotropic etching does not have the oxygen of barrier zones
Change layer, thickness is equal to the schematic diagram of upper layer oxidated layer thickness；
Figure 11 is the embodiment of the present invention one using silicon nitride layer as blocking, and anisotropic etching falls not no barrier zones
The schematic diagram of silicon oxynitride layer；
Figure 12 is the one certain thickness schematic diagram of isotropic etching silicon nitride layer of the embodiment of the present invention；
Figure 13 is that one anisotropic etching of the embodiment of the present invention does not have the oxide layer of barrier zones, and thickness is equal to upper layer oxygen
Change thickness degree, and carves the schematic diagram of the oxide layer except channel region；
Figure 14 is the schematic diagram that the embodiment of the present invention one strips all silicon nitride layers；
Figure 15 is that the embodiment of the present invention one coats glue-line protection quarter except other region polysilicons, oxide layer on area of grid
With the schematic diagram of silicon oxynitride layer；
Figure 16 is the structural schematic diagram of N-type transverse direction double-diffused transistor embodiment two of the present invention；
Figure 17 is that the embodiment of the present invention two deposited oxide layer, silicon oxynitride layer and silicon nitride layer on the surface of drift region show
It is intended to；
Figure 18 is the embodiment of the present invention two in drain region coating glue-line protection, carves and removes other region silicon nitride layers, and
Etch away the schematic diagram of no barrier zones oxide layer and silicon oxynitride layer；
Figure 19 is the two certain thickness schematic diagram of isotropic etching silicon nitride layer of the embodiment of the present invention；
Figure 20 is the embodiment of the present invention two using silicon nitride layer as blocking, and anisotropic etching falls not no barrier zones
The schematic diagram of oxide layer and silicon oxynitride layer；
Figure 21 is the two certain thickness schematic diagram of isotropic etching silicon nitride layer of the embodiment of the present invention；
Figure 22 is the embodiment of the present invention two using silicon nitride layer as blocking, and anisotropic etching falls not no barrier zones
Oxide layer and silicon oxynitride layer, and carve the schematic diagram of the oxide layer except channel region；
Figure 23 is the schematic diagram that the embodiment of the present invention two strips all silicon nitride layers；
Figure 24 is that the embodiment of the present invention two coats glue-line protection quarter except other region polysilicons, oxide layer on area of grid
With the schematic diagram of silicon oxynitride layer.
Specific embodiment
The preferred embodiment of the present invention is described in detail below in conjunction with attached drawing, but the present invention is not restricted to these
Embodiment.The present invention covers any substitution made in the spirit and scope of the present invention, modification, equivalent method and scheme.
In order to make the public have thorough understanding to the present invention, it is described in detail in the following preferred embodiment of the present invention specific
Details, and the present invention can also be understood completely in description without these details for a person skilled in the art.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It should be noted that attached drawing is adopted
With more simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.
The present invention proposes a kind of manufacturing method of lateral double-diffused transistor, including：Rank is formed among source electrode and drain electrode
The first medium layer of scalariform, the first medium layer is relatively thin in close source electrode, thicker close to draining；
The first medium layer is formed by more alternating depositions of dielectric layer A and dielectric layer B, to control the first medium layer
Step-thickness.
In example 1 and example 2, dielectric layer A is oxide layer, and dielectric layer B is silicon oxynitride layer, uses nitrogen oxidation
Silicon layer can separate oxide layer, can control first medium layer in the thickness of each ladder section, so that device property is more
Add stabilization.
Material for simplicity and economy, the thickness of some section for the ladder that can partially control, without controlling ladder
All sections of thickness.The embodiment one of N-type transverse direction double-diffused transistor of the present invention as shown in Figure 6, it can be seen that drift region oxygen
Change layer in total there are three types of thickness, the upper thickness of ladder is equal to the thickness of top dielectric layer A, i.e., only controls the thickness of this section of ladder
Degree.
The manufacture of the N-type transverse direction double-diffused transistor of the embodiment one includes the following steps：
1) trap well, drift region N-drift and silicon zoneofoxidation Locos are formed according to common process；
2) as shown in fig. 7, successively depositing first medium layer and second dielectric layer, the first medium on drift region surface
Layer is successively deposited by dielectric layer A, dielectric layer B and dielectric layer A, and it is thick that the thickness of underlying dielectric layers A is at least top dielectric layer A
2 times of degree；
3) as shown in figure 8, being carved using glue-line as blocking except other regions in drain region coating photoresist protection
Second dielectric layer.
Photoresist is removed, and using second dielectric layer as blocking, the dielectric layer A anisotropic etching that will do not stop
Fall.Here in etch media layer A, the etching side that the etch rate to medium A is very fast and slower to medium B etch rate is selected
Formula, so that can be parked on medium B layer after dielectric layer A has been etched.
Again using using second dielectric layer as blocking, the dielectric layer B anisotropic etching not stopped is fallen.Here
In etch media layer B, the etching mode that the etch rate to medium B is very fast and slower to medium A etch rate is selected, so that
After dielectric layer B has been etched, it can be parked on medium A layer.
Non-interfering principle is as above when the present invention etches medium A and medium B during remaining, repeats no more.
4) first thickness is removed as shown in figure 9, carving second dielectric layer using isotropic etching, isotropic etching is enabling
While second dielectric layer is longitudinally thinning, laterally can also it bounce back.
5) as shown in Figure 10, stopped using second dielectric layer, the top dielectric layer A not stopped all is etched
Fall, by the thickness of the underlying dielectric layers A not stopped etching top dielectric layer A.
6) as shown in figure 11, stopped using second dielectric layer, the dielectric layer B not stopped is etched away.
7) isotropic etching as shown in figure 12, is utilized again, second dielectric layer is carved and removes second thickness, and isotropism is carved
Erosion laterally can also bounce back while enabling second dielectric layer longitudinally thinning.
8) as shown in figure 13, stopped using second dielectric layer, the top dielectric layer A not stopped all is etched
Fall, by the thickness of the underlying dielectric layers A not stopped etching top dielectric layer A, all dielectric layer A of etching channel region guarantee
LDMOS channel region does not remain dielectric layer A.
9) as shown in figure 14, second dielectric layer is all carved and is removed.
10) gate oxide as shown in figure 15, is grown in silicon face, is then deposited above first medium layer and gate oxide
One layer of third dielectric layer to form gate MOS gate；
Photoresist is coated on area of grid third dielectric layer, carves the third dielectric layer for removing other regions, while utilizing light
Third dielectric layer, dielectric layer A and the dielectric layer B for removing other regions are carved in the protection of photoresist and third dielectric layer.
In example 1, third dielectric layer is polysilicon layer POLY.
When drift region first medium layer is thicker, locos loss amount is too big to prevent in etching process, needs additionally to increase
Reticle removes unwanted drift region first medium layer to carve.
11) Figure 15 and then source and drain and last part technology step according to routine, form completed device knot as shown in FIG. 6
Structure.
Wherein, in the embodiment of the present invention one and embodiment two, first medium layer is by dielectric layer A and dielectric layer B more times
Alternating deposition is formed, and dielectric layer A is oxide layer, and dielectric layer B is silicon oxynitride layer, and second dielectric layer is silicon nitride layer, and third is situated between
Matter layer is polysilicon layer, is not being repeated later.But the present invention is not limited this, can also be by using other similar material respectively
Material substitutes above-mentioned dielectric layer.
It, can be with strict control first medium layer in each ladder section in occasion higher for device property stability requirement
Thickness.The embodiment two of N-type transverse direction double-diffused transistor of the present invention as shown in figure 16, it can be seen that drift region oxide layer is in total
There are three types of thickness, the upper thickness of ladder is equal to the thickness of top dielectric layer A and top dielectric layer B, the intima-media thickness etc. of ladder
In the thickness of middle layer dielectric layer A and underlying dielectric layers B, the lower thickness of ladder is equal to the thickness of underlying dielectric layers A, i.e. control rank
The thickness in each terraced stage.
The manufacture of N-type transverse direction double-diffused transistor shown in embodiment two includes the following steps：
1) trap well, drift region N-drift and silicon zoneofoxidation Locos are formed according to common process；
2) first medium layer and second dielectric layer successively as shown in figure 17, are deposited on drift region surface, described first is situated between
Matter layer is successively deposited by dielectric layer A, dielectric layer B, dielectric layer A, dielectric layer B and dielectric layer A；
As shown in figure 18, glue-line is coated in drain region, using glue-line as blocking, carves the second medium for removing other regions
Layer, and except removal glue-line；
3) as shown in figure 18, using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then will not have
There is the dielectric layer B of blocking to etch away：
4) as shown in figure 19, second dielectric layer is carved using isotropic etching and removes first thickness, the isotropism is carved
Erosion is performed etching with silicon face vertical direction and with silicon face layer parallel direction；
5) as shown in figure 20, using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then will not have
There is the dielectric layer B of blocking to etch away；
6) as shown in figure 21, second dielectric layer is carved using isotropic etching and removes second thickness, the isotropism is carved
Erosion is performed etching with silicon face vertical direction and with silicon face layer parallel direction；
7) as shown in figure 22, stopped using second dielectric layer, the top dielectric layer A not stopped is etched away, then
The dielectric layer B not stopped is etched away, all dielectric layer A of etching channel region guarantee that LDMOS channel region does not remain medium
Layer A.
8) as shown in figure 23, second dielectric layer is all carved and is removed.
9) gate oxide is grown in silicon face, one layer is then deposited above first medium layer and gate oxide to be formed
The third dielectric layer of gate MOS gate.
10) photoresist as shown in figure 24, is coated on area of grid third dielectric layer, on the dielectric layer B of area of grid
Face coats glue-line, using glue-line as blocking, carves third dielectric layer, dielectric layer A and the dielectric layer B for removing other regions.
When drift region first medium layer is thicker, locos loss amount is too big to prevent in etching process, needs additionally to increase
Reticle removes unwanted drift region first medium layer to carve.
11) Figure 24 and then source and drain and last part technology step according to routine, form completed device knot as shown in Figure 2
Structure.
The above process is that oxide layer is divided into three sections, is only one embodiment of the present of invention, and oxide layer may be
Any multistage different-thickness, forms stair-stepping oxide layer among source electrode and drain electrode and is within the scope of the invention.
In implementation process, the number of segment of step structure is N (N is more than or equal to 2), then the first medium layer is by N number of
A, N-1 dielectric layer B of dielectric layer are successively deposited, and wherein top layer and lowest level are dielectric layer A, carry out step 3), 4)
Number be N-1 times, in above-described embodiment two, N=3 then carries out step 3 and step 4 twice.
The embodiment two of first thickness and second thickness in embodiment one and to(for) the etching of second dielectric layer can be identical,
It can also be different.
In the above process, it is equally applicable by taking NLDMOS as an example, but for PLDMOS in the present invention.
The drift region NLDMOS in the present invention is the oxide layer and silicon oxynitride layer of deposit, for thermally grown or other modes
The oxide layer and silicon oxynitride layer of formation are equally applicable.
Although embodiment is separately illustrated and is illustrated above, it is related to the common technology in part, in ordinary skill
Personnel apparently, can be replaced and integrate between the embodiments, be related to one of embodiment and the content recorded is not known, then
It can refer to another embodiment on the books.
Embodiments described above does not constitute the restriction to the technical solution protection scope.It is any in above-mentioned implementation
Made modifications, equivalent substitutions and improvements etc., should be included in the protection model of the technical solution within the spirit and principle of mode
Within enclosing.
Claims (9)
1. a kind of manufacturing method of transverse direction double-diffused transistor, including：Stair-stepping first is formed among source electrode and drain electrode to be situated between
Matter layer, the first medium layer is relatively thin in close source electrode, thicker close to draining；
The first medium layer is formed by more alternating depositions of dielectric layer A and dielectric layer B, to control the rank of the first medium layer
Terraced thickness.
2. the manufacturing method of transverse direction double-diffused transistor according to claim 1, which is characterized in that include the following steps：
Step 1：First medium layer and second dielectric layer are successively deposited on drift region surface, the first medium layer is by medium
Layer A, dielectric layer B and dielectric layer A are successively deposited, and the thickness of underlying dielectric layers A is at least 2 times of top dielectric layer A thickness,
Glue-line is coated in drain region, using glue-line as blocking, carves the second dielectric layer for removing other regions；
Step 2：Glue-line is removed, using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then will not have
The dielectric layer B of blocking is etched away；
Step 3：Using isotropic etching will second dielectric layer carve remove first thickness, the isotropic etching with silicon table
It face vertical direction and is performed etching with silicon face layer parallel direction；
Step 4：Stopped using second dielectric layer, the top dielectric layer A not stopped all is etched away, will not hindered
The thickness of the underlying dielectric layers A etching top dielectric layer A of gear, then the dielectric layer B not stopped is etched away；
Step 5：Using isotropic etching will second dielectric layer carve remove second thickness, the isotropic etching with silicon table
It face vertical direction and is performed etching with silicon face layer parallel direction；
Step 6：Stopped using second dielectric layer, the top dielectric layer A not stopped all is etched away, will not hindered
The thickness of the underlying dielectric layers A etching top dielectric layer A of gear, all dielectric layer A of etching channel region；
Step 7：It carves and removes all second dielectric layer, gate oxide is grown in silicon face, then in first medium layer and gate oxidation
Deposit forms the third dielectric layer of grid on layer；
Step 8：It is carved using glue-line as blocking except other regions in the third dielectric layer applied atop glue-line of area of grid
Third dielectric layer, dielectric layer A and dielectric layer B.
3. the manufacturing method of transverse direction double-diffused transistor according to claim 1, which is characterized in that include the following steps：
The number of segment of step structure is N, and N is more than or equal to 2,
Step 1：First medium layer and second dielectric layer are successively deposited on drift region surface, the first medium layer is by N number of Jie
A, N-1 dielectric layer B of matter layer are successively deposited, and wherein top layer and lowest level are dielectric layer A, in drain region coating adhesive
Layer carves the second dielectric layer for removing other regions using glue-line as blocking, and removes glue-line；
Step 2：Using second dielectric layer as blocking, the dielectric layer A not stopped is etched away, then Jie that will do not stop
Matter layer B is etched away；
Step 3：Using isotropic etching will second dielectric layer carve remove certain thickness, the isotropic etching with silicon table
It face vertical direction and is performed etching with silicon face layer parallel direction；
Step 4：Step 2 and step 3 carry out N-1 times in turn, so that first medium layer shows N sections of step structure；
Step 5：Stopped using second dielectric layer, the top dielectric layer A not stopped is etched away, then will not stop
Dielectric layer B etch away, all dielectric layer A of etching channel region；
Step 6：It carves and removes all second dielectric layer, gate oxide is grown in silicon face, then in first medium layer and gate oxidation
Deposit forms the third dielectric layer of grid on layer；
Step 7：In the dielectric layer B applied atop glue-line of area of grid, using glue-line as stopping, the except other regions is carved
Three dielectric layers, dielectric layer A and dielectric layer B.
4. the manufacturing method of transverse direction double-diffused transistor according to claim 3, it is characterised in that：The N is equal to 3,
The first medium layer is successively deposited by dielectric layer A, dielectric layer B, dielectric layer A, dielectric layer B and dielectric layer A.
5. the manufacturing method of transverse direction double-diffused transistor according to claim 2 or 3, it is characterised in that：In etch media
The etching mode used when layer A, it is fast and slow to the etch rate of medium B to the etch rate of medium A；In etch media layer B
The etching mode used, it is fast and slow to the etch rate of medium A to the etch rate of medium B.
6. the manufacturing method of transverse direction double-diffused transistor according to claim 2 or 3, it is characterised in that：The dielectric layer A
For oxide layer, the dielectric layer B is silicon oxynitride layer, and the second dielectric layer is silicon nitride layer, and the third dielectric layer is more
Crystal silicon layer.
7. the manufacturing method of transverse direction double-diffused transistor according to claim 1, it is characterised in that：The dielectric layer A
It is formed with dielectric layer B using thermal growth mode.
8. the manufacturing method of transverse direction double-diffused transistor according to claim 1, it is characterised in that：The transverse direction double diffusion
Transistor can be N-type or p-type.
9. a kind of transverse direction double-diffused transistor, it is characterised in that：It is manufactured by any one manufacturing method of the above claim 1-8
It forms.
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| CN108155227A (en) * | 2017-12-14 | 2018-06-12 | 杰华特微电子（杭州）有限公司 | lateral double-diffused transistor and its manufacturing method |
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| CN108155227A (en) * | 2017-12-14 | 2018-06-12 | 杰华特微电子（杭州）有限公司 | lateral double-diffused transistor and its manufacturing method |
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