CN108847826B - Stack type E-type power amplifier adopting dynamic bias network and application thereof - Google Patents

Stack type E-type power amplifier adopting dynamic bias network and application thereof Download PDF

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CN108847826B
CN108847826B CN201810646537.3A CN201810646537A CN108847826B CN 108847826 B CN108847826 B CN 108847826B CN 201810646537 A CN201810646537 A CN 201810646537A CN 108847826 B CN108847826 B CN 108847826B
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transistor
capacitor
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CN108847826A (en
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耿莉
李鹏
夏勤
陈泽强
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Xian Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2176—Class E amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Abstract

The invention discloses a stack type E-class power amplifier adopting a dynamic bias network and application thereof, wherein the stack type E-class power amplifier comprises the following components: the input matching network, the bias network, a load network required by the E-type power amplifier, the output matching network and three transistors; a choke inductor and three transistors are sequentially connected in series between a power supply end and the ground, and the three transistors are stacked in a mode that drain electrodes and source electrodes are connected; the grid electrode of the transistor at the bottommost layer is connected with the input end of the power amplifier through an input matching network, and the drain electrode of the transistor at the topmost layer is connected with the output end of the power amplifier through a load network and an output matching network required by the class-E power amplifier; the gate of the topmost transistor is connected to a dynamic bias network. The stacked E-type power amplifier can improve the power supply voltage of the power amplifier by stacking three transistors and adopting a dynamic bias network, and has higher efficiency compared with the existing E-type power amplifier adopting the transistors with the same channel length.

Description

Stack type E-type power amplifier adopting dynamic bias network and application thereof
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a stacked E-type power amplifier adopting a dynamic bias network and application thereof.
Background
Portable wireless communication devices typically need to deliver relatively large amounts of power, where power efficiency is critical because even a small increase in efficiency can effectively extend battery life. Due to the mode of operation of the zero voltage switch and the zero voltage derivative switch, the class E power amplifier has a high efficiency and is well suited for application in portable wireless communication devices. One significant feature of class E power amplifiers, however, is their high peak voltage (about 3.56V)DD) This increases the voltage stress experienced by the transistor. In order to ensure the reliability of the transistor, the power supply voltage of the class E power amplifier is usually lower than the normal bias voltage of the drain of the transistor, however, as the power supply voltage is reduced, the efficiency of the class E power amplifier is also significantly reduced, which is contradictory to the original purpose of designing a high-efficiency class E power amplifier. To solve this problem, a stacked transistor structure is an important technical approach, which can increase the power supply voltage and thus the efficiency of the class-E power amplifier without increasing the voltage stress of the individual transistors.
At present, part of research works for improving the power supply voltage of a class-E power amplifier by adopting a cascode (cascode) structure so as to improve the efficiency are carried out. For example, the document "Analysis of reliability and power efficiency in cascode class-E PAs" (a.mazzani, l.larcher, r.brama, et al, IEEE Journal of solid-State Circuits, vol.41, No.5, pp.1222-1229, May 2006) analyzes the power loss mechanism of the cascode class-E power amplifier and gives an optimization direction, and also focuses on a power loss mechanism specific to the cascode structure, that is, a loss caused by charging and discharging of a parasitic capacitance of an intermediate node (a node where a drain of a cascode and a source of the cascode are connected), and proposes a solution for resonating off the parasitic capacitance by using a parallel inductor, thereby reducing the power loss and improving the efficiency of the power amplifier. In the document "a Charging Acceleration technology for high hlyeffective Cascode Class-E CMOS Power Amplifiers" (o.lee, j.han, k.h.an, et al, IEEE Journal of Solid-State Circuits, vol.45, No.10, pp.2184-2197, oct.2010), the Charging Acceleration Technique is used to reduce the transition time from the linear region to the cut-off region of the common-gate transistor, so that the common-gate transistor can be rapidly turned off after the common-gate transistor is turned off, thereby reducing the Power loss of the common-gate transistor during the transition and improving the efficiency of the Cascode Class-E Power amplifier. The common problems of the existing cascode class-E power amplifier are as follows: in order to improve the applicable power supply voltage, transistors with thick gate oxide are used, which limits the radio frequency performance of the power amplifier, so that the two cascode class-E power amplifiers can only work at a lower working frequency, and the working frequency is lower than 2 GHz.
Disclosure of Invention
The present invention is directed to a stacked class-E power amplifier using a dynamic bias network and an application thereof, so as to solve the above-mentioned problems. The stacked E-type power amplifier can improve the power supply voltage of the power amplifier by stacking three transistors and adopting a dynamic bias network, and has higher efficiency compared with the existing E-type power amplifier adopting the transistors with the same channel length.
In order to achieve the purpose, the invention adopts the following technical scheme:
by using dynamic bias networkThe stacked class-E power amplifier of (1), comprising: the input matching network, the dynamic bias network, a load network required by the E-type power amplifier, the output matching network and three transistors; a choke inductor and three transistors M are sequentially connected in series between the power supply end and the ground1、M2And M3Three transistors M1、M2And M3Stacking the layers in sequence in a mode that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3The drain electrode of the power amplifier is connected with the output end of the power amplifier through a load network and an output matching network required by the class-E power amplifier; transistor M at the top layer3Is connected to a bias network.
Further, the bias network is a dynamic bias network; three transistors are bottom layer transistors M1Intermediate layer transistor M2And a top layer transistor M3；M1Source of (3) is grounded, M1Is connected to a constant voltage source V through a resistorg1，M1The grid electrode of the grid electrode is connected to the input matching network through a blocking capacitor; m2Source of (2) is connected with M1Drain electrode of, M2Is connected to a constant voltage source Vg2；M3Source of (2) is connected with M2Drain electrode of, M3Is connected to a supply voltage V via a choke inductanceDD，M3Is connected to the output matching network through an inductor and a capacitor connected in series, M3The grid of (A) is connected with a dynamic bias network, and the dynamic bias network is used for being M3A gate bias voltage is provided.
Further, the input matching network includes a capacitor CinAnd an inductance Lin(ii) a Inductor LinOne end of the capacitor is connected with M through a DC blocking capacitor1Is connected to the gate of, an inductor LinAnother end of the capacitor C is connected in parallelinAnd (4) grounding.
Further, the dynamic bias network comprises a first capacitor, a first resistor, a second resistor and a third resistor; m3Is connected to ground through a second resistor and a first capacitor connected in parallel, M3Is connected to M through a first resistor3Drain electrode of, M3Is connected to a constant voltage source V through a third resistorg3。
Further, the output matching network comprises an inductor LmCapacitor CmInductance LmOne end of which passes through an inductor L connected in seriessAnd a capacitor CsConnecting M3Drain electrode of (1), inductor LmThe other end of the capacitor is connected with a parallel capacitor CmGround while inductance LmAnd the other end of the load.
Further, the inductor also comprises a parallel resonance inductor LpAnd a DC blocking capacitor CBLParallel resonant inductor LpOne end of is connected with M3The other end of the drain electrode passes through a DC blocking capacitor CBLAnd (4) grounding.
Further, all three transistors are 0.18 μm NMOS transistors.
Use of any of the above stacked class-E power amplifiers with a dynamic bias network for a radio frequency transmitter.
A radio frequency transmitter comprising any of the above stacked class E power amplifiers employing a dynamic bias network.
Compared with the prior art, the invention has the following beneficial effects:
according to the stacked E-type power amplifier adopting the dynamic bias network, the three transistors are stacked in a mode of connecting the drain electrode and the source electrode, and the grid bias voltage is provided for the topmost transistor through the dynamic bias network, so that the power supply voltage of the power amplifier can be improved, and the efficiency of the power amplifier can be further improved; the class E power amplifier of the present invention has a higher efficiency than existing class E power amplifiers that use transistors of the same channel length.
Furthermore, the novel dynamic bias network can improve the applicable power supply voltage and improve the efficiency of the class-E power amplifier on the premise of not increasing the voltage stress of a single transistor.
Furthermore, the limitation of a small parallel capacitor required by the high-power-supply-voltage class-E power amplifier to the size of the transistor at the working frequency of 5GHz can be broken through by adopting the parallel resonance inductor, the on-resistance of the stacked transistor can be reduced, the power loss of the class-E power amplifier can be further reduced, and the efficiency of the class-E power amplifier is further improved.
Further, stacking three standard 0.18 μm NMOS transistors (without using thick-gate oxide transistors) can achieve 5GHz operation frequency of class E power amplifiers with higher efficiency.
The working frequency of the radio frequency transmitter can reach 5GHz, and the radio frequency transmitter has higher efficiency.
Drawings
Fig. 1 is a schematic circuit diagram of a three-layer stacked class E power amplifier employing fixed gate biasing in accordance with the present invention;
fig. 2 is a schematic circuit diagram of a three-layer stacked class E power amplifier employing conventional dynamic biasing;
fig. 3 is a schematic circuit diagram of a three-layer stacked class E power amplifier employing a novel dynamic bias network of the present invention;
FIG. 4 is a simulation of M for the three-layer stacked class E power amplifier of FIG. 31、M2And M3The drain voltage and gate voltage instantaneous waveform of (a);
fig. 5 is a schematic circuit diagram of a three-layer stacked class E power amplifier of the present invention employing a parallel resonant inductor;
fig. 6 is a schematic circuit diagram of a three-layer stacked class E power amplifier employing a parallel resonant inductor of the present invention;
FIG. 7 shows the output power P of a three-layer stacked class E power amplifier according to the present invention at an operating frequency of 5GHzoutA post-simulation result graph of the power added efficiency PAE changing with the input power;
FIG. 8 shows the peak output power P of a three-layer stacked class E power amplifier according to the present inventionoutAnd the post-simulation result graph of the change of the power added efficiency PAE along with the working frequency.
Detailed Description
The invention is described in further detail below with reference to the figures and specific embodiments.
Referring to fig. 1 to 8, the present inventionA stacked class-E power amplifier employing a dynamic bias network, comprising: the input matching network, the bias network, a load network required by the E-type power amplifier, the output matching network and three transistors; a choke inductor and three transistors are sequentially connected in series between a power supply end and the ground, and the three transistors are stacked in a mode that drain electrodes and source electrodes are connected; the grid electrode of the transistor at the bottommost layer is connected with the input end of the power amplifier through an input matching network, and the drain electrode of the transistor at the topmost layer is connected with the output end of the power amplifier through a load network and an output matching network required by the class-E power amplifier; the gate of the topmost transistor is connected to a dynamic bias network. The concrete connection is as follows: the bias network is a novel dynamic bias network; three transistors are bottom layer transistors M1Intermediate layer transistor M2And a top layer transistor M3；M1Source of (3) is grounded, M1Is connected to a constant voltage source V through a resistorg1，M1The grid electrode of the grid electrode is connected to the input matching network through a blocking capacitor; m2Source of (2) is connected with M1Drain electrode of, M2Is connected to a constant voltage source Vg2；M3Source of (2) is connected with M2Drain electrode of, M3Is connected to a supply voltage V via a choke inductanceDD，M3Is connected to the parallel resonant inductor LpOne terminal of (1), a parallel resonance inductor LpThe other end of the capacitor passes through a DC blocking capacitor CBLGround, M3Through the inductor L connected in seriessAnd a capacitor CsConnected to an output matching network, M3The grid of (A) is connected with a dynamic bias network, and the dynamic bias network is used for being M3A gate bias voltage is provided. Wherein the input matching network comprises a capacitor CinAnd an inductance Lin(ii) a Inductor LinOne end of the capacitor is connected with M through a DC blocking capacitor1Is connected to the gate of, an inductor LinAnother end of the capacitor C is connected in parallelinAnd (4) grounding. The dynamic bias network comprises a first capacitor, a first resistor, a second resistor and a third resistor; m3Is connected to ground through a second resistor and a first capacitor connected in parallel, M3Is connected to M through a first resistor3Drain electrode of, M3Is connected to a constant voltage source V through a third resistorg3. The output matching network comprises an inductor LmCapacitor CmInductance LmOne end of which passes through an inductor L connected in seriessAnd a capacitor CsConnecting M3Drain electrode of (1), inductor LmThe other end of the capacitor is connected with a parallel capacitor CmGround while inductance LmThe other end of the load is connected with the load; the three transistors in the stack are all 0.18 μm NMOS transistors.
The working principle of the invention is as follows:
design equation based on class E power amplifier
Figure BDA0001703648870000051
It is known that, when the output power is constant, the larger the applied power supply voltage is, the load resistance R required for the class-E power amplifier isLThe larger the load resistance is, on one hand, the impedance transformation ratio of the output matching network can be reduced, the power conversion efficiency of the matching network is improved, and on the other hand, the influence of the transistor on-resistance on the efficiency of the class-E power amplifier can be weakened. Therefore, increasing the supply voltage may increase the efficiency of the class E power amplifier. However, it is not easy to increase the supply voltage of class E power amplifiers; for the class E power amplifier, the peak value of the drain voltage can reach 3.56V when the transistor is turned offDDThis subjects the device to significant voltage stress, and in order to ensure device reliability, class E power amplifiers typically apply a supply voltage that is lower than the normal bias voltage of the transistor drain. It is conventional practice to keep the maximum voltage drop across the transistor less than 2VDD-nominalTo ensure reasonable device lifetime, VDD-nominalRefers to the supply voltage that the device conventionally allows. That is, for a 0.18 μm NMOS transistor, the voltage difference between the gate drain and the gate source is less than 3.6V, and when this condition is satisfied, the maximum power voltage that can be applied by the conventional cascode class-E power amplifier is only 0.88V, the maximum power voltage can be increased to 1.76V by the conventional cascode class-E power amplifier, and although the power voltage can be further increased by using a transistor with thick gate oxide (e.g., a 0.35 μm NMOS transistor), the radio frequency performance of the class-E power amplifier is limited. In order to realize a high-efficiency class-E power amplifier with the working frequency of 5GHz, three standard 0.18-micrometer NMOS tubes are stacked, a novel dynamic bias network is designed aiming at the defects and shortcomings of fixed bias and traditional dynamic bias, the power supply voltage is improved on the premise of not increasing the voltage stress of a single transistor, and the efficiency of the class-E power amplifier is further improved. Meanwhile, the parallel resonance inductor is adopted, the limitation of a small parallel capacitor required by a high power supply voltage class E power amplifier to the size of a transistor at 5GHz is broken, the on-resistance of a stacked transistor is reduced, and the power loss of the class E power amplifier is further reduced.
Example 1
Referring to fig. 1, the three-layer stacked class-E power amplifier with fixed-gate bias according to the present invention has a choke inductor and three transistors M connected in series between a power supply terminal and ground in sequence3、M2And M1The three transistors are stacked in a mode that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3Through a parallel capacitor CshGrounded while passing through a series inductor LsAnd a capacitor CsThe output matching network is connected with the output end of the power amplifier; three transistors M3、M2And M1The grids of the grid electrodes are respectively connected with a constant voltage source Vg3、Vg2And Vg1. For a class E power amplifier with three stacked 0.18 μ M NMOS transistors, due to the switching transistor M1The source and drain voltages of each transistor are close to 0V when conducting, in order to ensure M3The voltage difference between the gate drain and the gate source is less than 3.6V, and M is in the case of constant bias3Is connected to a voltage of at most 3.6V, so that when the switch is turned off, M3The peak drain voltage of the transistor can only reach 7.2V. Due to the peak voltage V of the drain electrode of the E-type power amplifierpk≈3.56VDDTherefore, the three-layer stacked class-E power amplifier adopting fixed gate bias can only apply 2V of power supply voltage at most, and the effect is improved compared with the class-E power amplifier of the traditional cascode structure, but the effect is not particularly goodIs remarkable.
Example 2
Referring to fig. 2, a three-layer stacked class-E power amplifier using conventional dynamic bias has a choke inductor and three transistors M connected in series between a power supply terminal and ground in sequence3、M2And M1The three transistors are stacked in a mode that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3Through a parallel capacitor CshGrounded while passing through a series inductor LsAnd a capacitor CsThe output matching network is connected with the output end of the power amplifier; transistor M2And M1The grids of the grid electrodes are respectively connected with a constant voltage source Vg2And Vg1Transistor M3Gate pass capacitance C1Grounded while passing through a resistor R1Connecting M3Of the substrate. As can be seen from FIG. 2, the conventional dynamic bias scheme is via a resistor R1Transistor M3Is connected to the drain and is connected to a capacitor C connected to ground at the gate1So that the gate voltage will follow the drain voltage. This dynamic biasing scheme is widely used in other types of power amplifiers, but for class E power amplifiers, M is the time when the switch is on3Is close to 0V, if the gate voltage also follows towards 0V, then transistor M3It is not normally turned on and further improvement is made below.
Referring to fig. 3, the three-layer stacked class-E power amplifier of the present invention using the novel dynamic bias network has a choke inductor and three transistors M connected in series between the power source terminal and the ground in sequence3、M2And M1The three transistors are stacked in a mode that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3Through a parallel capacitor CshGrounded while passing through a series inductor LsAnd a capacitor CsThe output matching network is connected with the output end of the power amplifier; transistor M2And M1The grids of the grid electrodes are respectively connected with a constant voltage source Vg2And Vg1Transistor M3Is connected to ground through a second resistor and a first capacitor connected in parallel, M3Is connected to M through a first resistor3Drain electrode of, M3Is connected to a constant voltage source V through a third resistorg3. As can be seen from FIG. 3, M3Is connected to the drain electrode and is also connected to the drain electrode through a resistor R3Connected to a constant voltage source Vg3(Vg34V). According to the principle of superposition, M3Is proportional to leakage voltage and is also proportional to constant voltage source Vg3Is in direct proportion. Thus, when the switch is on, M3The gate voltage can be maintained at a constant value (around 3.3V) while the drain voltage of (a) is close to 0V; when the switch is turned off, the drain voltage increases to a peak value, and the gate voltage also increases, so that the voltage difference between the gate and the drain is ensured to be less than 3.6V. It can be found by simulation that the instantaneous waveforms of the drain and gate voltages of the three transistors are shown in fig. 4. With a supply voltage of 2.5V, M3Leakage voltage VD3Has a peak value close to 8.9V and a gate voltage VG3Will be followed by an increase to 5.6V, so that VGD33.3V is less than 3.6V, so that gate oxide breakdown is avoided, and the reliability of the device is ensured. The class-E power amplifier is overdriven, and the input voltage swing of the present invention is set to 1.7V (i.e., the supply voltage V of the driver stage)DD_driver1.7V) due to M1The gate voltage is biased at 0.42V, so VG1The minimum can reach-1.28V, and V is realized at the momentD1Just to maximum, in order to make VGD1＜3.6V，VD1Is less than 2.32V, so M2Gate voltage V ofG2Is fixedly biased at 2.3V. As can be seen from FIG. 4, by dynamically biasing M3Gate voltage V ofG3Fixed offset M2Gate voltage V ofG2The voltage stress experienced by the class-E power amplifier is equally distributed over the three transistors, and the V of each transistorGDAre all close to a maximum of 3.6V, which makes the peak voltage of the stacked class-E power amplifier close to 8.9V, and the applicable supply voltage also increases to 2.5V. Assume that the peak output power of the class-E power amplifier to be achieved is 175mW (m w) ((m w))22.4dBm), considering that the maximum power voltages which can be applied by the traditional common-source class-E power amplifier adopting a 0.18-micron NMOS tube, the traditional cascode class-E power amplifier and the class-E power amplifier provided by the invention are 0.88V, 1.76V and 2.5V respectively, according to the design equation of the class-E power amplifier, the load resistors R required by the three class-E power amplifiersL2.55 omega, 10.2 omega and 20.6 omega respectively, and the impedance transformation ratio of the corresponding output matching network is 19.6, 4.9 and 2.4 respectively. When the output matching is realized by using a simple LC impedance transformation network and the used inductance quality factor Q is 6, the power conversion efficiency of the output matching networks of the three class-E power amplifiers is 58.2%, 75.2% and 83.5%, respectively. Through the analysis, the three-layer stacked class-E power amplifier adopting the novel dynamic bias network can obviously improve the power conversion efficiency of the output matching network and improve the overall efficiency of the power amplifier.
Example 3
The above embodiment of the present invention increases the applicable supply voltage of the class E power amplifier to 2.5V by stacking 3 transistors and using a novel dynamic bias network, thereby increasing the load resistance R required for the optimal class E operating stateLThe frequency is increased to 20.6 omega, and when the class E power amplifier works at a higher frequency of 5GHz, the design equation of the class E power amplifier is used
Figure BDA0001703648870000091
Parallel capacitance C required for optimal class E operating conditionsshVery small, only 0.284 pF. Considering that the parasitic capacitance of the drain of the transistor has to be a part of the parallel capacitance, in case the required parallel capacitance is small, the gate width of the transistor is still very limited even if the parallel capacitance is completely provided by the parasitic capacitance of the drain of the transistor. Furthermore, the transistor stack increases the on-resistance, and the transistor should be large in size in order to reduce the series on-resistance. Further improvements are made in order to break the transistor size limitation of small parallel capacitors.
Referring to fig. 5 and 6, a three-layer structure using parallel resonant inductors according to the present inventionStacked class E power amplifier, R1、R2、R3And C1Form a novel dynamic bias network, LpThe parallel resonance inductor is provided by the invention; c2And CBLIs a blocking capacitor; l isinAnd CinForming an input matching network for coupling the transistor M1The input impedance of the gate is matched to a source impedance of 50 omega. L ismAnd CmForming an output matching network for matching a load resistance R of 20.6 omegaLTo an antenna input impedance of 50 omega. A choke inductor and three transistors M are sequentially connected in series between the power supply end and the ground3、M2And M1The three transistors are stacked in a manner that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3Is connected through a series inductor LsAnd a capacitor CsThe output matching network is connected with the output end of the power amplifier; transistor M2And M1The grids of the grid electrodes are respectively connected with a constant voltage source Vg2And Vg1Transistor M3Is connected to ground through a second resistor and a first capacitor connected in parallel, M3Is connected to M through a first resistor3Drain electrode of, M3Is connected to a constant voltage source V through a third resistorg3，M3Is connected to the parallel resonant inductor LpOne terminal of (1), a parallel resonance inductor LpThe other end of the capacitor passes through a DC blocking capacitor CBLAnd (4) grounding. As can be seen from FIG. 5, the present embodiment employs a parallel inductor LpThe redundant parasitic capacitance is resonated out, and the residual part is used for providing the parallel capacitance required by the E-type working condition, so that the size of the transistor can be increased to 750 mu m, the series on-resistance of the stacked transistor can be effectively reduced, and the efficiency of the power amplifier can be further improved.
FIG. 7 shows the output power P of a three-layer stacked class E power amplifier designed according to the present invention at 5GHzoutFrom the post-simulation results of the variation of power added efficiency PAE with the input power, it can be seen from FIG. 7 that the power amplifier realizes the power amplifier at 5GHzA power added efficiency PAE of up to 49.5% and a drain efficiency DE of 53.7%, while achieving a peak output power of 22.3 dBm.
Fig. 8 shows post-simulation results of peak output power and PAE versus frequency for a three-layer stacked class E power amplifier designed according to the present invention, which achieves a PAE in excess of 44.9% and a peak output power in excess of 21dBm over the frequency range of 4.8-5.2 GHz.
The stacked E-type power amplifier adopting the dynamic bias network is an E-type power amplifier structure with three stacked transistors, and the power supply voltage can be improved by stacking the three transistors and adopting the novel dynamic bias network on the premise of not increasing the voltage stress of a single transistor, so that the efficiency of the E-type power amplifier is improved. In addition, the parallel resonance inductance structure breaks through the limitation of small parallel capacitors required by the class-E power amplifier with high working frequency and high power supply voltage on the size of the transistor, increases the size of the transistor, reduces the on-resistance of the stacked transistors, further improves the efficiency of the class-E power amplifier, and enables the working frequency of the amplifier to reach 5 GHz.
The radio frequency transmitter comprises the stacked type E power amplifier adopting the dynamic bias network, wherein the stacked type E power amplifier is formed by stacking three transistors according to the connection of sources and drains. Transistor M at the bottom layer1Is grounded, and the gate is connected to a constant voltage source V through a resistorg1And is connected to the input matching network through a blocking capacitor. The input matching network is formed by a capacitor connected in parallel to ground and a series inductor. Intermediate transistor M2Is connected to a constant voltage source Vg2. Top transistor M3Is connected to a supply voltage V via a chokeDD. Top transistor M3The grid electrode of the grid electrode is provided with bias voltage by the novel dynamic bias network, and the novel dynamic bias network has the following specific connection mode: top transistor M3Is connected to ground through a parallel resistor capacitor, and is connected to the drain through a resistor and a constant voltage source V respectivelyg3. Top transistor M3Is connected to one end of the parallel resonant inductor, and the other end of the parallel resonant inductor is connected to ground through a dc blocking capacitor. Top transistor M3The drain of the series inductor is connected to the output matching network through a series inductor capacitor, a part of the series inductor and the series capacitor realize series resonance at the working frequency, only the fundamental frequency component of leakage current is ensured to pass through the load, and the other part of the series inductor provides an extra phase shift between the output voltage and the output current, so as to ensure that the optimal class E working condition is realized. The output matching network consists of a series inductor and a capacitor connected to the ground in parallel and is responsible for matching 50 omega impedance to a load resistor R required by the class-E power amplifierL. The working frequency of the radio frequency transmitter can reach 5GHz, and the radio frequency transmitter has high efficiency.

Claims (7)

1. A stacked class-E power amplifier employing a dynamic bias network, comprising: the input matching network, the dynamic bias network, a load network required by the E-type power amplifier, the output matching network and three transistors;
a choke inductor and three transistors M are sequentially connected in series between the power supply end and the ground1、M2And M3Three transistors M1、M2And M3Stacking the layers in sequence in a mode that the drain electrodes and the source electrodes are connected; transistor M at the bottom1The grid of the transistor M is connected with the input end of the power amplifier through an input matching network, and the transistor M at the topmost layer3The drain electrode of the power amplifier is connected with the output end of the power amplifier through a load network and an output matching network required by the class-E power amplifier; transistor M at the top layer3The grid of the grid is connected with a bias network;
the bias network is a dynamic bias network;
three transistors are bottom layer transistors M1Intermediate layer transistor M2And a top layer transistor M3；
M1Source of (3) is grounded, M1Is connected to a constant voltage source V through a resistorg1，M1The grid electrode of the grid electrode is connected to the input matching network through a blocking capacitor;
M2source of (2) is connected with M1Drain electrode of, M2Is connected to a constant voltage source Vg2；
M3Source of (2) is connected with M2Drain electrode of, M3Is connected to a supply voltage V via a choke inductanceDD，M3Is connected to the output matching network through an inductor and a capacitor connected in series, M3The grid of (A) is connected with a dynamic bias network, and the dynamic bias network is used for being M3Providing a gate bias voltage;
the dynamic bias network comprises a first capacitor, a first resistor, a second resistor and a third resistor; m3Is connected to ground through a second resistor and a first capacitor connected in parallel, M3Is connected to M through a first resistor3Drain electrode of, M3Is connected to a constant voltage source V through a third resistorg3。
2. The stacked class-E power amplifier with dynamic bias network of claim 1, wherein the input matching network comprises a capacitor CinAnd an inductance Lin(ii) a Inductor LinOne end of the capacitor is connected with M through a DC blocking capacitor1Is connected to the gate of, an inductor LinAnother end of the capacitor C is connected in parallelinAnd (4) grounding.
3. The stacked class-E power amplifier of claim 1, wherein the output matching network comprises an inductor LmCapacitor CmInductance LmOne end of which passes through an inductor L connected in seriessAnd a capacitor CsConnecting M3Drain electrode of (1), inductor LmThe other end of the capacitor is connected with a parallel capacitor CmGround while inductance LmAnd the other end of the load.
4. The stacked class-E power amplifier with dynamic bias network of claim 1, further comprising a parallel resonant inductor LpAnd a DC blocking capacitor CBLParallel resonant inductor LpOne end of is connected with M3The other end of the drain electrode passes through a DC blocking capacitor CBLAnd (4) grounding.
5. The stacked class-E power amplifier with dynamic bias network of claim 1, wherein all three transistors are 0.18 μm NMOS transistors.
6. Use of a stacked class-E power amplifier employing a dynamic bias network according to any of claims 1 to 5 for a radio frequency transmitter.
7. A radio frequency transmitter comprising a stacked class E power amplifier employing a dynamic bias network as claimed in any one of claims 1 to 5.
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