CN108809329B

CN108809329B - Configuration method of BP decoder capable of simultaneously processing polarization code and LDPC code

Info

Publication number: CN108809329B
Application number: CN201810413191.2A
Authority: CN
Inventors: 张川; 杨宁远; 景树森; 俞安澜; 梁霄; 尤肖虎
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2018-05-03
Filing date: 2018-05-03
Publication date: 2021-09-28
Anticipated expiration: 2038-05-03
Also published as: CN108809329A

Abstract

The invention discloses a configuration method of a BP decoder capable of simultaneously processing a polarization code and an LDPC code, which comprises the following steps: (1) designing a basic module; (2) designing a polar code decoding module; (3) designing an LDPC decoding module; (4) designing a unified decoding hardware architecture; (5) and (3) comparing the decoding performance and the hardware complexity of the polarization code decoding module in the step (2) and the LDPC decoding module in the step (3), and realizing by using Verilog. The invention can realize the unification of hardware architecture and reduce the overall hardware consumption.

Description

Configuration method of BP decoder capable of simultaneously processing polarization code and LDPC code

Technical Field

The invention relates to the technical field of wireless communication, in particular to a configuration method of a BP decoder capable of processing a polarization code and an LDPC code simultaneously.

Background

The mobile communication has undergone the development process of the first generation analog communication (1G), the second generation cellular digital communication (2G) and the third generation CDMA broadband communication (3G), and has now entered the application stage of the fourth generation mobile communication (4G) industrialization. Mobile communications are moving towards high speed, high capacity, high spectral efficiency and low power consumption, continuously meeting the ever-increasing data and video demands of people. According to the prediction of main operators and authoritative consultants: mobile broadband traffic will grow 1000 times in the next 10 years. The existing 4G technology still cannot meet future requirements in the aspects of transmission rate, resource utilization rate and the like, and the wireless coverage and user experience of the technology are yet to be further improved. While promoting 4G industrialization in all countries around the world, the fifth generation mobile communication technology (5G) has become a research hotspot in the field of domestic and foreign wireless communication. The 5G can meet the diversified business requirements of work, life and entertainment of people, and can provide extreme business experiences of ultra-clear videos, augmented reality, online games and the like for users even in scenes with ultra-high flow density, ultra-high connection number density and ultra-high mobility characteristics such as central business areas, dense residential areas, stadiums, highways and the like.

In recent years, with the wide application of wireless communication technology in various fields, social communication requirements are rapidly increased rapidly, and the traditional communication technology cannot meet the social development requirements increasingly. According to the prediction of main operators and authoritative consultants, the mobile broadband service flow will increase by 1000 times in the next 10 years. To cope with the enormous communication pressure in the future, 5G has come to be produced as a completely new mobile communication technology. The key technology of the 5G mobile communication is mainly embodied in the ultra-high-performance wireless transmission technology and the high-density wireless network technology. Massive MIMO greatly improves spectral efficiency, connection reliability and coverage over conventional small-scale MIMO systems. Meanwhile, a high-performance and high-efficiency channel coding technology will become an important research direction of 5G. Under a brand-new application scenario of 5G mobile communication, a polarization code and a Low Density Parity Check (LDPC) code are set as standard encoding schemes, and the two encoding modes coexist in the same communication transmission scheme, which has attracted extensive attention in academia and industry.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a method for configuring a BP decoder capable of processing a polar code and an LDPC code simultaneously, which can achieve unification of hardware architectures and reduce overall hardware consumption.

In order to solve the above technical problem, the present invention provides a method for configuring a BP decoder capable of simultaneously processing a polarization code and an LDPC code, comprising the steps of:

(1) designing a basic module;

(2) designing a polar code decoding module;

(3) designing an LDPC decoding module;

(4) designing a unified decoding hardware architecture;

(5) and (3) comparing the decoding performance and the hardware complexity of the polarization code decoding module in the step (2) and the LDPC decoding module in the step (3), and realizing by using Verilog.

Preferably, in the step (1), the designing of the basic module specifically includes: the decoding calculation formula of the polarization code is as follows:

in formula (1), the variables L and R represent probability quantities that are passed to the left and right, respectively, and the subscripts thereof represent the positions of the nodes; based on the Min-Sum algorithm, the g function is calculated as follows:

g(x,y)＝sgn(x)sgn(y)min(|x|,|y|) (2)

in formula (2), sgn (x) and sgn (y) denote symbols for x and y, respectively;

the decoding calculation formula of the LDPC code is as follows:

l in the formulas (3) and (4) represents a probability quantity for transferring information;

the equations (1), (2) and (3) contain two important factors: the sign of the two numbers and the minimum of the absolute values of the two numbers; the g-function calculation module GFU consists of an exclusive-OR gate and a comparator; the exclusive-or gate is used for obtaining the product of two numbers and the comparator is used for obtaining the minimum value of the absolute values of the two numbers.

Preferably, in the step (2), designing a polar code decoding module specifically includes: for the decoding process of the polarization code, a two-input GFU module is used to calculate equation (1), and equation (1) can be divided into the following two types:

fig. 2 illustrates the hardware design of its corresponding computing module, the first type being: the two inputs are firstly calculated by GFU, and the result is added with the other input to obtain the final output; the second type is: the two inputs are added, and the sum of the result and the other input are subjected to GFU calculation to obtain the final output. Fig. 3 shows the hardware design of the basic computation block BCB of the polar code: it consists of 4 GFUs and 4 adders; rectangles indicated by black solid lines indicate registers for registering probability quantities passed to the left or to the right. The computation blocks in fig. 3 are divided into 4 groups, each group containing 1 adder and 1 GFU, two of which are the first type in fig. 2 and the other two of which are the second type in fig. 2, and the corresponding input and output values and connection modes are given by equation (1).

Preferably, in step (3), designing the LDPC decoding module specifically includes: in the decoding calculation formula (3) of the LDPC code, the right side of the equation has two or more probability quantities, if a certain number of GFUs are assembled to form a CU unit, the decoding process of the LDPC code can be executed; by observing the recursive nature of the following equation:

thus, fig. 4 designs a multi-input CN unit: the left half of fig. 4 is a three-input CU, which consists of 2 GFUs; the right half of fig. 4 is a four-input CU, which consists of 3 GFUs; to demonstrate the specific design process, a specific 6 × 12 LDPC code is considered, and the H matrix is as follows:

each CN node has 4 inputs and 4 outputs, and each VN has 3 inputs and 3 outputs; FIG. 5 shows the hardware design of the 0 th CN unit: it consists of 8 GFU units; from equation (7), the input to the 0 th CN unit is L (q)₀₀)、L(q₁₀)、L(q₂₀) And L (q)₃₀) The output is L (r)₀₀)、L(r₀₁)、 L(r₀₂) And L (r)₀₃) (ii) a From the formula (3), the hardware connection mode can be obtained, that is, the 8 GFU units are divided into 4 groups, and each group is a three-input CU unit composed of 2 GFUs; in addition, each VN unit will consist of 3 adders, for a total of 48 GFU units and 36 adders.

Preferably, in the step (4), designing a unified decoding hardware architecture specifically includes: a 9-input 6-output merging computation module MBCB for executing two decoding processes; according to the difference of the selection signal S, the MBCB has two different internal connection modes; in fig. 6, the solid black line indicates the hardware connection manner when decoding the polarization code, and the hardware connection manner is the same as that in fig. 3; the black dotted line indicates the hardware connection manner when decoding the LDPC code, which is consistent with the hardware connection manner in fig. 5; the selection signal S is 0 or 1 and is used for switching the two hardware connection modes;

the function of the MBCB and the function of the BCB are the same when decoding the polarization code; in addition, a pair of MBCBs is multiplexed for use in performing the work of decoding LDPC codes; FIG. 7 shows a design of a pair of MBCBs: their internal connection hardware is shown in fig. 6, the solid arrows represent the input and output of the polarization code, and the dotted arrows represent the input and output of the LDPC code;

the configuration decoder uses 96 exclusive-or gates, 96 comparators and 48 adders in total, and can be used for executing the decoding work of 8-bit polarization codes and the decoding work of the LDPC codes; compared with the sum of a polar code decoder and an LDPC decoder, the number of the exclusive-OR gates, the comparators and the adders of the configurable decoder is reduced by 50%, 50% and 43% respectively.

The invention has the beneficial effects that: the invention can realize the unification of hardware architecture and reduce the total hardware consumption, namely, under the condition of less decoding performance loss, the decoding functions of two different codes can be respectively realized at the cost of one set of decoder hardware.

Drawings

Fig. 1 is a schematic diagram of the design of a basic computing module GFU of the present invention.

Fig. 2 is a schematic diagram of hardware design corresponding to two calculation formulas of the polarization code of the present invention.

Fig. 3 is a hardware schematic diagram of a basic computation module BCB of a polarization code according to the present invention.

FIG. 4 is a hardware diagram of the LDPC basic module CU.

FIG. 5 is a hardware diagram of the CN module of LDPC of the present invention.

FIG. 6 is a hardware schematic of an MBCB according to the present invention.

Fig. 7 is a hardware schematic diagram of another MBCB of the present invention.

FIG. 8 is a performance curve of the decoder according to the present invention performing the decoding operation.

Detailed Description

A configuration method of a BP decoder capable of processing polarization codes and LDPC codes simultaneously comprises the following steps:

(1) designing a basic module;

(2) designing a polar code decoding module;

(3) designing an LDPC decoding module;

(4) designing a unified decoding hardware architecture;

The configurable BP decoder capable of processing both polarization codes and LDPC codes is described in detail below with reference to the following specific examples and accompanying drawings:

1. design of basic module:

the decoding calculation formula of the polarization code is as follows:

in equation (1), the L and R variables represent the probability quantities passed to the left and right, respectively, with the subscripts indicating where the nodes are located. Based on the Min-Sum algorithm, the g function is calculated as follows:

g(x,y)＝sgn(x)sgn(y)min(|x|,|y|) (2)

in formula (2), sgn (x) and sgn (y) denote symbols for x and y, respectively.

The decoding calculation formula of the LDPC code is as follows:

l in the formulas (3) and (4) represents a probability quantity for transferring information.

The equations (1), (2) and (3) contain two important factors: the sign of the two numbers and the minimum of the absolute values of the two numbers. Fig. 1 shows a g-function calculation module GFU, which consists of an exclusive or gate and a comparator. The exclusive-or gate is used for obtaining the product of two numbers and the comparator is used for obtaining the minimum value of the absolute values of the two numbers.

2. Design of a polar code decoding module:

for the decoding process of the polarization code, a two-input GFU module is used to calculate equation (1), and equation (1) can be divided into the following two types:

fig. 2 illustrates the hardware design of its corresponding computing module. Fig. 3 shows the hardware design of the Basic Computation Block (BCB) of the polarization code, which consists of a GFU and an adder. Rectangles indicated by black solid lines indicate registers for registering probability quantities passed to the left or to the right.

3. Design of LDPC decoding module: since there are two or more probability quantities on the right side of the equation in the decoding calculation formula (3) of the LDPC code, if a certain number of GFUs are assembled, the decoding process of the LDPC code can be performed. By observing the recursive nature of the following equation:

thus, fig. 4 designs a multi-input CU unit. Next, to demonstrate a specific design process, a specific 6 × 12 LDPC code is considered, and the H matrix is as follows:

each CN node has 4 inputs and 4 outputs, and each VN has 3 inputs and 3 outputs; the 0 th CN unit consists of 8 GFU units; from equation (7), the input to the 0 th CN unit is L (q)₀₀)、L (q₁₀)、L(q₂₀) And L (q)₃₀) The output is L (r)₀₀)、L(r₀₁)、L(r₀₂) And L (r)₀₃) (ii) a The hardware connection mode is obtained by the formula (3), namely the 8 GFU units are divided into 4 groups, and each group is a three-input CU unit consisting of 2 GFUs; in addition, each VN unit will consist of 3 adders, for a total of 48 GFU units and 36 adders.

4. Designing a unified decoding hardware architecture:

fig. 6 shows a 9-input 6-output merge computation module MBCB, which can be used to perform both decoding processes. The MBCB has two different internal connection modes depending on the selection signal S. In fig. 6, the solid black line indicates the hardware connection mode when decoding the polarization code, the dashed black line indicates the hardware connection mode when decoding the LDPC code, and the selection signal S is 0 or 1 for switching between the two hardware connection modes.

The function of the MBCB and the function of the BCB are the same when decoding the polarization code. In addition, a pair of MBCBs is multiplexed for use in performing the work of decoding LDPC codes. Fig. 7 shows a design diagram of a pair of MBCBs, solid arrows representing input and output of a polarization code, and dotted arrows representing input and output of an LDPC code.

Therefore, the configurable decoder uses 96 exclusive-or gates, 96 comparators and 48 adders in total, and can be used for performing the decoding operation of the 8-bit polarization code and the decoding operation of the LDPC code. Compared with the sum of a polar code decoder and an LDPC decoder, the number of the exclusive-OR gates, the comparators and the adders of the configurable decoder is reduced by 50%, 50% and 43% respectively.

5. Decoding performance analysis, hardware complexity comparison and Verilog realization result:

fig. 8 analyzes the performance of the polar code decoding process and the LDPC decoding process. Triangle curve representation using floating point numbersThe circular curve represents the performance of LDPC decoding by using fixed point numbers (1 bit sign bit, 4 bit integer bits, 2 bit decimal bits). The star curve represents the performance of decoding the polar code by using floating point number, and the square curve represents the performance of decoding the polar code by using fixed point number (1 sign bit, 4 integer bits, 2 decimal bits). When BER is 10^-2When compared with floating point number, the signal-to-noise ratio of LDPC code has 0.5dB gain, and the signal-to-noise ratio of polar code has 0.2dB gain. In this case, the loss of hardware performance is acceptable.

Table 1 is a theoretical comparative analysis of hardware complexity. The hardware complexity of the configurable BP decoder is determined by the code length N of the polar code to be 2ⁿ(n.gtoreq.2) determination, comprising 2 Nxlog₂N comparators, 2 Nx log₂N adders and 2 Nxlog₂N exclusive-OR gates. The table also gives the sum of the hardware complexity of a polar code decoder and an LDPC decoder. In the H matrix of the LDPC code, a_j(a_j≧ 3) represents the number of '1's in the jth row of the matrix, b_i(b_i≧ 2) represents the number of '1's in the ith column of the matrix. From the number of '1's in the matrix, the equation can be derived:

where m refers to the total code length of the LDPC code and k refers to the number of information bits in the LDPC code.

Table 2 lists the results of Verilog implementation; when the decoder processes the LDPC code with the code length of 12 and the coding rate of 0.5, setting the iteration number to be equal to 10, totally requiring 10 clock cycles, and calculating the throughput rate to be 144.6 Mbps; when the decoder processes the polar code with the code length of 8 and the coding rate of 0.5, the iteration number is set to be equal to 10, 63 clock cycles are needed in total, and the throughput rate is calculated to be 15.3 Mbps.

TABLE 1 decoder hardware complexity comparison

TABLE 2 Verilog implementation results

Decoding process	LDPC decoding	Polar code decoding
			Number of iterations	10	10
Code length	12	8
			Encoding rate	0.5	0.5
Throughput rate (Mbps)	144.6	15.3
			Number of clock cycles	10	63

The decoding algorithms of the polarization code and the LDPC code comprise belief propagation algorithms (BP), the calculation formulas of the BP algorithms have certain similarity, and the calculation formulas of the BP algorithms both relate to the processing of the sign bits of two numbers and the minimum value of the absolute values of the sign bits. Therefore, a basic module can be designed which comprises an exclusive or gate and a comparator for calculating the product of the sign bits of the two numbers and their absolute value minimum, respectively. On the basis, the hardware design of the polar code decoding module and the hardware design of the LDPC decoding module are respectively analyzed. Furthermore, a polarization code decoding module and an LDPC decoding module are integrated, and a set of unified decoding hardware architecture is designed, so that the polarization code decoding method can be used for decoding polarization codes and can also be used for decoding LDPC codes. Finally, the decoding performance of the hardware is analyzed, the complexity of the hardware is compared, and a Verilog implementation result is also given.

Claims

1. A configuration method of a BP decoder capable of simultaneously processing a polarization code and an LDPC code is characterized by comprising the following steps:

(1) designing a basic module;

(2) designing a polar code decoding module; the method specifically comprises the following steps: for the decoding process of the polarization code, a two-input GFU module is used to calculate formula (1), and formula (1) is classified into the following two types:

there are two types of computing modules, the first: the two inputs are firstly calculated by GFU, and the result is added with the other input to obtain the final output; the second type: the two inputs are added, and the result and the other input are subjected to GFU calculation to obtain final output;

(3) designing an LDPC decoding module;

(4) designing a unified decoding hardware architecture;

2. The method for configuring BP decoder capable of simultaneously processing both polar code and LDPC code according to claim 1, wherein in the step (1), designing the basic module specifically comprises: the decoding calculation formula of the polarization code is as follows:

g(x,y)＝sgn(x)sgn(y)min(|x|,|y|) (2)

in formula (2), sgn (x) and sgn (y) denote symbols for x and y, respectively;

the decoding calculation formula of the LDPC code is as follows:

the equations (1), (2) and (3) contain two important factors: the sign of the two numbers and the minimum of the absolute values of the two numbers; the g function calculation module GFU consists of an exclusive-OR gate and a comparator; the exclusive-or gate is used for obtaining the product of two numbers and the comparator is used for obtaining the minimum value of the absolute values of the two numbers.

3. The method for configuring BP decoder capable of simultaneously processing both polar code and LDPC code according to claim 1, wherein in step (3), designing the LDPC decoding module specifically comprises: in the decoding calculation formula (3) of the LDPC code, the right side of the equation has two or more probability quantities, if a certain number of GFUs are assembled to form a CU unit, the decoding process of the LDPC code can be executed; by observing the recursive nature of the following equation:

the three-input CU consists of 2 GFUs, and the four-input CU consists of 3 GFUs; to demonstrate the specific design process, a specific 6 × 12 LDPC code is considered, and the H matrix is as follows:

each CN node has 4 inputs and 4 outputs, and each VN has 3 inputs and 3 outputs; the 0 th CN unit consists of 8 GFU units; from equation (7), the input to the 0 th CN unit is L (q)₀₀)、L(q₁₀)、L(q₂₀) And L (q)₃₀) The output is L (r)₀₀)、L(r₀₁)、L(r₀₂) And L (r)₀₃) (ii) a The hardware connection mode is obtained by the formula (3), namely the 8 GFU units are divided into 4 groups, and each group is a three-input CU unit consisting of 2 GFUs; in addition, each VN unit will consist of 3 adders, for a total of 48 GFU units and 36 adders.

4. The method for configuring BP decoder capable of simultaneously processing polar code and LDPC code according to claim 1, wherein in the step (4), designing a unified decoding hardware architecture specifically comprises: a 9-input 6-output merging computation module MBCB for executing two decoding processes; according to the difference of the selection signal S, the MBCB has two different internal connection modes; the configuration decoder uses 96 exclusive-or gates, 96 comparators and 48 adders in total, and is used for performing both the decoding operation of the 8-bit polarization code and the decoding operation of the LDPC code.