CN108806762A - Storage chip test circuit device and test method - Google Patents
Storage chip test circuit device and test method Download PDFInfo
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- CN108806762A CN108806762A CN201811032357.2A CN201811032357A CN108806762A CN 108806762 A CN108806762 A CN 108806762A CN 201811032357 A CN201811032357 A CN 201811032357A CN 108806762 A CN108806762 A CN 108806762A
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- 238000012360 testing method Methods 0.000 title claims abstract description 104
- 238000010998 test method Methods 0.000 title claims description 12
- 238000007906 compression Methods 0.000 claims abstract description 28
- 230000006835 compression Effects 0.000 claims abstract description 28
- 230000005540 biological transmission Effects 0.000 claims description 71
- 230000005611 electricity Effects 0.000 claims description 6
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- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
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- 238000013144 data compression Methods 0.000 description 3
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- 230000002159 abnormal effect Effects 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention provides a kind of storage chip test circuit device and method, the first test data of the first storage array output is compressed by the first compressor circuit, generates the first compressed data.Second test data of the second storage array output is compressed by the second compressor circuit, generates the second compressed data.Second compression again is carried out using the first compressed data of third compressor circuit pair and the second compressed data, generates third compressed data.The first compressed data of generation can not only be exported, one kind in the second compressed data of output and third compressed data can also be selected by multiplexer.The test result whether storage chip fails is can not only obtain, the first storage array and the test result of the second storage array failure in storage chip can also be obtained, be accurately positioned invalid position.Test machine can obtain the failure conditions of storage chip and storage array by connecting a port, improve testing efficiency.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, and in particular to a kind of storage chip test circuit device and
Test method.
Background technology
With the development of integrated circuit fabrication process, the circuit test for the storage chip being made of multiple storage arrays faces
The problem that amount of test data is big and testing power consumption is excessively high.Usually test data is compressed and is asked to solve amount of test data
Topic.Data compression refers under the premise of not losing information, and reduction data volume improves its transmission, storage to reduce memory space
With a kind of technology for the treatment of effeciency, or refer to and data reorganized according to certain algorithm, reduce data redundancy and
The space of storage.
Under the test pattern of storage chip, each storage array can output test data, it is therefore an objective to test storage battle array
Whether the function of row is normal.As shown in Figure 1, the test data that each storage array 10 is exported passes through four level-one exclusive or respectively
Door 20 carries out first time data compression, generates compressed data D0~D3, then compressed data D0~D3 of each storage array 10 is total
Second of data compression is carried out with by two level XOR gate 30, obtained output result is indicated with bit F, is sentenced by bit F
Whether the test data that disconnected each storage array 10 exports is effective.
However, there are two the shortcomings that adopting this method：First, it can not judge the test number of which storage array output
According to including abnormal data；Second, when the test data of all storage arrays output has exception.It is obtained after two second compressions
The test data of output result judgement all storage arrays output and without exception, and reality and do not meet.For example, working as each
It is 1, D0 by the D0~D3 exported after the first second compression when the test data of storage array output includes abnormal number
The bit F that~D3 is exported after the second second compression is 0, at this point, bit F judgement compressed datas D0~D3 is without exception, and then is sentenced
The test data of fixed all storage array output is without exception, it is clear that do not conform to the actual conditions conjunction.
Disclosed above- mentioned information is only used for reinforcing the understanding of the background to the present invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Invention content
A kind of storage chip test circuit device of present invention offer and test method, to overcome or alleviated by background technology
Existing one or more problem at least provides a kind of beneficial selection.
As one aspect of the present invention, a kind of storage chip test circuit device is provided, including be mounted on storage core
The first compressor circuit component, the second compressor circuit component, third compressor circuit in piece and multiplexer；
The first compressor circuit component includes the first compressor circuit, and the second compressor circuit component includes the second compression
Circuit；
In the storage chip storage array combination in be equipped with the first storage array and the second storage array, described first
Storage array exports the first test data for reading primary data, and second storage array is described initial for reading
Data, and export the second test data；
The first compressor circuit component is used to compress first test data to generate the first compressed data,
The first compressor circuit component include the first input end for being connected to first storage array, for multichannel it is defeated
Go out the first output end and second output terminal of first compressed data, the second output terminal is connected to the third compression electricity
Road；
The second compressor circuit component is for compressing second test data to generate the second compressed data, and described the
Two compressor circuit components include the second input terminal for being connected to second storage array, for the second compression described in multiple-channel output
The third output end and the 4th output end of data, the third output end are connected to the multiplexer, the 4th output
End is connected to the third compressor circuit；
The third compressor circuit is for compressing first compressed data and second compressed data to generate third
Compressed data, the third compressor circuit includes the 5th output end (303) for being connected to the multiplexer, described in output
Third compressed data is to the multiplexer；
The multiplexer includes first via input terminal, the second road input terminal and multiplexing output end, the first via
Input terminal is connected to the 5th output end of the third compressor circuit, and second road input terminal is connected to second pressure
The third output end of contracting circuit unit, the multiplexing output end is for selecting an output second compressed data and described the
One kind in three compressed datas.
Preferably, in above-mentioned storage chip test circuit device, the third compressor circuit includes third input terminal, even
It is connected to the second output terminal, for receiving first compressed data, the third compressor circuit further includes the 4th input terminal,
It is connected to the 4th output end, for receiving second compressed data.
Preferably, in above-mentioned storage chip test circuit device, the first compressor circuit component further includes the first biography
Defeated device, the second compressor circuit component further include the second transmitting device；
First transmitting device is exported for controlling first compressed data to the first compressor circuit component
First output end and the second output terminal；
It is multiple that second transmitting device is connected to second compressor circuit, the third compressor circuit and the multichannel
With device, the third compressor circuit and the multiplexer are transmitted to for controlling second compressed data.
Preferably, in above-mentioned storage chip test circuit device, first transmitting device include the first transmission gate and
Second transmission gate, second transmitting device include third transmission gate and the 4th transmission gate；
First transmission gate is used to that first compressed data to be sent in the third compressor circuit in conducting,
Second transmission gate is used to export first compressed data in conducting, and the third transmission gate is used in conducting
Second compressed data is sent in the third compressor circuit, the 4th transmission gate is used for described the in conducting
Two compressed datas are exported to the multiplexer.
Preferably, in above-mentioned storage chip test circuit device, first compressor circuit includes the first XOR gate, institute
It includes the second XOR gate to state the second compressor circuit.
Preferably, in above-mentioned storage chip test circuit device, the third compressor circuit includes third XOR gate,
Four XOR gates and with door, wherein the Q1 input terminals of the third XOR gate and described be connected to institute with door Q4 input terminals
The first transmission gate is stated, the Q2 input terminals of the third XOR gate and described and door Q3 input terminals are connected to the third and transmit
Door, the Q5 input terminals of the 4th XOR gate are connected to the output end of the third XOR gate, and the Q6 of the 4th XOR gate is defeated
Enter end and be connected to the output end with door, the output end of the 4th XOR gate is connected to described the of the multiplexer
Input terminal all the way.
Preferably, further include the first controller and second controller in above-mentioned storage chip test circuit device, it is described
First controller and the second controller are connected to first transmission gate, second transmission gate, third transmission
Door and the 4th transmission gate；
First controller opens second transmission gate and the 4th transmission gate for controlling, and it is multiple to control the multichannel
Second compressed data is exported with device, simultaneously closes off first transmission gate and the third transmission gate；
The second controller opens first transmission gate and the third transmission gate for controlling, and controls described more
Path multiplexer exports the third compressed data, simultaneously closes off second transmission gate and the 4th transmission gate.
Preferably, in above-mentioned storage chip test circuit device, it is multiple that first controller is additionally coupled to the multichannel
With the control terminal (404) of device, the control terminal of the multiplexer is used to control the multiplexing output end according to control signal and select
Select the one kind exported in second compressed data and the third compressed data.
The present invention also provides a kind of storage chip test methods, including：
First test data of the first storage array output in storage chip is compressed, the first compression number is generated
According to；
Second test data of the second storage array output in the storage chip is compressed, the second compression is generated
Data；
First compressed data and second compressed data are compressed, third compressed data is generated；
Control exports any in first compressed data, second compressed data and the third compressed data
Kind, to judge the failure conditions of first storage array and second storage array.
Preferably, in above-mentioned storage chip test method, control exports first compressed data, second compression
Any one of data and the third compressed data, including：
First compressed data is exported according to first control signal control；
Second compressed data and the third compressed data are input to multiplexer；
The multiplexer, which is controlled, according to second control signal selects an output second compressed data and the third
Compressed data.
The present invention uses above-mentioned technical proposal, has the following advantages that：In the present solution, the first of the output of the first storage array surveys
Examination data are compressed by the first compressor circuit, generate the first compressed data.Second test number of the second storage array output
It is compressed according to by the second compressor circuit, generates the second compressed data.Using the first compressed data of third compressor circuit pair and
Second compressed data carries out second compression again, generates third compressed data.The output of the first compressed data can will be not only generated, may be used also
To select one kind in the second compressed data of output and third compressed data by multiplexer.Sentenced according to the first compressed data
Whether disconnected first storage array fails.Judge whether the second storage array fails according to the second compressed data.It is compressed according to third
Data judge whether storage chip fails.The storage chip test circuit device provided by this programme can not only obtain storage
The test result whether chip fails can also obtain the test result of which of storage chip storage array failure, essence
Determine position invalid position.In addition, the output end of the multiplexer in the storage chip test circuit device that this programme provides can
To be connected in test machine, selection the second compressed data of output or third compressed data are tested.Test machine passes through connection one
A port can access the failure conditions of storage chip, additionally it is possible to obtain the failure conditions of storage array.So that test machine carries
High testing efficiency.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise run through the identical reference numeral of multiple attached drawings and indicate same or analogous
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is painted storage chip test circuit device schematic diagram in background technology.
Fig. 2 is painted the block diagram of storage chip test circuit device provided in an embodiment of the present invention.
Fig. 3 is painted the block diagram of another storage chip test circuit device provided in an embodiment of the present invention.
Fig. 4 is painted a kind of schematic diagram of storage chip test circuit device provided in an embodiment of the present invention.
Fig. 5 is painted the schematic diagram of another storage chip test circuit device provided in an embodiment of the present invention.
Fig. 6 is painted a kind of storage chip test circuit device provided in an embodiment of the present invention and uses schematic diagram
Fig. 7 is painted another storage chip test circuit device provided in an embodiment of the present invention and uses schematic diagram.
Fig. 8 is painted a kind of storage chip test method flow chart provided in an embodiment of the present invention.
Description of the drawings：
Background technology：
10- storage arrays；20- level-one XOR gates；30- two level XOR gates.
The embodiment of the present invention one：
1- storage chips；
The first test interfaces of 11-；The second test interfaces of 22-；
100- storage arrays combine；
The first storage arrays of 110-；
The second storage arrays of 120-；
210- the first compressor circuit components；
The first input end of 213- the first compressor circuit components；
First output end of 214- the first compressor circuit components；
The second output terminal of 215- the first compressor circuit components；
220- the second compressor circuit components；
Second input terminal of 223- the second compressor circuit components；
The third output end of 224- the second compressor circuit components；
4th output end of 225- the second compressor circuit components；
300- third compressor circuits；
The third input terminal of 301- third compressor circuits；
4th input terminal of 302- third compressor circuits；
5th output end of 303- third compressor circuits；
400- multiplexers；401- first via input terminals；
The second roads 402- input terminal；403- is multiplexed output end；
The control terminal of 404- multiplexers.
The embodiment of the present invention two：
The first compressor circuits of 201-；The second compressor circuits of 202-；
The first XOR gates of 211-；The second XOR gates of 212-；
The first transmitting devices of 230-；The second transmitting devices of 240-；
The first transmission gates of 231-；The second transmission gates of 232-；
241- third transmission gates；The 4th transmission gates of 242-；
The first controllers of 510-；520- second controllers.
The embodiment of the present invention three：
130- third storage arrays；The 4th storage arrays of 140-；
The 5th XOR gates of 221-；The 6th XOR gates of 222-；
250- third transmitting devices；The 4th transmitting devices of 260-；
The 6th compressor circuits of 310-.
Specific implementation mode
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on ... shown in the drawings or
Position relationship is merely for convenience of description of the present invention and simplification of the description, and does not indicate or imply the indicated device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；Can be that machinery connects
It connects, can also be electrical connection, can also be communication；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the interaction relationship of the connection or two elements inside two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or "lower"
It may include that the first and second features are in direct contact, can also not be to be in direct contact but pass through it including the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Right over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " include fisrt feature right over second feature and oblique upper, or be merely representative of
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Embodiment one
In a kind of specific embodiment, a kind of storage chip test circuit device, storage chip test electricity are provided
Road device is mounted in storage chip 1.As shown in Fig. 2, storage chip test circuit device includes storage array combination 100, the
One compressor circuit component 210, the second compressor circuit component 220, third compressor circuit 300 and multiplexer 400.
First compressor circuit component 210 includes the first compressor circuit 201, and the second compressor circuit component 202 includes the second pressure
Contracting circuit 202.
It is equipped with the first storage array 110 and the second storage array 120 in storage array combination 100.First storage array 110
For reading primary data, and export the first test data to the first compressor circuit 210.Second storage array 120 is for reading
Primary data, and export the second test data to the second compressor circuit 220.
First compressor circuit component 210 is for compressing the first test data to generate the first compressed data, to allow basis
First compressed data judges whether the first storage array 110 fails.First compressor circuit component 210 includes being connected to the first storage
The first input end 213 of array, the first output end 214 and second output terminal 215 for the first compressed data of multiple-channel output, the
Two output ends 215 are connected to third compressor circuit 300.
Second compressor circuit component 220 is for compressing the second test data to generate the second compressed data, to allow basis
Second compressed data judges whether the second storage array 110 fails.Second compressor circuit component 220 includes being connected to the second storage
Second input terminal 223 of array, third output end 224 and the 4th output end 225 for the second compressed data of multiple-channel output, the
Three output ends 224 are connected to multiplexer 400, and the 4th output end 225 is connected to third compressor circuit 300.
Third compressor circuit 300 be used to compress the first compressed data and the second compressed data any one to generate third pressure
Contracting data.Third compressor circuit 300 includes the 5th output end 303 for being connected to multiplexer 400, compresses number to export third
According to multiplexer 400.Third compressor circuit 300 further includes third input terminal 301, is connected to second output terminal 215, is used for
Receive the first compressed data.Third compressor circuit 300 further includes the 4th input terminal 302, is connected to the 4th output end 225, is used for
Receive the second compressed data.
Multiplexer 400 includes first via input terminal 401, the second road input terminal 402, multiplexing output end 403, Yi Jiduo
The control terminal 404 of path multiplexer.First via input terminal 401 is connected to the 5th output end 303 of third compressor circuit 300, and second
Road input terminal 402 is connected to the third output end 224 of the second compressor circuit component 202.The control terminal 404 of multiplexer 400
Signal is controlled for receiving, and according to the control signal control multiplexing selection of output end 403 the second compressed data of output and third pressure
One kind in contracting data.Third compressed data can be used for judging whether storage chip 1 fails.
First output end 214 of the first compressor circuit component 210 is connected to the first test interface 11, can be surveyed by first
Mouth 11 of trying is connected on test machine, and test machine uses any test machine known in the art.Test machine passes through the first compression number
According to judging whether the first storage array fails.Multiplexing output end 403 is connected to the second test interface 22, can be surveyed by second
Mouth 22 of trying is connected on test machine, and test machine judges second by receiving the second compressed data and/or third compressed data
Whether storage array 120 and storage chip 1 fail.Due to the limited amount of the connecting test port of test machine, so this implementation
The storage chip test circuit device that example provides improves the test port utilization rate of test machine, not only right by two output ends
Storage chip 1 is whole to have carried out failure testing, but also to internal the first storage array 110 and the second storage array 120 into
Row failure testing.It is accurately positioned invalid position, improves testing efficiency.
It should be pointed out that 100 inside of storage array combination includes but not limited to the first storage battle array in above-described embodiment
Row 110 and the second storage array 120 can also include more storage arrays, and the quantity of storage array is by storage chip 1
Memory size determines.
It should be pointed out that the first compressor circuit 201 is only one of first compressor circuit component 210 of the invention
Embodiment, the second compressor circuit 202 are only one of the first compressor circuit component 220 of the invention embodiment, Qi Taneng
Enough realize the circuit of compression function in the protection domain of the present embodiment.
Embodiment two
In another embodiment specific implementation mode, as shown in figure 3, the first compressor circuit component 210 further includes the first transmission dress
230 are set, the second compressor circuit component 220 further includes the second transmitting device 240.First transmitting device 230 is connected to the first compression
Circuit 201 is exported for controlling the first compressed data to the first output end of the first compressor circuit component or the first compressor circuit
The second output terminal of component.Second transmitting device 240 is connected to the second compressor circuit 202, third compressor circuit 300 and multichannel
Multiplexer 400 is transmitted to third compressor circuit 300 and multiplexer 400 for controlling the second compressed data.
Specifically, as shown in figure 4, the first compressor circuit 210 includes the first XOR gate 211, the second compressor circuit 220 includes
Second XOR gate 212.First transmitting device 230 includes the first transmission gate 231 and the second transmission gate 232, the second transmitting device 240
Including third transmission gate 241 and the 4th transmission gate 242.First transmission gate 231 is used to send the first compressed data in conducting
Into third compressor circuit 300, the second transmission gate 232 is used to export the first compressed data, and third transmission gate 241 is for leading
Second compressed data is sent in third compressor circuit 300 when logical, the 4th transmission gate 242 is used for the second compression in conducting
Data are exported to multiplexer 400.
It should be pointed out that the first compressor circuit and the first transmitting device together constitute the one of the first compressor circuit component
The one embodiment for the second compressor circuit component that a embodiment, the second compressor circuit and the second transmitting device collectively form.
Third compressor circuit 300 include third XOR gate 312, the 4th XOR gate 313 and with door 311, wherein third is different
Or door 312 Q1 input terminals and the output of the first transmission gate 231 is connected to the Q4 input terminals of door 311, third XOR gate 312
Q2 input terminals and the output of third transmission gate 241 is connected to the Q3 input terminals of door 311, the Q5 of the 4th XOR gate 313 is defeated
Enter the output end T1 that end is connected to third XOR gate 312, the Q6 input terminals of the 4th XOR gate 313 are connected to the output with door 311
T2, the output end T3 of the 4th XOR gate 313 is held to be connected to the first via input terminal 401 of multiplexer 400.
It should be pointed out that the first compressor circuit 210 includes but not limited to first XOR gate 211 of above-described embodiment, the
Two compressor circuits 220 include but not limited to second XOR gate 212 of above-described embodiment, and third compressor circuit 300 includes but unlimited
The device and connection type provided in above-described embodiment, can also be other types of device and connection type, Neng Goushi
Now to the compression function of data, in the protection domain of the present embodiment.
On the basis of the above embodiments, as shown in figure 4, storage chip test circuit device further includes the first controller
510 and second controller 520.First controller 510 and second controller 520 are connected to the transmission of the first transmission gate 231, second
Door 232, third transmission gate 241 and the 4th transmission gate 242.
As shown in fig. 6, the first controller 510 opens the second transmission gate 232 for controlling, the first compression number is directly exported
According to.First controller 510 is additionally operable to control and opens the 4th transmission gate 242, and controls the output of multiplexer 400 second compression number
According to.Meanwhile first controller 510 be additionally operable to close the first transmission gate 231 and third transmission gate 241, prevent third compression electricity
Road 300 carries out second-compressed to the first compressed data and the second compressed data.
As shown in fig. 7, second controller 520 opens the first transmission gate 231 and third transmission gate 241 for controlling, to permit
Perhaps the first compressed data and the second compressed data, which are input in third compressor circuit 300, carries out second compression again, the third pressure of generation
Contracting data are input in multiplexer 400.Second controller 520 is additionally operable to control multiplexer 400 and exports third compression
Data.Meanwhile second controller 520 is additionally operable to control and closes the second transmission gate 232 and the 4th transmission gate 242, has obstructed first
The direct output of compressed data and the second compressed data.
On the basis of the above embodiments, the first controller 510 is additionally coupled to the control terminal 404 of multiplexer, multichannel
The control terminal 404 of multiplexer is used for according to the control signal control multiplexing selection of output end 403 the second compressed data of output and third
One kind in compressed data.
Embodiment three
In another embodiment specific implementation mode, on the basis of the above embodiments, one group of storage chip test electricity is increased
Road device.As shown in figure 5, further including third storage array 130, the 4th storage array 140 and the 5th XOR gate the 221, the 6th
XOR gate 222, third transmitting device 250, the 4th transmitting device 260, the 6th compressor circuit 310 and multiplexer 400.The
Five XOR gates 221 and the 6th XOR gate 222 carry out one stage of compression, and the 6th compressor circuit 310 carries out two-stage compression.Above-mentioned device
Connection type is same as the previously described embodiments, and details are not described herein.
It should be pointed out that the present embodiment includes but not limited to above-mentioned one newly increased group storage chip test circuit dress
Set, according to the test port quantity of test machine and other actual conditions to the quantity of storage chip test circuit device and
Connection type is adaptively adjusted, within the protection domain of the present embodiment.
Example IV
In another embodiment specific implementation mode, a kind of storage chip test method is provided, above-mentioned implementation is can be applied to
The storage chip test circuit device that example provides.As shown in figure 8, storage chip test method includes：
Step S100：First test data of the first storage array output in storage chip is compressed, generates the
One compressed data.
Step S200：Second test data of the second storage array output in storage chip is compressed, generates the
Two compressed datas.
Step S300：First compressed data and the second compressed data are compressed, third compressed data is generated.
Step S400：Any one of the first compressed data of control output, the second compressed data and third compressed data,
To judge the failure conditions of the first storage array and the second storage array.
In above-mentioned storage chip test method, the first compressed data of control output, the second compressed data and third pressure
Any one of contracting data, including：
The first compressed data of output is controlled according to first control signal；
Second compressed data and third compressed data are input to multiplexer；
Multiplexer, which is controlled, according to second control signal selects second compressed data of output and third compressed data.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (10)
1. a kind of storage chip test circuit device, which is characterized in that include the first compressor circuit in storage chip
Component, the second compressor circuit component, third compressor circuit and multiplexer；
The first compressor circuit component includes the first compressor circuit, and the second compressor circuit component includes the second compression electricity
Road；
The first storage array and the second storage array, first storage are equipped in storage array combination in the storage chip
Array exports the first test data for reading primary data, and second storage array is used to read the primary data,
And export the second test data；
The first compressor circuit component is for compressing first test data to generate the first compressed data, first pressure
Contracting circuit unit includes the first input end for being connected to first storage array, for the first compressed data described in multiple-channel output
The first output end and second output terminal, the second output terminal be connected to the third compressor circuit；
The second compressor circuit component is for compressing second test data to generate the second compressed data, second pressure
Contracting circuit unit includes the second input terminal for being connected to second storage array, for the second compressed data described in multiple-channel output
Third output end and the 4th output end, the third output end is connected to the multiplexer, and the 4th output end connects
It is connected to the third compressor circuit；
The third compressor circuit is for compressing first compressed data and second compressed data to generate third compression
Data, the third compressor circuit include the 5th output end for being connected to the multiplexer, are compressed with exporting the third
Data are to the multiplexer；
The multiplexer includes first via input terminal, the second road input terminal and multiplexing output end, the first via input
End is connected to the 5th output end of the third compressor circuit, and second road input terminal is connected to the second compression electricity
The third output end of road component, the multiplexing output end is for selecting an output second compressed data and the third pressure
One kind in contracting data.
2. storage chip test circuit device as described in claim 1, which is characterized in that the third compressor circuit includes the
Three input terminals are connected to the second output terminal, and for receiving first compressed data, the third compressor circuit further includes
4th input terminal is connected to the 4th output end, for receiving second compressed data.
3. storage chip test circuit device as described in claim 1, which is characterized in that the first compressor circuit component is also
Including the first transmitting device, the second compressor circuit component further includes the second transmitting device；
First transmitting device is exported for controlling first compressed data to described in the first compressor circuit component
First output end and the second output terminal；
Second transmitting device is connected to second compressor circuit, the third compressor circuit and the multiplexing
Device is transmitted to the third compressor circuit and the multiplexer for controlling second compressed data.
4. storage chip test circuit device as claimed in claim 3, which is characterized in that first transmitting device includes the
One transmission gate and the second transmission gate, second transmitting device include third transmission gate and the 4th transmission gate；
First transmission gate is used to that first compressed data to be sent in the third compressor circuit in conducting, described
Second transmission gate is used to export first compressed data in conducting, and the third transmission gate is used for will be described in conducting
Second compressed data is sent in the third compressor circuit, and the 4th transmission gate is used to compress described second in conducting
Data are exported to the multiplexer.
5. storage chip test circuit device as claimed in claim 3, which is characterized in that first compressor circuit includes the
One XOR gate, second compressor circuit include the second XOR gate.
6. storage chip test circuit device as claimed in claim 4, which is characterized in that the third compressor circuit includes the
Three XOR gates, the 4th XOR gate and with door, wherein Q1 input terminals of the third XOR gate and described with door Q4 input terminals
It is connected to first transmission gate, the Q2 input terminals of the third XOR gate and described and door Q3 input terminals are connected to institute
Third transmission gate is stated, the Q5 input terminals of the 4th XOR gate are connected to the output end of the third XOR gate, and the described 4th is different
Or the Q6 input terminals of door are connected to the output end with door, the output end of the 4th XOR gate is connected to the multiplexing
The first via input terminal of device.
7. storage chip test circuit device as claimed in claim 4, which is characterized in that further include the first controller and second
Controller, first controller and the second controller are connected to first transmission gate, second transmission gate, institute
State third transmission gate and the 4th transmission gate；
First controller opens second transmission gate and the 4th transmission gate for controlling, and controls the multiplexer
Second compressed data is exported, first transmission gate and the third transmission gate are simultaneously closed off；
The second controller opens first transmission gate and the third transmission gate for controlling, and it is multiple to control the multichannel
The third compressed data is exported with device, simultaneously closes off second transmission gate and the 4th transmission gate.
8. storage chip test circuit device as claimed in claim 7, which is characterized in that first controller is additionally coupled to
The control terminal of the multiplexer, the control terminal of the multiplexer are used to control the multiplexing according to control signal and export
End selection exports one kind in second compressed data and the third compressed data.
9. a kind of storage chip test method, which is characterized in that including：
First test data of the first storage array output in storage chip is compressed, the first compressed data is generated；
Second test data of the second storage array output in the storage chip is compressed, the second compression number is generated
According to；
First compressed data and second compressed data are compressed, third compressed data is generated；
Control exports any one of first compressed data, second compressed data and described third compressed data,
To judge the failure conditions of first storage array and second storage array.
10. storage chip test method as claimed in claim 9, which is characterized in that control output first compressed data,
Any one of second compressed data and the third compressed data, including：
First compressed data is exported according to first control signal control；
Second compressed data and the third compressed data are input to multiplexer；
The multiplexer, which is controlled, according to second control signal selects an output second compressed data and third compression
Data.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811032357.2A CN108806762B (en) | 2018-09-05 | 2018-09-05 | Memory chip test circuit device and test method |
| PCT/CN2019/101883 WO2020048318A1 (en) | 2018-09-05 | 2019-08-22 | Memory test circuit apparatus and test method |
| US17/124,198 US11715543B2 (en) | 2018-09-05 | 2020-12-16 | Memory test circuit apparatus and test method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811032357.2A CN108806762B (en) | 2018-09-05 | 2018-09-05 | Memory chip test circuit device and test method |
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| CN108806762A true CN108806762A (en) | 2018-11-13 |
| CN108806762B CN108806762B (en) | 2023-10-20 |
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| CN108806762B (en) | 2023-10-20 |
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