CN108763120B - Multi-channel serial port management device and method based on FPGA - Google Patents
Multi-channel serial port management device and method based on FPGA Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention provides a multi-channel serial port management device and method based on an FPGA, comprising an FPGA, an external selector, a first serial interface, a TTL level conversion chip and a CPU group; the external selector and the CPU group are connected with the FPGA; one end of the TTL level conversion chip is connected with the first serial interface, and the other end of the TTL level conversion chip is connected with the FPGA. The invention has the advantages that: the number of external serial ports is reduced, serial port faults can be reported in time, and the maintenance cost of equipment is reduced.
Description
Technical Field
The invention relates to a serial port management device and method, in particular to a multi-channel serial port management device and method based on an FPGA.
Background
The debugging through the serial port is a common debugging mode in daily maintenance of equipment, and for large-scale equipment with a plurality of serial ports, a plurality of subsystems are often arranged in the equipment and respectively correspond to the serial ports used for debugging. In the prior art, for a device having a plurality of subsystems, a plurality of serial ports are usually provided on a motherboard, however, for the whole device, due to the limitation of structure or appearance, the serial ports cannot be externally connected at the same time.
Under the condition that a plurality of serial ports cannot be externally connected at the same time, when an individual subsystem needs to be maintained, the following two methods exist: one is to access by telnet mode, and the other is to open the case and connect the corresponding serial port for maintenance. However, both of these methods have the following drawbacks: in the first method, if the subsystem network port cannot communicate or the telnet service is not opened by default, the subsystem cannot be accessed externally; in the second method, the case is opened, so that maintenance cost is increased, and when the serial port of the subsystem in the equipment fails, the specific serial port cannot be reported in time.
Through searching, the Chinese patent application with the application date of 2016.01.28 and the application number of 201610058904.9 discloses a multi-channel serial port communication system and method based on an FPGA, wherein each channel of serial port of the FPGA is connected with one latch in a one-to-one correspondence manner; each readable and writable memory chip is connected with at least one latch; the latches are utilized to receive the first address signals and the first service data in a time-sharing manner, namely the same signal lines can be utilized to transmit the first address signals and the first service data in a time-sharing manner between the latches and the serial ports in a one-to-one correspondence manner, and therefore the number of the signal lines can be reduced. The invention has the following problems: each serial port corresponds to one latch, and the structure is complex; the same signal lines are used for transmitting data in time intervals, but the number of serial ports which need to be externally connected is not reduced.
Disclosure of Invention
One of the technical problems to be solved by the invention is to provide a multi-channel serial port management device based on an FPGA, which is used for reducing the number of serial port external connections, reporting serial port faults in time and reducing maintenance cost.
The invention is realized in the following way: a multi-channel serial port management device based on FPGA comprises an FPGA, an external selector, a first serial interface, a TTL level conversion chip and a CPU group; the external selector and the CPU group are connected with the FPGA; one end of the TTL level conversion chip is connected with the first serial interface, and the other end of the TTL level conversion chip is connected with the FPGA.
Further, the FPGA comprises a second serial interface, a third serial interface group, a dial value reading interface, a decoder and an I2C interface; one end of the second serial interface is connected with the TTL level conversion chip, and the other end of the second serial interface is connected with the decoder; one end of the third serial interface group is connected with the decoder, and the other end of the third serial interface group is connected with the CPU group; the input end of the dial value reading interface is connected with the external selector, and the output end is connected with the CPU group; and the I2C interface is connected with the CPU group.
Further, the decoder is provided with a first register, a second register and a third register.
Further, the external selector is a dial switch, a band switch or a micro switch.
Further, the first serial interface is an RS232 interface.
Further, the TTL level conversion chip is a TTL232 chip.
Further, the CPU group comprises a main CPU and a plurality of auxiliary CPUs; and the main CPU and the auxiliary CPU are connected with the FPGA.
The second technical problem to be solved by the invention is to provide a multi-channel serial port management method based on an FPGA, serial port gating is performed according to an external selector by the method, the number of external serial ports is reduced, the current inactive serial port is polled by a background, and faults are reported in time.
The invention is realized in the following way: the method for managing the multiple serial ports based on the FPGA needs to use the management device, and comprises the following steps of:
s1, the FPGA assigns a first initial value to a third register;
s2, dialing an external selector to select a serial port needing communication;
step S3, the dial value reading interface reads the level signal of the external selector, carries out debouncing processing on the level signal of the external selector, judges whether the level signal of the external selector is effective, and if so, enters step S6; if not, adding one to the value of the third register, and entering a step S4;
step S4, judging whether the value of the third register exceeds a set threshold value, and if not, entering step S2; if yes, a first initial value is given to a third register, an error event is generated, and step S5 is carried out;
s5, reporting an error event to the main CPU, and ending the flow;
step S6, transmitting the level signal of the external selector to a decoder, converting the level signal into serial numbers needing gating by the decoder, and storing the serial numbers needing gating into a first register; meanwhile, switching the communication signal to a serial port with a corresponding serial number, judging whether the serial port communicates normally, and ending the flow after the communication is completed if the external physical serial port communicates normally with the switched internal serial port; if normal communication is not possible and an error event is generated, the process proceeds to step S5.
Further, the method also comprises the step of background polling the current inactive serial port, and comprises the following steps:
step S10, the FPGA assigns a second initial value to the second register, judges whether the value of the second register is equal to the value of the first register, if not, sends a query instruction to the currently polled serial port, and enters step S20; if so, go to step S30;
step S20, the FPGA judges the return content of the currently polled serial port, and if the return content is a correct command response, the step S30 is entered; if the command is not returned to answer correctly, an INT interrupt is sent to the main CPU, and the current polled serial port fault is reported to the main CPU and the current active serial port;
step S30, the FPGA adds one to the second register value, judges whether the second register value exceeds the total serial number, and if so, enters step S10;
if not, judging whether the value of the first register is changed, and if so, entering step S10; if not, ending the flow.
The invention has the advantages that:
1. the serial port signal is gated through the external selector, so that the number of serial port external connections is reduced, and the device can be made smaller and more portable.
2. And by the background polling of the FPGA, the serial port of which subsystem has faults can be obtained, and the serial port faults can be reported in time.
3. The external selector is used for gating serial port signals, when equipment fails, the equipment can be directly connected with a corresponding serial port for debugging and maintenance, and when a subsystem network port cannot communicate or telnet service is not started, the equipment can be debugged without opening a case, so that maintenance cost is reduced.
4. Centralized detection, channel switching, centralized information transmission and issuing configuration are carried out through the FPGA, so that excessive time occupied by CPU is avoided when the number of serial ports is large, CPU resource loss is effectively reduced, efficiency is improved, the FPGA belongs to hardware language, and the speed is high.
5. The external selector signal is received to the CPU group through the FPGA, so that the influence of electrification stirring on the CPU group is avoided.
6. The FPGA queries the state of the third serial interface group, so that the serial port state of the subsystem is polled in the background, the intervention of a main CPU is not needed, and the resources are saved.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a multi-channel serial port management device based on an FPGA of the present invention.
FIG. 2 is a flow chart of serial gating according to the present invention for an external selector.
FIG. 3 is a flow chart of background polling of a currently inactive serial port in accordance with the present invention.
Description of the drawings:
the system comprises a 100-serial port management device, a 1-FPGA, a 2-first serial interface, a 3-TTL level conversion chip, a 4-external selector, a 5-CPU group, a 11-second serial interface, a 12-third serial interface, a 13-dial value reading interface, a 14-decoder, a 141-first register, a 142-second register, a 143-third register, a 15-I2C interface, a 51-main CPU and a 52-auxiliary CPU.
Detailed Description
Referring to fig. 1 to 3, a preferred embodiment of a multi-channel serial port management device 100 based on FPGA of the present invention includes an FPGA1, an external selector 4, a first serial port 2, a TTL level shift chip 3, and a CPU group 5; the external selector 4 and the CPU group 5 are connected with the FPGA 1; one end of the TTL level conversion chip 3 is connected with the first serial interface 2, and the other end is connected with the FPGA 1; the serial port signal is gated through the external selector 4, so that the number of serial port external connections is reduced, the equipment can be made smaller and more portable, and when the equipment space is limited, the external selector 4 and the first serial interface 2 can be integrated together; the FPGA1 is used for carrying out centralized detection, channel switching, centralized information transmission and issuing configuration, so that excessive time for occupying a CPU by polling one by one when the number of serial ports is large is avoided, CPU resource loss is effectively reduced, efficiency is improved, and the FPGA1 belongs to hardware language and has high speed.
The FPGA1 includes a second serial interface 11, a third serial interface group 12, a dial value reading interface 13, a decoder 14, and an I2C interface 15; one end of the second serial interface 11 is connected with the TTL level conversion chip 3, and the other end is connected with the decoder 14; one end of the third serial interface group 12 is connected with the decoder 14, the other end is connected with the CPU group 5, and the decoder 14 is used for gating the logic unit; the input end of the dial value reading interface 13 is connected with the external selector 4, and the output end is connected with the CPU group 5; the dial value reading interface 13 is used for reading the dial value of the external selector 4; the I2C interface 15 is connected to the CPU group 5, specifically, connected to the main CPU51, and configured to receive serial port fault information reported by the FPGA1 by the main CPU51 and issue a control instruction to the FPGA1 by the main CPU 51.
The decoder 14 is provided with a first register 141, a second register 142 and a third register 143; the first register 141 is used for storing a current serial number, the second register 142 is used for storing a background query serial number, and the third register 143 is used for storing flag bit information.
The external selector 4 is a dial switch, a band switch or a micro switch; the signal of the external selector 4 is received to the CPU group 5 through the FPGA14, so that the influence of electrification stirring on the CPU group 5 is avoided; the TVS tube is designed at the output end of the dial switch for protection, so that the influence of peak interference or surge on the interface of the FPGA1 when the switch is toggled is prevented, and even if the dial switch is constantly toggled under the condition of power-on, the FPGA1 and the CPU group 5 at the later stage can be protected from being damaged; the external selector 4 can access 2 only by n segments n And each internal serial port (n is a positive integer), and the marginal cost is low when the internal serial port routing requirement is increased.
The first serial interface 2 is an RS232 interface.
The TTL level conversion chip 3 is a TTL232 chip, and is configured to convert a signal transmitted by the RS232 interface into a TTL level signal.
The CPU set 5 includes a main CPU51 and a plurality of auxiliary CPUs 52; the main CPU51 and the sub CPU52 are connected to the FPGA1, and the main CPU51 uses the MT7621A of MediaTek.
The preferred embodiment of the multi-channel serial port management method based on the FPGA comprises the following steps of:
step S1, the FPGA1 assigns a first initial value to the third register 143, wherein the first initial value is 0;
s2, dialing the external selector 4 to select the serial port needing communication, and the external selector 4 can access 2 only by n segments n Internal serial ports (n is a positive integer);
step S3, the dial value reading interface 13 reads the level signal of the external selector 4, carries out debouncing processing on the level signal of the external selector 4, prevents voltage fluctuation of the external selector 4 in the toggle process, judges whether the level signal of the external selector 4 is effective, and if so, enters step S6; if not, the value of the third register 143 is incremented by one, and the process proceeds to step S4;
step S4, judging whether the value of the third register 143 exceeds a set threshold value, and if not, proceeding to step S2; if yes, the first initial value is given to the third register 143, an error event is generated, and the step S5 is performed;
step S5, reporting the error event to the main CPU51, and ending the flow;
step S6, the level signal of the external selector 4 is transmitted to the decoder 14, the decoder 14 converts the level signal into serial numbers to be gated, and the serial numbers to be gated are stored in the first register 141; meanwhile, switching the communication signal to a serial port with a corresponding serial number, judging whether the serial port communicates normally, and ending the flow after the communication is completed if the external physical serial port communicates normally with the switched internal serial port; if normal communication is not possible and an error event is generated, the process proceeds to step S5.
The method also comprises the step of background polling of the current inactive serial port, and comprises the following steps:
step S10, the FPGA1 assigns a second initial value to the second register 142, wherein the second initial value represents the serial number of the current polling in the background, the second initial value is 1, the polling starts from the first serial port, whether the value of the second register 142 is equal to the value of the first register 141 or not is judged, if not, a query instruction is sent to the current polling serial port, and the step S20 is carried out; if so, go to step S30;
step S20, the FPGA1 judges the return content of the currently polled serial port, and if the return content is a correct command response, the step S30 is entered; if the command is not returned to answer correctly, an INT interrupt is sent to the main CPU51, and the current polled serial port fault is reported to the main CPU51 and the current active serial port;
step S30, the FPGA1 adds one to the value of the second register 142, and judges whether the value of the second register 142 exceeds the total serial number, if yes, the step S10 is entered;
if not, judging whether the value of the first register 141 is changed, if so, proceeding to step S10, and restarting polling in the background after the serial port is reselected by the external selector 4; if not, ending the flow.
In summary, the invention has the advantages that:
1. the serial port signal is gated through the external selector, so that the number of serial port external connections is reduced, and the device can be made smaller and more portable.
2. And by the background polling of the FPGA, the serial port of which subsystem has faults can be obtained, and the serial port faults can be reported in time.
3. The external selector is used for gating serial port signals, when equipment fails, the equipment can be directly connected with a corresponding serial port for debugging and maintenance, and when a subsystem network port cannot communicate or telnet service is not started, the equipment can be debugged without opening a case, so that maintenance cost is reduced.
4. Centralized detection, channel switching, centralized information transmission and issuing configuration are carried out through the FPGA, so that excessive time occupied by CPU is avoided when the number of serial ports is large, CPU resource loss is effectively reduced, efficiency is improved, the FPGA belongs to hardware language, and the speed is high.
5. The external selector signal is received to the CPU group through the FPGA, so that the influence of electrification stirring on the CPU group is avoided.
6. The FPGA queries the state of the third serial interface group, so that the serial port state of the subsystem is polled in the background, the intervention of a main CPU is not needed, and the resources are saved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (6)
1. The utility model provides a multichannel serial ports management device based on FPGA which characterized in that: the system comprises an FPGA, an external selector, a first serial interface, a TTL level conversion chip and a CPU group; the external selector and the CPU group are connected with the FPGA; one end of the TTL level conversion chip is connected with the first serial interface, and the other end of the TTL level conversion chip is connected with the FPGA;
the FPGA comprises a second serial interface, a third serial interface group, a dial value reading interface, a decoder and an I2C interface; one end of the second serial interface is connected with the TTL level conversion chip, and the other end of the second serial interface is connected with the decoder; one end of the third serial interface group is connected with the decoder, and the other end of the third serial interface group is connected with the CPU group; the input end of the dial value reading interface is connected with the external selector, and the output end is connected with the CPU group; the I2C interface is connected with the CPU group;
the external selector is a dial switch, a band switch or a micro switch.
2. The FPGA-based multi-port serial management device of claim 1, wherein: the decoder is provided with a first register, a second register and a third register.
3. The FPGA-based multi-port serial management device of claim 1, wherein: the first serial interface is an RS232 interface.
4. The FPGA-based multi-port serial management device of claim 1, wherein: the TTL level conversion chip is a TTL232 chip.
5. The FPGA-based multi-port serial management device of claim 1, wherein: the CPU group comprises a main CPU and a plurality of auxiliary CPUs; and the main CPU and the auxiliary CPU are connected with the FPGA.
6. A multi-channel serial port management method based on FPGA is characterized in that: the method needs to use the management device according to any one of claims 1 to 5, and the method includes serial port gating according to an external selector, including the following steps:
s1, the FPGA assigns a first initial value to a third register;
s2, dialing an external selector to select a serial port needing communication;
step S3, the dial value reading interface reads the level signal of the external selector, carries out debouncing processing on the level signal of the external selector, judges whether the level signal of the external selector is effective, and if so, enters step S6; if not, adding one to the value of the third register, and entering a step S4;
step S4, judging whether the value of the third register exceeds a set threshold value, and if not, entering step S2; if yes, a first initial value is given to a third register, an error event is generated, and step S5 is carried out;
s5, reporting an error event to the main CPU, and ending the flow;
step S6, transmitting the level signal of the external selector to a decoder, converting the level signal into serial numbers needing gating by the decoder, and storing the serial numbers needing gating into a first register; meanwhile, switching the communication signal to a serial port with a corresponding serial number, judging whether the serial port communicates normally, and ending the flow after the communication is completed if the external physical serial port communicates normally with the switched internal serial port; if the communication cannot be normally performed, generating an error event, and entering step S5;
the method also comprises the step of background polling of the current inactive serial port, and comprises the following steps:
step S10, the FPGA assigns a second initial value to the second register, judges whether the value of the second register is equal to the value of the first register, if not, sends a query instruction to the currently polled serial port, and enters step S20; if so, go to step S30;
step S20, the FPGA judges the return content of the currently polled serial port, and if the return content is a correct command response, the step S30 is entered; if the command is not returned to answer correctly, an INT interrupt is sent to the main CPU, and the current polled serial port fault is reported to the main CPU and the current active serial port;
step S30, the FPGA adds one to the second register value, judges whether the second register value exceeds the total serial number, and if so, enters step S10;
if not, judging whether the value of the first register is changed, and if so, entering step S10; if not, ending the flow.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104866452A (en) * | 2015-05-19 | 2015-08-26 | 哈尔滨工业大学(鞍山)工业技术研究院 | Multi-serial port extension method based on FPGA and TL16C554A |
| CN107908582A (en) * | 2017-11-06 | 2018-04-13 | 杭州宏杉科技股份有限公司 | Serial ports switching device and storage device |
| CN208766645U (en) * | 2018-08-03 | 2019-04-19 | 福建星网智慧科技股份有限公司 | A kind of multi-channel serial port managing device based on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104866452A (en) * | 2015-05-19 | 2015-08-26 | 哈尔滨工业大学(鞍山)工业技术研究院 | Multi-serial port extension method based on FPGA and TL16C554A |
| CN107908582A (en) * | 2017-11-06 | 2018-04-13 | 杭州宏杉科技股份有限公司 | Serial ports switching device and storage device |
| CN208766645U (en) * | 2018-08-03 | 2019-04-19 | 福建星网智慧科技股份有限公司 | A kind of multi-channel serial port managing device based on FPGA |
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