CN111666242B - Multi-channel communication system based on FT platform LPC bus - Google Patents

Multi-channel communication system based on FT platform LPC bus Download PDF

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CN111666242B
CN111666242B CN202010517514.XA CN202010517514A CN111666242B CN 111666242 B CN111666242 B CN 111666242B CN 202010517514 A CN202010517514 A CN 202010517514A CN 111666242 B CN111666242 B CN 111666242B
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bus
interrupt
data
module
chip
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CN111666242A (en
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唐湘衡
邓勇
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Hunan Zetian Zhihang Electronic Technology Co ltd
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Hunan Zetian Zhihang Electronic Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3852—Converter between protocols

Abstract

The invention provides a multi-channel communication system based on a Feiteng platform LPC bus, which is characterized in that a programmable logic device supporting multiple level standards is used as a communication data intermediate processing module between a Feiteng chip and a plurality of external devices, so that a level conversion chip and a protocol conversion chip are omitted, and the Feiteng chip can access a plurality of types of external devices through one LPC bus. The circuit structure of the multi-channel communication system is simple, the manufacturing cost is low, and meanwhile, the main modules of the multi-channel communication system are integrated in the programmable logic device, and only one LPC bus is needed to transmit data of the Feiteng chip, so that the multi-channel communication system is easy to expand, high in real-time performance, good in portability, low in hardware resource requirement, and capable of remarkably reducing software workload, and the multi-layer requirements of an application system are greatly met.

Description

Multi-channel communication system based on FT platform LPC bus
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a multi-channel communication system based on a Feiteng platform LPC bus.
Background
The LPC (Low Pin Count, Low Pin interface) bus is a bus protocol proposed by intel corporation, and is mainly applied to the chip accessing external devices. The LPC bus is used in the communication between the Feiteng chip and the external equipment, because the Feiteng chip has defects, an LPC interface of the Feiteng chip can only access 4-byte aligned addresses, and the LPC interface voltage of the Feiteng chip is not matched with the external equipment, so that the Feiteng chip cannot be directly communicated with the external equipment through the LPC bus, but an information conversion module is required to be directly added to the Feiteng chip and the external equipment to convert information output by the LPC interface of the Feiteng chip into information matched with the external equipment.
In some applications of the FT chip, communication of devices with different interface types needs to be simultaneously realized through an LPC bus, and if the requirement is realized by directly adopting a mode of a single level conversion chip and a protocol conversion chip according to the existing general mode, hardware overhead and software overhead are increased, hardware cost is directly increased, and software operation cost is also indirectly increased.
Disclosure of Invention
In view of this, the present invention provides a multi-channel communication system based on a FT platform LPC bus, so as to solve the problem that in the prior art, when realizing the communication between a FT chip and a multi-channel external device, too much hardware overhead and software overhead are required to be added, which increases the cost.
A multi-channel communication system based on a Feiteng platform LPC bus comprises: a FT chip, a programmable logic device, and a plurality of external devices,
the Feiteng chip is connected with the programmable logic device through a LPC bus, a plurality of output ports of the programmable logic device are respectively connected with corresponding external equipment through corresponding standard buses,
wherein the programmable logic device supports multiple level standards, an LPC slave module, a matching conversion module, an address allocation module and a plurality of driving IP cores corresponding to a plurality of external devices are integrated in the programmable logic device, the LPC slave module supports IO read-write operation,
the first data frame sent by the Feiteng chip is transmitted to the LPC slave module through the LPC bus, the LPC slave module transmits data bit information and address bit information in the first data frame to the matching conversion module,
the matching conversion module converts the data bit information and the address bit information into a second data frame matched with the first ICB bus, and the second data frame is transmitted to the address distribution module through the first ICB bus,
the address distribution module divides the address in the second data frame into a plurality of address spaces and distributes each address space to each driving IP core module through each second ICB bus respectively,
and the driving signals output by the driving IP module core are respectively connected with the corresponding external equipment through the corresponding standard bus.
Preferably, the first ICB bus and the second ICB bus are both integrated within the programmable logic device.
Preferably, the data transmission mode of the multi-path communication system is a polling mode or an interrupt mode.
Preferably, the interrupt signal output by the driver IP core module is connected to the LPC slave module via an interrupt bus, and the interrupt bus is matched with an interrupt bus interface of the LPC slave module.
Preferably, the driving IP core module includes: an ICB bus interface configuration unit, a transmission FIFO unit, a reception FIFO unit and a data transmission/reception state machine unit,
the ICB bus interface configuration unit is configured to read and write the second ICB bus and output corresponding control signals to the transmission FIFO unit, the reception FIFO unit and the data transmission/reception state machine unit so as to control the units to perform corresponding functional operations,
the state information of the external equipment received by the data sending/receiving state machine unit through the standard bus is input to the second ICB bus after passing through the receiving FIFO unit and the ICB bus interface configuration unit,
the data instruction information data in the second ICB bus is sent to the external equipment through the standard bus after passing through the ICB bus interface configuration unit, the transmission FIFO unit and the data transmission/reception state machine unit,
the status information data received by the data transmission/reception state machine unit is read by the second ICB bus via the reception FIFO unit, the ICB bus interface configuration unit,
the receive FIFO unit also generates the interrupt signal based on the received status information data, the interrupt signal being transmitted to the LPC slave module via an interrupt bus.
Preferably, the multi-channel communication system further includes a software module, the software module runs in an upper computer of the FT chip, and the software module controls the read-write operation of the FT chip according to an address block allocated by the address allocation module, an address and a command given by the driver IP core module, so as to control the FT chip to send the first data frame with a corresponding data command, and correspondingly access and control each of the external devices through the programmable logic device.
Preferably, the software module comprises an application layer, a virtual driver layer and a device driver layer,
the application layer is configured to provide interface service for an application program of the upper computer,
the virtual driver layer is configured to provide the application layer with a standardized set of API functions that conform to the specifications of the upper computer operating system, register callback functions with the device driver layer, and perform internal initialization operations,
the device driver layer is configured to provide a callback function for the virtual driver layer, set address space mapping of a channel corresponding to each external device to control the Feiteng chip to access different channels by accessing different address spaces and control the channels to perform character receiving and sending operations, and a communication channel between each driver IP core module and the corresponding external device is one channel.
Preferably, the internal initialization operation includes:
registering a driver of the underlying device driver layer to provide a driver call interface for the application,
creating a channel device to set a different interrupt number and associated interrupt function for each of said channels,
initializing relevant system parameters for each of the channels.
Preferably, the totem chip determines which of the channels currently sends an interrupt according to the interrupt signal received by the LPC slave module from the interrupt bus, so as to send the corresponding first data frame to control to close the channel currently sending the interrupt and process the channel currently having the interrupt, and after the processing step is executed, opens the closed channel.
Preferably, the LPC slave module is provided with a status register and a sending register, the driving IP core module further comprises a receiving buffer register,
the interrupt signal is stored by the status register,
the software module controls the Feiteng chip to read the data in the status register so as to judge the type of the interrupt,
if the type of the interrupt is abnormal interrupt, the abnormal interrupt processing module in the Feiteng chip is used for processing the abnormality,
if the interrupt type is a valid interrupt of received data, the receiving FIFO unit receives the relevant data information of the external device of the channel where the interrupt currently occurs, then the relevant data received by the receiving FIFO unit is put into the receiving buffer register for buffering through the registered callback function of the virtual drive layer, the chip receives the data from the LPC bus,
if the type of the interrupt is effective interrupt of sending data, the data of the sending register is set and sent to the external equipment through the sending FIFO unit, and the Feiteng chip sends the data to the LPC bus.
The invention has the following beneficial effects:
the Feiteng chip can be configured with various types of external equipment through one LPC bus, and a programming logic device supporting various level standards is used as a communication data intermediate processing module between the Feiteng chip and the external equipment, so that a level conversion chip is omitted. And a matching conversion module is arranged in the programmable logic device to convert the data in the LPC bus into data matched with the ICB bus for transmission of the ICB bus, a protocol conversion chip is not required to be additionally arranged, the circuit structure of the multi-path communication system is simplified, the manufacturing cost is reduced, the application requirement of a Feiteng series platform system on LPC multi-path communication is met, and the development and debugging efficiency is obviously improved. Meanwhile, the main modules of the multi-channel communication system are integrated in the programmable logic device, and only one path of LPC bus is needed for data transmission, so that the multi-channel communication system is easy to expand, high in real-time performance, good in portability, low in hardware resource requirement, and remarkably reduced in software workload, and greatly meets the multi-level requirements of an application system.
Drawings
Fig. 1 is a schematic diagram of a frame of a multi-channel communication system based on a FT platform LPC bus according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of the driving IP core module in the multi-path communication system;
FIG. 3 is a diagram illustrating the configuration of software modules provided according to an embodiment of the present invention;
fig. 4 is a schematic view of a workflow of the internal initialization according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a workflow of the creation of the channel device according to an embodiment of the present invention;
fig. 6 is a schematic flow chart illustrating an execution flow of the interrupt manner according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only for technical attributes or features of the present invention.
The invention provides a multi-channel communication system based on a Feiteng platform LPC bus, which can realize that a Feiteng chip accesses various external devices through one LPC bus, saves interfaces of the Feiteng chip, and the Feiteng chip is a Feiteng CPU. Specifically, as shown in fig. 1, it is a schematic diagram of a framework of a multi-channel communication system based on a FT platform LPC bus according to an embodiment of the present invention. The multi-channel communication system comprises a Feiteng chip, a programmable logic device and various types of external equipment. The Feiteng chip is connected with the programmable logic device through one LPC bus, and a plurality of output ports of the programmable logic device are respectively connected with corresponding external equipment through corresponding standard buses.
In order to overcome the problem that the level of an LPC interface of a Feiteng chip is not matched with the level of an interface of each external device, the programmable logic device is selected to be a programmable logic device supporting multiple level standards, so that the Feiteng chip can respectively access the corresponding external devices after being converted and output by the programmable logic device through one LPC bus. In this embodiment, the FT chip is FT-2000, and the programmable logic device is a purple light similar compact series PGC2KG-6FBG 256.
Referring to fig. 1, an LPC slave module, a match conversion module address assignment module, and a plurality of driver IP cores corresponding to a plurality of external devices are integrated inside the programmable logic device. In this embodiment, the external devices include first to sixth types of external devices, and the driving IP core module includes a UART _ IP core module for driving the first type of external device, an SPI _ IP core module for driving the second type of external device, a CAN _ IP core module for driving the third type of external device, an ONEWIRE _ IP core module for driving the fourth type of external device, an I2C _ IP core module for driving the fifth type of external device, and a keyscan _ IP core module for driving the sixth type of external device. The first type of external equipment is connected with the UART _ IP core module through a standard bus 1, the second type of external equipment is connected with the SPI _ IP core module through a bus 2, the third type of external equipment is connected with the CAN _ IP core module through a standard bus 3, the fourth type of external equipment is connected with the ONEWIRE _ IP core module through a standard bus 5, the fifth type of external equipment is connected with the I2C _ IP core module through a standard bus 5, and the sixth type of external equipment is connected with the Keysacn _ IP core module through a standard bus 6. The communication channel between each driving IP core module and the corresponding external device is one channel, for example, the present embodiment has six channels, which are a channel 1 between the first type external device and the UART _ IP core module, a channel 2 between the second type external device and the SPI _ IP core module, a channel 3 between the third type external device and the CNA _ IP core module, a channel 4 between the fourth type external device and the ONEWIRE _ IP core module, a channel 5 between the fifth type external device and the I2C _ IP core module, and a channel 6 between the sixth type external device and the Keysacn _ IP core module (channels 1 to 6 are not labeled in the figure), the standard buses 1 to 6 are provided in the channels 1 to 6, respectively. The respective standard buses may be selected as the third ICB bus set according to the external device type.
The LPC slave module supports IO read-write operation, so that a first Data frame sent by the Feiteng chip can be transmitted to the LPC slave module through the LPC bus, and the LPC slave module transmits Data bit Data information and address bit ADDR information in the first Data frame (the first Data frame is a Data command sent by the Feiteng chip) to the matching conversion module. Namely, the LPC slave module performs data elimination operation on the first data frame sent by the FT chip, and extracts only the data bit information and the address bit information in the first data frame for output. And the format of the first Data frame transmitted by the Feiteng chip through the LPC bus is fixed to be a Start + CT/DIR + ADDR + TAR + SYNC + Data + TAR format, and the LPC slave equipment only outputs the information of the address bit ADDR and the Data bit Data in the first Data frame.
Because the communication protocol of the LPC bus is different from that of the ICB bus, the output data of the LPC slave module cannot be directly transmitted to the address distribution module through the first ICB data bus for distribution, but needs to be converted by the matching conversion module to meet the requirement of the first ICB bus protocol and then can be transmitted through the first ICB bus. The matching conversion module is therefore configured to convert the data output by the LPC slave module into a second data frame matching the first ICB bus, the second data frame being transmitted to the address assignment module via the first ICB bus. Specifically, in this embodiment, the address bit ADDR in the first data frame is continuously transmitted for 4 cycles, and 4 bits are transmitted in each cycle, and the data bit in the first data frame is the instruction data information sent by the flyover chip, and is continuously transmitted for 2 cycles, and 4 bits are transmitted in each cycle, so that the address bit ADDR in the data output by the LPC slave module is 16 bits, and the data bit is 8 bits. In this embodiment, the first ICB bus adopts a communication protocol with an address bit width of 32 bits. In order to enable address bits in the LPC slave moduleInformation and data bit information can be transmitted to the address distribution module through the first ICB bus, the matching conversion module expands data bits of data received from an LPC slave module from 8 bits to 32 bits, and the address bits are kept to 16 bits, so that the address bits in a second data frame transmitted in the first ICB bus are 16 bits, the data bits are 32 bits wide, namely, the space which can be accessed by the LPC bus through the first ICB bus is at most 216And a plurality of said channels. The matching conversion module is a shift register in this embodiment.
And the address allocation module receives the second data frame in the first ICB bus and divides the total address space in the first ICB bus into a plurality of address spaces according to actual requirements to be respectively allocated to the channels. In this embodiment, the address line is kept to be 16 bits, the total LPC accessible space is at most 216, and the total space range and the base address can be specifically divided according to actual requirements. For example, m-1: n in the second data frame of the first ICB bus data can be customized according to actual requirements]Bit width for accessing max 2(m-1)-nA number of said lanes, where (m-1) ≧ n, and [ n-1:0 ] in said second data frame]The bits are used for transmitting instructions and data information sent by the Feiteng chip. Wherein the address and data lines of the first ICB bus pair are active only when the read/write enable signal line csr _ ren/csr _ wen is asserted.
For example, in this embodiment, the base address of the LPC bus is 0x600, the total address space range is 0x600 to 0x6FF, and the address allocation module performs address allocation division by using a depth of 64 as an interval division, so that the channel 1 address space is 0x600 to 0x63F, the channel 2 address space is 0x640 to 0x67F, the channel 3 address space is 0x680 to 0x6BF, and the channel 4 address space is 0x6C0 to 0x6FF, and so on.
And the plurality of address spaces divided by the address allocation module are respectively allocated to the driving IP core modules through the second ICB buses so as to realize the access of the Feiteng chip to the plurality of external devices.
The first ICB bus and the second ICB bus are also integrated inside the programmable logic device. In the multi-channel communication system provided by the embodiment of the invention, a concrete hardware layer structure is abstracted and is deployed on the programmable logic device to construct a hardware circuit, so that the realization of concrete functions and hardware can form weak link. The type of the programmable logic device can be selected according to actual requirements.
Further, the data transmission mode of the multi-channel communication system is a polling mode or an interrupt mode, for example, in this embodiment, the multi-channel communication system transmits data in an interrupt mode. Interrupt signals IRQ 1-IRQ 6 output by each driving IP core module are transmitted to the LPC slave module through an interrupt bus, and the communication protocol of the interrupt bus is matched with the interrupt bus interface of the LPC slave module, so that the Feiteng chip can directly access each channel through the LPC slave module to conduct corresponding access and control. It should be noted that fig. 1 only illustrates the data flow from one module to another module in the direction of arrows for convenience of illustration, but actually, the communication between the modules includes one-way communication and two-way communication, for example, the ICB bus is two-way communication.
Fig. 2 is a schematic structural diagram of the driving IP core module in the multi-path communication system, where the driving IP core module includes: the ICB bus interface configuration unit is configured to read and write the second ICB bus and output corresponding control signals to the transmission FIFO unit, the reception FIFO unit and the data transmission/reception state machine unit so as to control each unit to perform corresponding functional operation. Specifically, the status information of the external device received by the data transmission/reception state machine unit through the standard bus is input to the second ICB bus via the reception FIFO unit and the ICB bus interface configuration unit, the data instruction information data in the second ICB bus is sent to the external equipment through the standard bus after passing through the ICB bus interface configuration unit, the transmission FIFO unit and the data transmission/reception state machine unit, the status information data received by the data transmission/reception state machine unit is read by the second ICB bus via the reception FIFO unit, the ICB bus interface configuration unit, the receive FIFO unit also generates the interrupt signal IRQ from the received status information data, which is transmitted to the LPC slave module over an interrupt bus. The Feiteng chip judges which channel sends an interrupt currently through the interrupt signal received by the LPC slave module from the interrupt bus so as to send the corresponding first data frame to control to close the channel sending the interrupt currently and process the channel which is interrupted currently, and the closed channel is opened after the processing step is executed.
In the multi-channel communication system provided by the invention, because the communication of multi-channel external equipment is realized only through one LPC bus, only one set of software module for controlling the read-write operation of the Feiteng chip needs to be operated in the upper computer of the Feiteng chip, and a set of software module does not need to be set for the access of each channel, thereby saving the software overhead. Specifically, the software module runs in an upper computer of the soar chip, and the software module controls the read-write operation of the soar chip according to an address distribution block of the address distribution module, an address and a command given by the driving IP core module, so as to control the soar chip to send the first data frame with the corresponding data command, and correspondingly access and control each external device through the programmable logic device.
In this embodiment, the software module is an operating system Kylin operating system of an upper computer operated by the software module, and the software module includes an application layer, a virtual driver layer, and an equipment driver layer. The application layer is configured to provide interface services for an application program of the upper computer, the virtual drive layer is configured to provide a set of standardized API functions meeting the specification of an operating system of the upper computer for the application layer, register a callback function with the device drive layer, and complete internal initialization operations, the device drive layer is configured to provide the callback function for the virtual drive layer, set address space mapping of channels corresponding to the external devices so as to control the Feiteng chip to access different channels by accessing different address spaces and control the channels to perform character receiving and sending operations, and the channels are signal channels formed by the drive IP core module and the corresponding external devices.
The specific configuration diagram of the software module is shown in fig. 3, the application layer mainly provides interface services for upper layer applications, and the user application program realizes the communication function of the application layer by calling a standard user interface layer API function specified by the operating system. The virtual driver layer comprises an API interface module, an LPC _ Drv module and an LPC _ Lib module, the API interface is essentially a set of self-defined operation functions and data structures of a system (kylin operating system) kernel, and the LPC _ Drv module and the LPC _ Lib module work cooperatively to provide services for an upper layer through a hardware driver program of a management bottom layer. The virtual driver layer mainly has the following three functions.
Function 1: a set of operating system specified standardized API functions is provided for upper level applications (application layer). The communication system of this embodiment is implemented based on the real-time operating system Kylin (Kylin operating system), so that the read-write and control functions are registered in the IO system layer of the Kylin system in the form of character devices. The registration is done in the LPC _ Drv module. Meanwhile, the LPC _ Drv driving module calls a corresponding operating system function to complete the registration function of the operating system function. The read-write and control functions of the virtual drive layer to the upper layer registration are as follows:
LPC _ Open: opening a function by LPC equipment, and corresponding to an application layer interface function open;
LPC _ Close: the LPC equipment closing function corresponds to an application layer interface function close;
LPC _ Read: the LPC equipment character reading function corresponds to an application layer interface function read;
LPC _ Write: LPC equipment character sending function corresponding to application layer interface function write;
LPC _ Ioctl: and the LPC equipment control function corresponds to an application layer interface function ioctl function.
Function 2: a callback function is registered with the underlying hardware driver layer. If the Write operation is performed, when the Write function Write device is called by the IO system layer, the LPC _ Write function actively calls the relevant function of the underlying hardware driver to send character data. If it is a Read operation, the LPC _ Read function reads the character directly from the virtual drive layer Read buffer. When the buffer is empty, the method needs to wait if the buffer is in a blocking mode, and immediately returns an error if the buffer is in a non-blocking mode. The filling of the buffer area is carried out by the bottom layer hardware driver in an interrupt mode, when the bottom layer hardware driver receives a character, an interrupt is generated, and then a callback function provided by the virtual driver layer is called to write the character into the buffer area for the upper layer to read. Thus, the virtual driver layer needs to provide two callback functions to the underlying hardware driver: the first is a send function, which realizes that a bottom hardware driver reads a character function from a write buffer; the second is the receive function, the underlying hardware driver writes a function of characters into the read buffer.
Function 3: complete its internal initialization
The internal initialization work mainly comprises driver registration, device channel creation and system parameter initialization. The work flow is shown in fig. 4, and the initialization mainly includes:
step 1: driver registration to underlying driver device layer
The driver registration is to fill the entry point of the driver into the driver table and provide the calling interface of the driver for the upper application. In the system, a plurality of functions such as Open, Close, Read, Write and Ioctl are designed, and registration is realized through a Kylin operating system function register chrdev.
Step 2: channel creation device
The channel is a communication channel of the external device, and in order to add the device of each channel to the device list, different interrupt numbers need to be set for each channel, and an interrupt function needs to be associated, then an LPC drive function is called to register in an operating system, and finally the LPC drive function is associated with bottom layer hardware. The creation flow of the channel device is shown in fig. 5. Firstly, initializing whether the channel number i of the channel is less than or equal to N (N is the number of the channels), if the judgment result is that i +1 is still not greater than N, continuing to interrupt and set up, and calling an LPC driver to register in an operating system after the interruption of the channels is set up. And after the driver is registered, initializing the channel number, and starting to create channel number devices one by one until all the channel devices are created.
And step 3: initializing system parameters
Initialization sets its interrupt number, baud rate, and other parameters, etc., primarily for each channel.
The device driver layer mainly comprises various bottom hardware drivers. The layer interacts with the virtual driver layer upwards and interacts with the specific hardware downwards. The functions of three aspects are mainly completed: firstly, providing a callback function registration function to an upper layer, such as starting a data sending function; secondly, completing communication setting of different channels, mainly setting address space mapping, and realizing access to different channels by accessing different address spaces; and thirdly, controlling the channel to receive and transmit characters and other hardware configuration work, and realizing the receiving and transmitting of the characters. In the normal mode, data is generally received and transmitted in an interrupt mode. The system also supports a polling mode for data receiving and transmitting.
In an embodiment of the present invention, data is received and transmitted in an interrupt manner, the LPC slave module is provided with a status register and a transmission register (not shown in fig. 1), the driving IP core module further includes a receiving buffer register (not shown in fig. 2), and the interrupt signal is stored through the status register. As shown in fig. 6, it is a flowchart for executing an interrupt manner provided by the embodiment of the present invention, where the interrupt manner is: the method comprises the steps of firstly obtaining a channel number i which causes interruption, then closing the interruption of the ith channel, and after the interruption of the ith channel is processed, opening the interruption of the ith channel. Specifically, in the process of processing an interrupt, the software module controls the soar chip to read data in a status register so as to determine the type of the interrupt, if the type of the interrupt is an abnormal interrupt, the abnormal interrupt processing module in the soar chip processes the abnormality, if the type of the interrupt is an effective interrupt of received data, the receiving FIFO unit receives a relevant data message of an external device of the channel where the interrupt currently occurs, and then the relevant data received by the receiving FIFO unit is buffered in the receiving buffer register through a registered callback function of the virtual drive layer, the chip receives data from the LPC bus, and if the type of the interrupt is an effective interrupt of transmitted data, the data of the transmitting register is transmitted to the external device through the transmitting FIFO unit by setting the data of the transmitting register, and the Feiteng chip sends data to the LPC bus.
In order to realize callback function registration, the virtual driver layer defines a data structure with a structure body of LPC _ DRV _ FUNCS, all members of the structure body are function pointers, the device driver layer completes corresponding functions through corresponding functions, initializes the LPC _ DRV _ FUNCS structure body by the function addresses and informs the virtual driver layer of the function addresses.
The multi-channel communication system based on the FT platform LPC bus can realize that a Feiteng chip configures a plurality of types of external equipment through one LPC bus, and a programming logic device supporting a plurality of level standards is used as a communication data intermediate processing module between the Feiteng chip and the external equipment, so that a level conversion chip is omitted. And a matching conversion module is arranged in the programmable logic device to convert the data in the LPC bus into data matched with the ICB bus for transmission of the ICB bus, a protocol conversion chip is not required to be additionally arranged, the circuit structure of the multi-path communication system is simplified, the manufacturing cost is reduced, the application requirement of a Feiteng series platform system on LPC multi-path communication is met, and the development and debugging efficiency is obviously improved. Meanwhile, the main modules of the multi-channel communication system are integrated in the programmable logic device, and only one path of LPC bus is needed to transmit data, so that the expansion is easy, the real-time performance is strong, the portability is good, the use of hardmac resources is not needed, the workload of software is remarkably reduced, and the multi-level requirements of an application system are greatly met.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A multi-channel communication system based on a Feiteng platform LPC bus is characterized by comprising the following components: a FT chip, a programmable logic device, and a plurality of external devices,
the Feiteng chip is connected with the programmable logic device through a LPC bus, a plurality of output ports of the programmable logic device are respectively connected with corresponding external equipment through corresponding standard buses,
wherein the programmable logic device supports multiple level standards, an LPC slave module, a matching conversion module, an address allocation module and a plurality of driving IP cores corresponding to a plurality of external devices are integrated in the programmable logic device, the LPC slave module supports IO read-write operation,
the first data frame sent by the Feiteng chip is transmitted to the LPC slave module through the LPC bus, the LPC slave module transmits data bit information and address bit information in the first data frame to the matching conversion module,
the matching conversion module converts the data bit information and the address bit information into a second data frame matched with the first ICB bus, and the second data frame is transmitted to the address distribution module through the first ICB bus,
the address allocation module divides the total address space in the second data frame into a plurality of address spaces and allocates each address space to each driving IP core module through each second ICB bus respectively,
and the driving signals output by the driving IP core module are respectively connected with the corresponding external equipment through the corresponding standard bus.
2. The multi-lane communication system of claim 1, wherein the first ICB bus and the second ICB bus are integrated within the programmable logic device.
3. The multi-channel communication system according to claim 1, wherein the data transmission mode of the multi-channel communication system is a polling mode or an interrupt mode.
4. The multi-channel communication system of claim 1, wherein the interrupt signal output by the driver IP core module is connected to the LPC slave module via an interrupt bus, and the interrupt bus is matched to an interrupt bus interface of the LPC slave module.
5. The multi-lane communication system of claim 4, wherein the driver IP core module comprises: an ICB bus interface configuration unit, a transmission FIFO unit, a reception FIFO unit and a data transmission/reception state machine unit,
the ICB bus interface configuration unit is configured to read and write the second ICB bus and output corresponding control signals to the transmission FIFO unit, the reception FIFO unit and the data transmission/reception state machine unit so as to control the units to perform corresponding functional operations,
the state information of the external equipment received by the data sending/receiving state machine unit through the standard bus is input to the second ICB bus after passing through the receiving FIFO unit and the ICB bus interface configuration unit,
the data instruction information data in the second ICB bus is sent to the external equipment through the standard bus after passing through the ICB bus interface configuration unit, the transmission FIFO unit and the data transmission/reception state machine unit,
the status information data received by the data transmission/reception state machine unit is read by the second ICB bus via the reception FIFO unit, the ICB bus interface configuration unit,
the receive FIFO unit also generates the interrupt signal based on the received status information data, the interrupt signal being transmitted to the LPC slave module via an interrupt bus.
6. The multi-channel communication system according to claim 5, further comprising a software module, wherein the software module is run in an upper computer of the FT chip, and the software module controls read/write operations of the FT chip according to an address block allocated by the address allocation module, an address and a command given by the driver IP core module, so as to control the FT chip to send the first data frame with a corresponding data command, and perform corresponding access and control on each external device through the programmable logic device.
7. The multi-way communication system according to claim 6, wherein the software modules comprise an application layer, a virtual driver layer, and a device driver layer,
the application layer is configured to provide interface service for an application program of the upper computer,
the virtual driver layer is configured to provide the application layer with a standardized set of API functions that conform to the specifications of the upper computer operating system, register callback functions with the device driver layer, and perform internal initialization operations,
the device driver layer is configured to provide a callback function for the virtual driver layer, set address space mapping of a channel corresponding to each external device to control the Feiteng chip to access different channels by accessing different address spaces and control the channels to perform character receiving and sending operations, and a communication channel between each driver IP core module and the corresponding external device is one channel.
8. The multi-channel communication system of claim 7, wherein the internal initialization operation comprises:
registering a driver in the device driver layer to provide a driver call interface for the application,
creating a channel device to set a different interrupt number and associated interrupt function for each of said channels,
initializing relevant system parameters for each of the channels.
9. The multi-channel communication system according to claim 7, wherein the totem chip determines which of the channels currently sends an interrupt according to the interrupt signal received from the interrupt bus by the LPC slave module, so as to send the corresponding first data frame to control to close the channel currently sending the interrupt and process the channel currently having the interrupt, and to open the closed channel after the processing step is completed.
10. The multi-channel communication system according to claim 9, wherein the LPC slave module is provided with a status register and a transmission register, the driver IP core module further comprises a reception buffer register,
the interrupt signal is stored by the status register,
the software module controls the Feiteng chip to read the data in the status register so as to judge the type of the interrupt,
if the type of the interrupt is abnormal interrupt, the abnormal interrupt processing module in the Feiteng chip is used for processing the abnormality,
if the interrupt type is a valid interrupt of received data, the receiving FIFO unit receives the relevant data information of the external device of the channel where the interrupt currently occurs, then the relevant data received by the receiving FIFO unit is put into the receiving buffer register for buffering through the registered callback function of the virtual drive layer, the chip receives the data from the LPC bus,
if the type of the interrupt is effective interrupt of sending data, the data of the sending register is set and sent to the external equipment through the sending FIFO unit, and the Feiteng chip sends the data to the LPC bus.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112199317B (en) * 2020-10-27 2022-10-18 南京大学 Bridging system and bridging method for RISCV processor to access Flash memory
CN112612739A (en) * 2020-12-17 2021-04-06 深圳慧能泰半导体科技有限公司 Digital communication bus of multi-module system and control method thereof
CN112395230A (en) * 2020-12-21 2021-02-23 太原智林信息技术股份有限公司 UART interface extension circuit based on programmable logic device
CN112612667B (en) * 2020-12-24 2022-11-22 天津国芯科技有限公司 Tracking debugging information processing circuit and method for SoC chip
CN113448898A (en) * 2021-08-30 2021-09-28 成都万创科技股份有限公司 Device and method for realizing multifunctional low-speed IO by using UART
CN114143135B (en) * 2021-11-17 2023-07-07 天津市英贝特航天科技有限公司 Remote data transmission device, system and method
CN114817106B (en) * 2022-05-11 2023-10-24 湖南泽天智航电子技术有限公司 Universal interface expansion system based on Feiteng series PCIE bus
CN117421257A (en) * 2023-10-24 2024-01-19 上海合芯数字科技有限公司 Memory bank initialization method, device, equipment and storage medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440219A (en) * 2013-08-23 2013-12-11 上海航天测控通信研究所 Novel general bus transforming bridge IP core
CN108763112A (en) * 2018-06-05 2018-11-06 成都爱斯顿科技有限公司 The method that LPC-LBC bus bridges IP kernel and lpc bus based on FPGA turn LBC buses
CN109032973A (en) * 2018-07-09 2018-12-18 胡振波 ICB bus system and agreement

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008028910A1 (en) * 2006-09-06 2008-03-13 Thomson Licensing Device for processing a stream of data words

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440219A (en) * 2013-08-23 2013-12-11 上海航天测控通信研究所 Novel general bus transforming bridge IP core
CN108763112A (en) * 2018-06-05 2018-11-06 成都爱斯顿科技有限公司 The method that LPC-LBC bus bridges IP kernel and lpc bus based on FPGA turn LBC buses
CN109032973A (en) * 2018-07-09 2018-12-18 胡振波 ICB bus system and agreement

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