Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The differential pressure sensor comprises three performance indexes of sensitivity, linearity and reliability. The sensitivity refers to the ratio of the output quantity change delta y to the input quantity change delta x of the differential pressure sensor under the steady-state working condition, namely the sensitivity degree of the output quantity to the input quantity change, when the pressure sensing film is thinner, the deformation after stress is larger, namely the differential pressure sensor is more sensitive, and the visible sensitivity is inversely proportional to the thickness of the pressure sensing film. The linearity refers to the maximum deviation of the linear relation between the output quantity y and the input quantity x of the differential pressure sensor in the working pressure range, and when the pressure sensing film is too thin, the stress generated by the pressure sensing film and the applied pressure are not in the linear relation any more, namely, the thinner the pressure sensing film is, the worse the linearity is, and the linearity is in direct proportion to the thickness of the pressure sensing film. The reliability is the ability or possibility of executing a predetermined function without fail under a certain condition for a certain period of time, and the larger the thickness of the pressure-sensitive film, the less likely to be broken, and the higher the reliability, and the visible reliability is proportional to the thickness of the pressure-sensitive film.
Fig. 1 is a flowchart illustrating a method for manufacturing a differential pressure sensor according to an embodiment of the present invention. The manufacturing method is particularly suitable for manufacturing a micro differential pressure sensor, and as can be seen from the figure, the manufacturing method 100 of the differential pressure sensor comprises the following steps:
step S101, preparing an insulator wafer with a cavity, wherein the insulator wafer with the cavity comprises a device layer, an oxidation layer and a substrate layer which are sequentially overlapped, and an annular cavity located in the substrate layer is arranged between the substrate layer and the oxidation layer.
Step S102, preparing the piezoresistor on the surface of the device layer.
Step S103, etching off part of the substrate layer within the orthographic projection range of the annular cavity until the annular cavity is exposed.
In one embodiment, the method for manufacturing a differential pressure sensor as shown in fig. 1 further comprises:
and step S104, etching a second groove on the surface of the device layer to form a second convex island, wherein the piezoresistor is positioned on the second convex island.
And step S105, etching the substrate layer and the oxide layer which are remained in the orthographic projection range of the annular cavity until the device layer is exposed.
The following describes a method for manufacturing a differential pressure sensor according to the present invention with reference to the accompanying drawings.
Fig. 2a to 2i are schematic cross-sectional views illustrating device structures obtained in a process of manufacturing an insulator wafer with a cavity according to an embodiment of the present invention.
In a first step, an island wafer is prepared as shown in fig. 2e, which includes a groove 203 and a first island 204 surrounded by the groove 203.
Specifically, referring first to fig. 2a, a wafer 10 is provided, wherein the wafer 10 includes an upper surface and a lower surface, i.e., a first surface and a second surface.
A wafer, i.e., a silicon wafer, is generally a circular sheet-like structure, and various circuit elements can be processed and fabricated on the surface thereof, thereby forming a silicon semiconductor integrated circuit.
Next, referring to fig. 2b, the first surface and the second surface of the wafer 10 are thermally oxidized to form a first silicon dioxide layer 201 and a second silicon dioxide layer 202, respectively.
The first silicon dioxide layer 201 serves as a mask in a subsequent process, and the second silicon dioxide layer 202 serves to prevent the lower surface of the wafer 10 from being scratched. Of course, if the influence of the external mechanical damage on the lower surface of the wafer 10 is negligible, the first surface may be thermally oxidized to form the first silicon dioxide layer 201.
The thickness of the first silicon dioxide layer 201 and the second silicon dioxide layer 202 is typically about 1 micron, but is not limited thereto,
referring to fig. 2c and fig. 2d, fig. 2d is a top view of the device structure shown in fig. 2c, a photolithography process or a plasma etching process is used to etch from the surface of the first silicon dioxide layer 201 to the inside of the wafer 10, so as to form a ring-shaped first groove 203, and then a dry etching process or a wet etching process is used to etch away the remaining first silicon dioxide layer 201.
The first groove 203 may be any regular or irregular annular groove, such as a rectangular annular groove or a circular annular groove.
To this end, an island wafer 20 is obtained as shown in fig. 2e, the island wafer 20 includes a front side and a back side, and the front side of the island wafer includes a first groove 203 and a first convex island 204 surrounded by the first groove 203. Specifically, the island-in-wafer in the present embodiment includes a silicon substrate 205 and a second silicon dioxide layer 202 stacked up and down, wherein a surface of the silicon substrate 205 includes a first groove 203 and a first convex island 204 surrounded by the first groove 203.
In a second step, an insulator wafer is provided, the front side of which includes a first silicon layer.
Fig. 2f is a schematic structural diagram of an insulator wafer according to an embodiment of the invention. The Insulator wafer 30 is an engineered substrate fabricated by Silicon-On-Insulator (SOI) technology, that is, an insulating oxide layer, for example, a Silicon dioxide layer, is sealed between two Silicon substrates, so as to form a structure of a first Silicon layer 301, an oxide layer 302, and a second Silicon layer 303 stacked in sequence from top to bottom as shown in fig. 2f, wherein the thickness of the first Silicon layer 301 can be precisely controlled for forming a circuit structure, preferably 5 to 15 micrometers in this embodiment, the surface of the first Silicon layer 301 generally serves as the front surface of the Insulator wafer 30, and the surface of the second Silicon layer 303 generally serves as the back surface of the Insulator wafer.
And thirdly, attaching the front surface of the insulator wafer to the front surface of the wafer with the island.
Specifically, referring first to fig. 2g, the third silicon dioxide layer 401 and the fourth silicon dioxide layer 410 are formed by performing thermal oxidation on the upper and lower surfaces of the insulator wafer 30 shown in fig. 2f, respectively.
The third silicon oxide layer 401 is used for a bonding process in a subsequent process, and the fourth silicon oxide layer 410 is used for preventing the surface of the second silicon layer 303 from being scratched. Of course, if the influence of the external mechanical damage on the lower surface of the insulator wafer 30 is negligible, the third silicon dioxide layer 401 may be formed by performing thermal oxidation only on the upper surface.
The thickness of the third silicon dioxide layer 401 and the fourth silicon dioxide layer 410 is typically several hundred nanometers, but is not limited thereto.
Referring next to fig. 2h, the thermally oxidized insulator wafer 30 shown in fig. 2g is turned upside down with its back side facing upward, silicon dioxide-silicon bonding is performed on the back side of the thermally oxidized insulator wafer 30 and the front side of the island-carrying wafer 20 shown in fig. 2e, and the top opening of the recess 203 is closed by the third silicon dioxide layer 401 to form the annular cavity 206.
Fourth, the first silicon layer 301 of the insulator wafer is etched down from the back side of the insulator wafer to expose the insulator wafer.
Referring to fig. 2h, the fourth silicon dioxide layer 410 is chemically and mechanically polished to expose the second silicon layer 303 of the insulator wafer; etching off the second silicon layer 303 by using a tetramethylammonium hydroxide solution until the oxide layer 302 of the insulator wafer is exposed; finally, the oxide layer 302 is wet etched away by using a hydrofluoric acid solution until the first silicon layer 301 of the insulator wafer is exposed, as shown in fig. 2 i.
It can be understood by those skilled in the art that when the fourth silicon dioxide layer 410 is not formed by thermally oxidizing the lower surface of the insulator wafer 30 in step S103, the process of chemically and mechanically polishing the fourth silicon dioxide layer 410 to expose the second silicon layer 303 may be omitted in step S104, and the second silicon layer 303 is directly etched away by using a tetramethylammonium hydroxide solution to expose the oxide layer 302 of the insulator wafer; the oxide layer 302 is then wet etched away using a hydrofluoric acid solution to expose the first silicon layer 301 of the insulator wafer.
To this end, an insulator wafer 40 with cavities is formed as shown in fig. 2 i. The insulator wafer 40 with the cavity comprises a device layer 402, an oxidation layer 403, a substrate layer 404 and a protection layer 405 which are sequentially stacked, wherein an annular cavity 406 located in the substrate layer 404 is arranged between the oxidation layer 403 and the substrate layer 404, and the thickness of the device layer 402 is precisely controllable.
Fig. 3 a-3 e are schematic structural diagrams illustrating a device in a process of manufacturing a differential pressure sensor by using an insulator wafer with a cavity according to an embodiment of the invention.
In a first step, a varistor is fabricated on the surface of the device layer 402 of the insulator wafer 40 with cavities as shown in fig. 2i, according to step S102.
Referring to fig. 3a, a lightly doped region 501 and a heavily doped region 502 in contact therewith are formed at the surface of the device layer 402. The lightly doped region 501 serves as a varistor and the heavily doped region 502 serves as a conductor for leading out a resistance value in the varistor.
The process of forming the lightly doped region 501 and the heavily doped region 502 in contact therewith includes: the upper surface of the device layer 402 is first etched by photolithography to form regions to be doped, including regions to be heavily doped and regions to be lightly doped, and then the regions to be heavily doped are respectively heavily doped by an ion implantation process, and the regions to be lightly doped are lightly doped. This forms a heavily doped region 502 for use as a wire and a lightly doped region 501 for use as a varistor.
In one embodiment, step S102 may further include preparing a wheatstone bridge including piezoresistors.
Specifically, referring first to fig. 3b, a deposition process is used to form an insulating composite layer 503 on the surfaces of the device layer 402, the lightly doped region 501 and the heavily doped region 502.
The insulating composite layer 503 shown in fig. 3b includes a first silicon dioxide layer, a silicon nitride layer, and a second silicon dioxide layer stacked in this order from bottom to top. In other embodiments, the insulating composite layer may also include only the first silicon dioxide layer and the silicon nitride layer deposited on the upper surface of the first silicon dioxide layer. The thickness proportion of each film layer in the insulating composite layer is based on the stress balance state.
Referring next to fig. 3c, metal wiring is prepared to form a wheatstone bridge configuration.
For example, a through hole penetrating through the insulating composite layer 503 and contacting the heavily doped region 502 is formed on the upper surface of the insulating composite layer 503 by using a photolithography etching or anisotropic etching process, metal is deposited in the through hole, on the upper surface of the insulating composite layer 503 and around the through hole, so as to form a pressure pad 504 contacting the heavily doped region 502, the pressure pad 504 is contacted with the heavily doped region 502 to extract a resistance signal in the lightly doped region 501 serving as a piezoresistor, and the pressure pad 504 is used as a connection terminal of the piezoresistor to construct a wheatstone bridge structure.
Secondly, according to step S103, etching is performed from the surface of the protection layer 405 to expose the annular cavity 406 within the orthographic projection range of the annular cavity 406.
Referring first to FIG. 3d, a photolithography or plasma etching process is used to etch away the protective layer 405 within the orthographic projection of the annular cavity 406 to expose the substrate layer 404.
Referring next to fig. 3e, a portion of the substrate layer 404 is etched away by using the remaining protective layer 405 as a mask and using a deep reactive ion etching or plasma etching process until the ring-shaped cavity 406 is exposed.
It should be understood by those skilled in the art that when the second surface of the wafer 10 is not thermally oxidized to form the second silicon dioxide layer 202 (i.e., the protective layer 405) in step S101, step S103 may include etching away a portion of the substrate layer 404 within the orthographic projection range of the ring-shaped cavity 406 by using a deep reactive ion etching or plasma etching process until the ring-shaped cavity 406 is exposed.
Thus, the differential pressure sensor 50 shown in fig. 3e is obtained, the device layer 402 forms the pressure sensing film 505 of the differential pressure sensor 50, the lower surface of the pressure sensing film 505 is fixedly connected to the first islands 204 through the oxide layer 403, and the thickness of the first islands 204 is preferably 20 to 50 μm to satisfy the load bearing capability of the pressure sensing film 505.
According to the method for manufacturing the differential pressure sensor 50 provided by the invention, when the stress generated by the pressure sensing film 505 being bent by the force is concentrated towards the middle part, the thickness of the pressure sensing film at the position of the first convex island 204 is increased due to the first convex island 204 below the pressure sensing film 505, so that the linearity and the reliability of the differential pressure sensor are improved. In addition, the thickness of the pressure sensing film 505 depends on the thickness of the first silicon layer 301 in the insulator wafer 30, and the thickness of the pressure sensing film in a plurality of differential pressure sensors produced by using the same insulator wafer or different insulator wafers is consistent, that is, the sensitivity of the differential pressure sensors produced in mass production is consistent, because the thickness of the first silicon layer 301 is precisely controllable.
Fig. 4 a-4 b are schematic structural diagrams illustrating a device structure in a manufacturing process of manufacturing a differential pressure sensor using an insulator wafer with a cavity according to an embodiment of the invention. The manufacturing process for manufacturing a differential pressure sensor using an insulator wafer with a cavity provided according to the present embodiment is different from the manufacturing process shown in fig. 3a to 3e only in the second step.
The second step in this embodiment, according to step S103, referring to fig. 3c, includes etching from the surface of the protection layer 405 to expose the device layer 402 in the orthographic projection range of the annular cavity 406, and etching a groove on the surface of the device layer 402 to form a second convex island on which the piezoresistor is located, as shown in fig. 4 b.
Specifically, referring to fig. 3c, a photolithography or plasma etching process is used to etch away the protective layer 405 within the orthographic projection range of the annular cavity 406 until the substrate layer 404 is exposed; etching away part of the substrate layer 404 to expose the annular cavity 406 by using the remaining protective layer 405 as a mask and adopting a deep reactive ion etching or plasma etching process; and etching the raised islands and the oxide layer 403 in the annular cavity 406 by using a BOE wet etching process until the device layer 402 is exposed, so as to obtain the structure shown in fig. 4 a.
Next, referring to fig. 4b, a photolithography or plasma etching process is used to etch a groove 601 on the front surface insulating composite layer 503 of the device layer 402 to the inside of the device layer 402 to form a second protruding island 602, where the piezoresistor is located on the second protruding island 602, avoiding the piezoresistor.
The groove 601 in this embodiment includes four sub-grooves, thereby forming a cross-shaped second island 602. In other embodiments, the second islands 602 may be rectangular or circular islands, and in this case, the grooves 601 should be selected according to the shape of the islands to be formed.
Thus, the differential pressure sensor 60 shown in fig. 4b is obtained, wherein the upper surface of the pressure-sensitive film 603 is fixedly connected with the second raised island 602, and the thickness of the second raised island 602 is preferably 5 to 10 μm to satisfy the load-bearing capacity of the pressure-sensitive film.
In one embodiment, the surface area of the grooves 601 is greater than the surface area of the second islands 602. This can reduce the load on the pressure-sensitive film 603 as much as possible.
According to the method for manufacturing the differential pressure sensor 60 provided by the invention, the second raised island 602 is arranged above the pressure sensing film, so that the thickness of the pressure sensing film at the position of the second raised island 602 is increased, and the linearity and the reliability of the differential pressure sensor are improved. In addition, the islands formed by the method for manufacturing a differential pressure sensor according to this embodiment are located above the pressure-sensitive film, and the thickness of the pressure-sensitive film can be reduced as compared with the method for manufacturing a differential pressure sensor shown in fig. 3a to 3e, which is suitable for manufacturing a differential pressure sensor having a smaller range.
It should be understood that the terms "first", "second", "third", and "fourth", etc. used in the description of the embodiments of the present invention are only used for clearly illustrating the technical solutions, and are not used for limiting the protection scope of the present invention.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and the like that are within the spirit and principle of the present invention are included in the present invention.