CN108735713B - 半导体堆叠结构 - Google Patents

半导体堆叠结构 Download PDF

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Publication number
CN108735713B
CN108735713B CN201710470387.0A CN201710470387A CN108735713B CN 108735713 B CN108735713 B CN 108735713B CN 201710470387 A CN201710470387 A CN 201710470387A CN 108735713 B CN108735713 B CN 108735713B
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substrate
pad
disposed
semiconductor stack
top surface
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CN108735713A (zh
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林柏均
朱金龙
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体堆叠结构，包含基板、第一电子元件、第一斜坡件以及第一重分布层。基板具有支持面，其中基板包含第一接垫，第一接垫设置于支持面上。第一电子元件设置于支持面上且具有第一底面、第一顶面以及连接第一底面与第一顶面的第一侧面，其中第一电子元件包含第二接垫，第二接垫设置于第一顶面上。第一斜坡件设置于支持面与第一侧面上且具有第一斜面。第一重分布层设置于支持面、第一顶面以及第一斜面上且电性连接第一接垫与第二接垫。本发明的半导体堆叠结构没有引线，因此可以避免不同引线可能会短路的情况，同时半导体堆叠结构的尺寸将会较小。

Description

半导体堆叠结构
技术领域
本发明是有关于一种半导体堆叠结构。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐进入多功能、高性能的研发方向。为满足半导体元件高积集度(Integration)以及微型化(Miniaturization)的要求，封装结构的各项要求也越来越高。
为了进一步改善封装结构的各项特性，相关领域莫不费尽心思开发。如何能提供一种具有较佳特性的封装结构，实属当前重要研发课题之一，也成为当前相关领域亟需改进的目标。
发明内容
本发明的目的是在于提供一种半导体堆叠结构，以增加半导体堆叠结构的制造合格率与减少半导体堆叠结构的尺寸与制造成本。
根据本发明一实施方式，一种半导体堆叠结构包含基板、第一电子元件、第一斜坡件以及第一重分布层。基板具有支持面，其中基板包含第一接垫，第一接垫设置于支持面上。第一电子元件设置于支持面上且具有第一底面、第一顶面以及连接第一底面与第一顶面的第一侧面，其中第一电子元件包含第二接垫，第二接垫设置于第一顶面上。第一斜坡件设置于支持面与第一侧面上且具有第一斜面。第一重分布层设置于支持面、第一顶面以及第一斜面上且电性连接第一接垫与第二接垫。
在本发明的一个或多个实施方式中，基板还包含本体与至少一个第二重分布层，其中第二重分布层设置在本体中。
在本发明的一个或多个实施方式中，半导体堆叠结构还包含多个焊球。焊球设置于基板相对于支持面的一面。
在本发明的一个或多个实施方式中，半导体堆叠结构还包含封装件。封装件设置于支持面上且覆盖第一电子元件。
在本发明的一个或多个实施方式中，第一电子元件为晶片。
在本发明的一个或多个实施方式中，第一斜坡件覆盖第一侧面。
在本发明的一个或多个实施方式中，第一斜坡件裸露第一侧面的至少一部分。
在本发明的一个或多个实施方式中，第一重分布层还设置于第一侧面上。
在本发明的一个或多个实施方式中，半导体堆叠结构还包含晶片粘着件。晶片粘着件设置于支持面与第一底面之间，其中晶片粘着件的材质与第一斜坡件的材质相同。
在本发明的一个或多个实施方式中，半导体堆叠结构还包含第二电子元件与第二斜坡件。第二电子元件设置于第一顶面上且具有第二底面、第二顶面以及连接第二底面与第二顶面的第二侧面，其中第二电子元件包含第三接垫，第三接垫设置于第二顶面上。第二斜坡件设置于第二侧面上且具有第二斜面。
在本发明的一个或多个实施方式中，第二斜坡件还设置于第一顶面上，第一重分布层还设置于第二斜面与第二顶面上且还电性连接第三接垫。
在本发明的一个或多个实施方式中，第二斜坡件还设置于第一斜面上。半导体堆叠结构还包含第二重分布层。第二重分布层设置于第二斜面与第二顶面上且电性连接第一接垫与第三接垫。
在本发明的一个或多个实施方式中，第一重分布层电性连接第二重分布层。
在本发明的一个或多个实施方式中，第一重分布层与第二重分布层电性绝缘。
在本发明的一个或多个实施方式中，第一电子元件在基板上的正投影与第二电子元件在基板上的正投影大致相同。
在本发明的一个或多个实施方式中，第二电子元件在基板上的正投影的一部分与第一电子元件在基板上的正投影不重叠。
在本发明的一个或多个实施方式中，第二电子元件覆盖第二接垫。
在本发明的一个或多个实施方式中，第二电子元件没有覆盖第二接垫。
在本发明的一个或多个实施方式中，第二接垫在基板上的正投影与第二电子元件在基板上的正投影重叠。
在本发明的一个或多个实施方式中，第二接垫在基板上的正投影与第二电子元件在基板上的正投影不重叠。
通过利用重分布层电性连接接垫，基板以及堆叠的电子元件将会互相电性连接。相较于使用引线焊接(Wire Bonding)的方法，使用本方法将可以避免不同引线可能会短路的情况。在此同时，因为半导体堆叠结构中没有引线，其会占据极大的空间，所以半导体堆叠结构的尺寸将会较小。
另外，因为半导体堆叠结构中没有穿透硅通孔(Through-silicon Vias，TSV)，其价格较为昂贵，因此半导体堆叠结构的制造成本将能有效降低。
附图说明
图1绘示依照本发明一实施方式的半导体堆叠结构的剖面示意图。
图2绘示依照本发明另一实施方式的半导体堆叠结构的剖面示意图。
图3绘示依照本发明另一实施方式的半导体堆叠结构的剖面示意图。
图4至图9绘示依照本发明一实施方式的半导体堆叠结构的制程的各步骤的剖面示意图。
图10至图14绘示依照本发明另一实施方式的半导体堆叠结构的工艺的各步骤的剖面示意图。
具体实施方式
以下将以附图公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化附图起见，一些公知惯用的结构与元件在附图中将以简单示意的方式绘示。
图1绘示依照本发明一实施方式的半导体堆叠结构100的剖面示意图。如图1所绘示，本发明不同实施方式提供一种半导体堆叠结构100。在一些实施方式中，半导体堆叠结构100为封装结构。半导体堆叠结构100可以通过晶圆级工艺(Wafer-level Process)或面板级工艺(Panel-level Process)制造。
半导体堆叠结构100包含基板200、电子元件310、320、330、340、斜坡件410、420、430、440以及重分布层510。基板200具有支持面200s，其中基板200包含接垫210，接垫210设置于支持面200s上。
电子元件310设置于支持面200s上且具有底面310b、顶面310t以及连接底面310b与顶面310t的侧面310s。电子元件310包含接垫311。接垫311设置于顶面310t上。斜坡件410设置于支持面200s与侧面310s上且具有斜面410i。
电子元件320设置于顶面310t上且具有底面320b、顶面320t以及连接底面320b与顶面320t的侧面320s。电子元件320包含接垫321。接垫321设置于顶面320t上。斜坡件420设置于顶面310t与侧面320s上且具有斜面420i。
在本实施方式中，电子元件320在基板200上的正投影的一部分与电子元件310在基板200上的正投影不重叠。换句话说，电子元件320不与电子元件310对齐。
进一步来说，电子元件320没有覆盖接垫311。于是，接垫311在基板200上的正投影与电子元件320在基板200上的正投影不重叠。
电子元件330设置于顶面320t上且具有底面330b、顶面330t以及连接底面330b与顶面330t的侧面330s。电子元件330包含接垫331。接垫331设置于顶面330t上。斜坡件430设置于顶面320t与侧面330s上且具有斜面430i。
在本实施方式中，电子元件330在基板200上的正投影的一部分与电子元件320在基板200上的正投影不重叠。换句话说，电子元件330不与电子元件320对齐。
进一步来说，电子元件330没有覆盖接垫321。于是，接垫321在基板200上的正投影与电子元件330在基板200上的正投影不重叠。
电子元件340设置于顶面330t上且具有底面340b、顶面340t以及连接底面340b与顶面340t的侧面340s。电子元件340包含接垫341。接垫341设置于顶面340t上。斜坡件440设置于顶面330t与侧面340s上且具有斜面440i。
在本实施方式中，电子元件340在基板200上的正投影的一部分与电子元件330在基板200上的正投影不重叠。换句话说，电子元件340不与电子元件330对齐。
进一步来说，电子元件340没有覆盖接垫331。于是，接垫331在基板200上的正投影与电子元件340在基板200上的正投影不重叠。
重分布层510设置于支持面200s、顶面310t、320t、330t、340t以及斜面410i、420i、430i、440i上且电性连接接垫210、311、321、331、341。
通过利用重分布层510电性连接接垫210、311、321、331、341，基板200以及堆叠的电子元件310、320、330、340将会互相电性连接。相较于使用引线焊接(Wire Bonding)的方法，使用本方法将可以避免不同引线可能会短路的情况。在此同时，因为半导体堆叠结构100中没有引线，其会占据极大的空间，所以半导体堆叠结构100的尺寸将会较小。
另外，因为半导体堆叠结构100中没有穿透硅通孔(Through-silicon Vias，TSV)，其价格较为昂贵，因此半导体堆叠结构100的制造成本将能有效降低。
基板200还包含本体220与至少一个重分布层230，其中重分布层230设置在本体220中。半导体堆叠结构100还包含多个焊球910。焊球910设置于基板200相对于支持面200s的一面。
在一些实施方式中，电子元件310、320、330、340为晶片。应了解到，以上所举的电子元件310、320、330、340的具体实施方式仅为例示，并非用以限制本发明，本发明所属技术领域中的技术人员，应视实际需要，弹性选择电子元件310、320、330、340的具体实施方式。
在本实施方式中，斜坡件410覆盖侧面310s，斜坡件420覆盖侧面320s，斜坡件430覆盖侧面330s，斜坡件440覆盖侧面340s，但不限于此。在一些实施方式，斜坡件410、420、430、440可能没有覆盖侧面310s、320s、330s、340s。覆盖侧面310s、320s、330s、340s的斜坡件410、420、430、440可以保护侧面310s、320s、330s、340s。
半导体堆叠结构100还包含晶片粘着件921、922、923、924。晶片粘着件921设置于支持面200s与底面310b之间。晶片粘着件922设置于顶面310t与底面320b之间。晶片粘着件923设置于顶面320t与底面330b之间。晶片粘着件924设置于顶面330t与底面340b之间。
在一些实施方式中，晶片粘着件921、922、923、924的材质与斜坡件410、420、430、440的材质相同。应了解到，以上所举的晶片粘着件921、922、923、924与斜坡件410、420、430、440的具体实施方式仅为例示，并非用以限制本发明，本发明所属技术领域中的技术人员，应视实际需要，弹性选择晶片粘着件921、922、923、924与斜坡件410、420、430、440的具体实施方式。
半导体堆叠结构100还包含封装件930。封装件930设置于支持面200s上且覆盖电子元件310、320、330、340。
在一些实施方式中，重分布层510的材质为铜。应了解到，以上所举的重分布层510的材质仅为例示，并非用以限制本发明，本发明所属技术领域中的技术人员，应视实际需要，弹性选择重分布层510的材质。
图2绘示依照本发明另一实施方式的半导体堆叠结构100的剖面示意图。如图2所绘示，本实施方式的半导体堆叠结构100类似于图1的半导体堆叠结构100，以下将描述两者的主要差异。
电子元件310、320、330、340在基板200上的正投影大致相同。换句话说，电子元件310、320、330、340互相对齐。
进一步来说，电子元件320覆盖接垫311，电子元件330覆盖接垫321，电子元件340覆盖接垫331。因此，接垫311在基板200上的正投影与电子元件320在基板200上的正投影重叠，接垫321在基板200上的正投影与电子元件330在基板200上的正投影重叠，接垫331在基板200上的正投影与电子元件340在基板200上的正投影重叠。
斜坡件420设置于斜面410i上，斜坡件430设置于斜面420i上，斜坡件440设置于斜面430i上。
半导体堆叠结构100还包含重分布层520、530、540。重分布层520设置于斜面420i与顶面320t且电性连接接垫210、321。重分布层530设置于斜面430i与顶面330t且电性连接接垫210、331。重分布层540设置于斜面440i与顶面340t且电性连接接垫210、341。
另外，重分布层510的一部分设置于斜坡件410、420之间。重分布层520的一部分设置于斜坡件420、430之间。重分布层530的一部分设置于斜坡件430、440之间。
在本实施方式中，重分布层510、520、530、540之间互相电性绝缘，但不限于此。在一些实施方式中，重分布层510、520、530、540之间可能互相电性连接。
在本实施方式中，斜坡件410裸露侧面310s的至少一部分。斜坡件420裸露侧面320s的至少一部分。斜坡件430裸露侧面330s的至少一部分。斜坡件440裸露侧面340s的至少一部分。通过上述配置，将可以避免斜坡件410、420、430、440所产生的应力破坏电子元件310、320、330、340的情形。
进一步来说，重分布层510还设置于侧面310s上。重分布层520还设置于侧面320s上。重分布层530还设置于侧面330s上。重分布层540还设置于侧面340s上。
图3绘示依照本发明另一实施方式的半导体堆叠结构100的剖面示意图。如图3所绘示，本实施方式的半导体堆叠结构100与图2的半导体堆叠结构100类似，两者的主要差异在于，在本实施方式中，重分布层510、520、530、540之间互相电性连接。
图4至图9绘示依照本发明一实施方式的半导体堆叠结构100的工艺的各步骤的剖面示意图。如图4所绘示，设置晶片粘着件921于基板200的支持面200s。
如图5所绘示，设置电子元件310于晶片粘着件921上，以紧压晶片粘着件921。然后，部分的晶片粘着件921会被挤出而形成斜坡件410，且电子元件310为固定于基板200。
如图6所绘示，类似于图4与图5，设置晶片粘着件922于电子元件310的顶面310t上。然后，设置电子元件320于晶片粘着件922上。电子元件320没有对齐电子元件310。
如图7所绘示，进行类似于图4与图6的工艺。于是，电子元件310、320、330、340为依序堆叠，且电子元件310、320、330、340没有互相对齐。晶片粘着件922设置于电子元件310、320之间。晶片粘着件923设置于电子元件320、330之间。晶片粘着件924设置于电子元件330、340之间。形成了斜坡件420、430、440。
然后，形成图案化光阻991于基板200的支持面200s、斜坡件410的斜面410i、电子元件310的顶面310t、斜坡件420的斜面420i、电子元件320的顶面320t、斜坡件430的斜面430i、电子元件330的顶面330t、斜坡件440的斜面440i以及电子元件340的顶面340t上。
如图8所绘示，形成重分布层510于基板200的支持面200s与接垫210、斜坡件410的斜面410i、电子元件310的接垫311与顶面310t、斜坡件420的斜面420i、电子元件320的接垫321与顶面320t、斜坡件430的斜面430i、电子元件330的接垫331与顶面330t、斜坡件440的斜面440i以及电子元件340的接垫341与顶面340t上。然后，移除图案化光阻991。于是，重分布层510电性连接接垫210、311、321、331、341。
如图9所绘示，形成封装件930以覆盖支持面200s、电子元件310、320、330、340以及重分布层510。然后，形成多个焊球910于基板200相对于支持面200s的一面200b。本实施方式的半导体堆叠结构100可以对应于图1的半导体堆叠结构100。
图10至图14绘示依照本发明另一实施方式的半导体堆叠结构100的工艺的各步骤的剖面示意图。如图10所绘示，设置晶片粘着件921于基板200的支持面200s上。然后，设置电子元件310于晶片粘着件921上，以紧压晶片粘着件921。
如图11所绘示，部分的晶片粘着件921会被挤出而形成斜坡件410，且电子元件310为固定于基板200。然后，形成图案化光阻992于基板200的支持面200s以及斜坡件410的斜面410i上。然后，形成重分布层510于基板200的支持面200s与接垫210、斜坡件410的斜面410i以及电子元件310的接垫311与顶面310t上。因此，重分布层510电性连接接垫210、311。
如图12所绘示，类似于图10，在移除图案化光阻992后，设置晶片粘着件922于电子元件310的顶面310t上。然后，设置电子元件320于晶片粘着件922上，且电子元件320对齐电子元件310。
如图13所绘示，进行类似于图10至图12的工艺。于是，电子元件310、320、330、340为依序堆叠，且电子元件310、320、330、340互相对齐。晶片粘着件922设置于电子元件310、320之间。晶片粘着件923设置于电子元件320、330之间。晶片粘着件924设置于电子元件330、340之间。形成斜坡件420于斜坡件410的斜面410i上。形成斜坡件430于斜坡件420的斜面420i上。形成斜坡件440于斜坡件430的斜面430i上。形成重分布层520于基板200的支持面200s与接垫210、斜坡件420的斜面420i以及电子元件320的接垫321与顶面320t上。形成重分布层530于基板200的支持面200s与接垫210、斜坡件430的斜面430i以及电子元件330的接垫331与顶面330t上。形成重分布层540于基板200的支持面200s与接垫210、斜坡件440的斜面440i以及电子元件340的接垫341与顶面340t上。于是，重分布层520电性连接接垫210、321，重分布层530电性连接接垫210、331，重分布层540电性连接接垫210、341。
如图14所绘示，形成封装件930以覆盖支持面200s、电子元件310、320、330、340以及重分布层540。然后，形成多个焊球910于基板200相对于支持面200s的一面200b。本实施方式的半导体堆叠结构100可以对应于图2的半导体堆叠结构100。
通过利用重分布层510电性连接接垫210、311、321、331、341，基板200以及堆叠的电子元件310、320、330、340将会互相电性连接。相较于使用引线焊接的方法，使用本方法将可以避免不同引线可能会短路的情况。在此同时，因为半导体堆叠结构100中没有引线，其会占据极大的空间，所以半导体堆叠结构100的尺寸将会较小。
另外，因为半导体堆叠结构100中没有穿透硅通孔，其价格较为昂贵，因此半导体堆叠结构100的制造成本将能有效降低。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何所属领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (17)

1.一种半导体堆叠结构，其特征在于，包含：
基板，具有支持面，其中所述基板包含第一接垫，所述第一接垫设置于所述支持面上；
第一电子元件，设置于所述支持面上且具有第一底面、第一顶面以及连接所述第一底面与所述第一顶面的第一侧面，其中所述第一电子元件包含第二接垫，所述第二接垫设置于所述第一顶面上；
第一斜坡件，设置于所述支持面与所述第一侧面上且具有第一斜面，所述第一斜坡件裸露所述第一侧面的一上部分；
第一重分布层，设置于所述支持面、所述第一顶面、所述第一侧面的所述上部分以及所述第一斜面上，且电性连接所述第一接垫与所述第二接垫；以及
晶片粘着件，设置于所述支持面与所述第一底面之间，其中所述晶片粘着件的材质与所述第一斜坡件的材质相同，且所述晶片粘着件与所述第一斜坡件为一体成形。
2.如权利要求1所述的半导体堆叠结构，其特征在于，所述基板还包含本体与至少一个第二重分布层，其中所述第二重分布层设置于所述本体中。
3.如权利要求1所述的半导体堆叠结构，其特征在于，还包含：
多个焊球，设置于所述基板相对于所述支持面的一面。
4.如权利要求1所述的半导体堆叠结构，其特征在于，还包含：
封装件，设置于所述支持面上且覆盖所述第一电子元件。
5.如权利要求1所述的半导体堆叠结构，其特征在于，所述第一电子元件为晶片。
6.如权利要求1所述的半导体堆叠结构，其特征在于，所述第一斜坡件覆盖所述第一侧面。
7.如权利要求1所述的半导体堆叠结构，其特征在于，还包含：
第二电子元件，设置于所述第一顶面上且具有第二底面、第二顶面以及连接所述第二底面与所述第二顶面的第二侧面，其中所述第二电子元件包含第三接垫，所述第三接垫设置于所述第二顶面上；以及
第二斜坡件，设置于所述第二侧面上且具有第二斜面。
8.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二斜坡件还设置于所述第一顶面上，所述第一重分布层还设置于所述第二斜面与所述第二顶面上且还电性连接所述第三接垫。
9.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二斜坡件还设置于所述第一斜面上；以及所述半导体堆叠结构还包含：
第二重分布层，设置于所述第二斜面与所述第二顶面上且电性连接所述第一接垫与所述第三接垫。
10.如权利要求9所述的半导体堆叠结构，其特征在于，所述第一重分布层电性连接所述第二重分布层。
11.如权利要求9所述的半导体堆叠结构，其特征在于，所述第一重分布层与所述第二重分布层电性绝缘。
12.如权利要求7所述的半导体堆叠结构，其特征在于，所述第一电子元件在所述基板上的正投影与所述第二电子元件在所述基板上的正投影大致相同。
13.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二电子元件在所述基板上的正投影的一部分与所述第一电子元件在所述基板上的正投影不重叠。
14.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二电子元件覆盖所述第二接垫。
15.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二电子元件没有覆盖所述第二接垫。
16.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二接垫在所述基板上的正投影与所述第二电子元件在所述基板上的正投影重叠。
17.如权利要求7所述的半导体堆叠结构，其特征在于，所述第二接垫在所述基板上的正投影与所述第二电子元件在所述基板上的正投影不重叠。
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