CN108735576A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108735576A CN108735576A CN201710276849.5A CN201710276849A CN108735576A CN 108735576 A CN108735576 A CN 108735576A CN 201710276849 A CN201710276849 A CN 201710276849A CN 108735576 A CN108735576 A CN 108735576A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 238000011282 treatment Methods 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 34
- 239000007789 gas Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
- 230000008569 process Effects 0.000 description 11
- 230000007547 defect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 239000005864 Sulphur Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- -1 sulphur Compound Chemical class 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A kind of semiconductor structure of present invention offer and forming method thereof, the forming method includes：Substrate is provided；Plasma vulcanizing treatment is carried out to the substrate；After carrying out plasma vulcanizing treatment to the substrate, high-K dielectric layer is formed on the substrate.The semiconductor structure electric property that forming method of the present invention is formed is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the rapid development of semiconductor technology, the characteristic size of semiconductor structure constantly reduces so that integrated circuit
Integrated level is higher and higher, and higher requirements are also raised for this performance to device.
Currently, as the size of Metal-Oxide Semiconductor field-effect transistor (MOSFET) constantly becomes smaller.In order to adapt to
The reduction of process node can only constantly shorten the channel length of MOSFET field-effect tube.The shortening of channel length, which has, increases core
The benefits such as the tube core density of piece, the switching speed for increasing MOSFET field-effect tube.
However, with the shortening of device channel length, device source electrode between drain electrode at a distance from also shorten therewith, so
Grid is deteriorated to the control ability of raceway groove, and the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing so that sub- valve
It is worth leaky, i.e. short-channel effect (SCE：Short-channel effects) become a most important technical problem.
Therefore, in order to preferably adapt to the scaled requirement of device size, semiconductor technology gradually starts from plane
Transistor transient from mosfet transistor to the three-dimensional with more high effect, such as fin field effect pipe (FinFET).
FinFET has good channel controllability.
However, the electric property for the semiconductor structure that the prior art is formed is to be improved.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the electricity of semiconductor structure
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；To institute
It states substrate and carries out plasma vulcanizing treatment；After plasma vulcanizing treatment being carried out to the substrate, shape on the substrate
At high-K dielectric layer.
Optionally, the step of plasma vulcanizing treatment includes：The substrate is carried out to mix sulphuring treatment；Mix sulphuring treatment it
Afterwards, the substrate is made annealing treatment.
Optionally, using plasma H2S gases carry out the substrate to mix sulphuring treatment.
Optionally, using plasma H2The technological parameter that S gases to the substrate mix sulphuring treatment includes：It is passed through H2S
Gas, the H2The gas flow of S gases is 40sccm to 120sccm, and power is 500w to 1200w, pressure 0.5mtorr
To 20mtorr, temperature is 500 DEG C to 1050 DEG C, and the time is 60s to 150s.
Optionally, the technological parameter of the annealing includes：Temperature be 400 DEG C to 1100 DEG C, the time be 80s extremely
120s。
Optionally, the substrate is single layer structure or laminated construction.
Optionally, the material of the substrate is：InP,InxGa1-xOne or more of As or GaN.
Optionally, the technique for providing the substrate is selective epitaxial growth or metal organic chemical vapor deposition.
Optionally, the material of the high-K dielectric layer is：Al2O3Or HfO2One or more of.
Optionally, the technique for forming the high-K dielectric layer is physical vapour deposition (PVD), chemical vapor deposition or atomic layer deposition
Product.
Correspondingly, the present invention also provides a kind of semiconductor structures, including：Substrate, to the substrate using plasma sulphur
Compound is handled；High-K dielectric layer is located in the substrate.
Optionally, the substrate is single layer structure or laminated construction.
Optionally, the material of the substrate is：InP,InxGa1-xOne or more of As or GaN.
Optionally, the material of the high-K dielectric layer is：Al2O3Or HfO2One or more of.
Compared with prior art, technical scheme of the present invention has the following advantages：
Substrate is first provided, then plasma vulcanizing treatment is carried out to the substrate, forms high K on the substrate again later
Dielectric layer.The substrate is carried out using plasma sulfide gas to mix sulphuring treatment, since the plasma sulfide gas is mixed
Enter depth and the concentration of substrate convenient for control, enable to sulphion mix the substrate depth and concentration it is big, to rear
In continuous semiconductor high temperature process so that stability of the sulphion in the substrate is good, it is not easy to be lost in.The sulphur
Ion mixes in the substrate, the lattice defect in the substrate can be repaired, so as to improve the interface performance of the substrate.
In follow-up the step of forming the high-K dielectric layer on the substrate again, since the interface performance of the substrate is good, so that
The quality of the high-K dielectric layer is also improved, so that the leakage rate of semiconductor structure is reduced, therefore improves institute
State the electric property of semiconductor structure.
In alternative, using plasma H2S gases carry out the substrate to mix sulphuring treatment, specific process parameter packet
It includes：It is passed through H2S gases, the H2The gas flow of S gases is 40sccm to 120sccm, and power is 500w to 1200w, and pressure is
0.5mtorr to 20mtorr, temperature are 500 DEG C to 1050 DEG C, and the time is 60s to 150s.Due to the H2S gases are easy to be formed
Plasma (DPS plasma) mixes the technological parameter of sulphuring treatment by adjusting, by the process parameter control in model appropriate
In enclosing, the depth of sulphion incorporation substrate and concentration can be made larger, after subsequently being made annealing treatment again to the substrate, institute
It states sulphion to be activated in the substrate, and repairs the lattice defect in the substrate, so that the interface of the substrate
Performance is improved.Since the interface performance for mixing substrate after sulphur is good, when forming high-K dielectric layer on the substrate, accordingly
Ground also improves the quality of the high-K dielectric layer, therefore reduces the leakage rate of the semiconductor structure.
Description of the drawings
Fig. 1 to Fig. 2 is the structural schematic diagram that semiconductor structure forms process；
Fig. 3 to Fig. 5 is the structural schematic diagram that semiconductor structure of the embodiment of the present invention forms process.
Specific implementation mode
Electric property according to the semiconductor structure of background technology formation is to be improved.Figures 1 and 2 show that semiconductor junction
It is configured to the structural schematic diagram of process, is carried out in conjunction with reason to be improved to the electric property of semiconductor structure Fig. 1 and Fig. 2
Analysis.
With reference to figure 1, substrate 100 is provided；Using (NH4)2S solution carries out the substrate 100 to mix sulphuring treatment.
With reference to figure 2, using (NH4)2S solution carries out after mixing sulphuring treatment the substrate 100, the shape in the substrate 100
At dielectric layer 110.
The semiconductor structure electric property that above-mentioned forming method is formed is to be improved.
It is found through analysis, the reason for causing the semiconductor structure electric property to be improved includes：Due to (the NH4)2S solution has larger corrosivity, using (NH4)2S solution carries out after mixing sulphuring treatment the substrate 100, is easy to described
Substrate 100 causes interface damage, to generate harmful effect to the interface performance of the substrate 100.Further, since using
(NH4)2After S solution treatments, sulphion mix the substrate 100 depth and concentration it is smaller, in Subsequent semiconductor high temperature process
In be easy to cause loss, the effect that 100 lattice defect of the substrate is repaired so as to cause sulphion is poor.
Using (NH4)2S solution carries out after mixing sulphuring treatment the substrate 100, also forms dielectric in the substrate 100
Layer 110, correspondingly will also result in the of poor quality of the dielectric layer 110.In conjunction in terms of above-mentioned two, the substrate 100 with it is described
Interface performance between dielectric layer 110 is poor, and the dielectric layer 110 is of poor quality, so as to cause the leakage of the semiconductor structure
Electric rate increases, therefore reduces the electric property of the semiconductor structure.
To solve the above-mentioned problems, in the embodiment of the present invention, the method for using plasma vulcanizing treatment is to the substrate
It carries out mixing sulphuring treatment, enables to sulphion stability in the substrate good, not easily run off, and the base can be repaired
The lattice defect at bottom, so as to improve the interface performance of the substrate.It is good accordingly, due to the interface performance of the substrate, from
And so that the quality of the high-K dielectric layer formed is also improved, it is reduced to the leakage rate of the semiconductor structure,
And then improve the electric property of the semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Fig. 5 is the structural schematic diagram that semiconductor structure of the embodiment of the present invention forms process.
With reference to figure 3, substrate 200 is provided.
In the present embodiment, the substrate 200 is single layer structure or laminated construction.
In the present embodiment, the substrate 200 selects the III-V material that can improve carrier mobility, specially：
InP、InxGa1-xOne or more of As or GaN.In other embodiments of the present invention, the material of the substrate may be used also
Think：One or more of Si, Ge, SiGe, SiC, GaAs or InGa.
In the present embodiment, the technique for providing the substrate 200 is selective epitaxial growth.Using selective epitaxial growth work
Artistic skill enough improves the lattice defect of the substrate 200, improves the quality of the substrate 200.In other embodiments of the present invention, shape
Technique at the substrate can also be metal organic chemical vapor deposition.
With reference to figure 4, plasma vulcanizing treatment is carried out to the substrate 200.
In the present embodiment, after mix sulphuring treatment to the substrate 200 using plasma sulfide gas so that sulphur from
The sub depth for mixing the substrate 200 and concentration are big, in Subsequent semiconductor high temperature process so that the sulphion is in institute
The stability stated in substrate 200 is good, it is not easy to be lost in.
The sulphion for mixing the substrate 200, for repairing the lattice defect in the substrate 200, so as to improve institute
State the interface performance of substrate 200.Subsequently again in the step of forming the high-K dielectric layer 210 in the substrate 200, by institute
The interface performance for stating substrate 200 is good, so that the quality of the high-K dielectric layer 210 is also improved.
In terms of in conjunction with above-mentioned two, since the interface performance between the substrate 200 and the high-K dielectric layer 210 is good, and
The quality of the high-K dielectric layer 210 is high, so that the leakage rate of semiconductor structure is reduced, therefore improves described half
The electric property of conductor structure.
In the present embodiment, the step of plasma vulcanizing treatment, includes：The substrate 200 is carried out to mix sulphuring treatment；
After mixing sulphuring treatment, the substrate 200 is made annealing treatment.
Specifically, in described the step of mixing sulphuring treatment, using plasma H2S gases mix the substrate 200
Sulphuring treatment.Due to the H2S gases are readily formed plasma, by adjusting the plasma H2S gases mix sulphuring treatment
Technological parameter can make the depth of sulphion incorporation substrate 200 and concentration larger.After mixing sulphuring treatment described in progress, to institute
It states substrate 200 to be made annealing treatment so that the sulphion is activated in the substrate 200, and the base is repaired to play
The effect of lattice defect in bottom 200, and then improve the interface performance of the substrate 200.
In the present embodiment, using plasma H2S gases to the substrate 200 mix the technological parameter packet of sulphuring treatment
It includes：It is passed through H2S gases, the H2The gas flow of S gases is 40sccm to 120sccm, and power is 500w to 1200w, and pressure is
0.5mtorr to 20mtorr, temperature are 500 DEG C to 1050 DEG C, and the time is 60s to 150s.
The H2S gases are easy to form plasma, by the process parameter control for mix sulphuring treatment appropriate
In range, enable to that sulphion mixes the depth of the substrate 200 and concentration meets the needs of semiconductor structure.For example, this
In embodiment, the plasma H2The gas flow of S gases is within the scope of 40sccm to 120sccm.If the plasma
H2The gas flow of S gases is too small, then the concentration that sulphion mixes can be caused too small, to influence 200 interface of the substrate
Repairing performance；If the plasma H2The gas flow of S gases is excessive, then can be produced again to the electric property of the substrate 200
Raw harmful effect.In the present embodiment, the power for mixing sulphuring treatment is within the scope of 40sccm to 120sccm.If described mix at sulphur
The power of reason is too small, then the depth of sulphion incorporation substrate 200 can be caused inadequate；If the power for mixing sulphuring treatment is excessive, again
200 surface of the substrate can be caused to damage.
In the present embodiment, the technological parameter of the annealing includes：Temperature be 400 DEG C to 1100 DEG C, the time be 80s extremely
120s.If the temperature of the annealing is too low, the time is too short, then so that the sulphion in the substrate 200 is difficult quilt
Activation plays a role；If the temperature of the annealing is excessively high, overlong time, and the sulphion can be caused to be easy to diffuse out
It goes so that the effect that sulphion repairs lattice defect in substrate 200 is poor.
High K is formed in the substrate 200 after carrying out plasma vulcanizing treatment to the substrate 200 with reference to figure 5
Dielectric layer 210.
In the present embodiment, due in the substrate 200 doped with sulphion, and have good interface performance so that
The quality of the high-K dielectric layer 210 formed in the substrate 200 is high.The high-K dielectric layer 210 has good insulation performance, and
The leakage rate of the semiconductor structure can be reduced.The material of the high-K dielectric layer 210 is：Al2O3Or HfO2In one kind
Or it is a variety of.
In the present embodiment, the technique for forming the high-K dielectric layer 210 is：Physical vapour deposition (PVD), chemical vapor deposition or
Atomic layer deposition.
Correspondingly, the present invention also provides a kind of semiconductor structures, with reference to figure 5, including：Substrate 200, to the substrate 200
Using plasma sulfide is handled；High-K dielectric layer 210 is located in the substrate 200.
In the present embodiment, the depth and concentration of the doping sulphion of the substrate 200 are larger, in Subsequent semiconductor high temperature
In processing procedure, there is preferable stability, it is not easy to spread.Meanwhile the sulphion in the substrate 200 can play
The effect for repairing 200 lattice defect of substrate, is conducive to the interface performance for improving the substrate 200.Accordingly, due to the substrate
200 with interface performance, the quality of the high-K dielectric layer 210 formed in the substrate 200 are preferable well.In conjunction with above-mentioned two
A aspect, due to having good interface performance, and the high K dielectric between the substrate 200 and the high-K dielectric layer 210
Layer 210 it is high-quality, to reduce the leakage rate of the semiconductor structure, improve the electrical property of the semiconductor structure
Energy.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided；
Plasma vulcanizing treatment is carried out to the substrate；
After carrying out plasma vulcanizing treatment to the substrate, high-K dielectric layer is formed on the substrate.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of the plasma vulcanizing treatment
Suddenly include：
The substrate is carried out to mix sulphuring treatment；
After mixing sulphuring treatment, the substrate is made annealing treatment.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that using plasma H2S gases are to institute
Substrate is stated to carry out mixing sulphuring treatment.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that using plasma H2S gases are to institute
It states substrate and mix the technological parameter of sulphuring treatment and include：It is passed through H2S gases, the H2The gas flow of S gases be 40sccm extremely
120sccm, power are 500w to 1200w, and pressure is 0.5mtorr to 20mtorr, and temperature is 500 DEG C to 1050 DEG C, and the time is
60s to 150s.
5. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the technological parameter of the annealing
Including：Temperature is 400 DEG C to 1100 DEG C, and the time is 80s to 120s.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate be single layer structure or
Laminated construction.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the substrate is：InP,
InxGa1-xOne or more of As or GaN.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the technique for providing the substrate is choosing
The epitaxial growth of selecting property or metal organic chemical vapor deposition.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the high-K dielectric layer is：
Al2O3Or HfO2One or more of.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that form the work of the high-K dielectric layer
Skill is physical vapour deposition (PVD), chemical vapor deposition or atomic layer deposition.
11. a kind of semiconductor structure, which is characterized in that including：
Substrate handles the substrate using plasma sulfide；
High-K dielectric layer is located in the substrate.
12. semiconductor structure as claimed in claim 11, which is characterized in that the substrate is single layer structure or lamination knot
Structure.
13. semiconductor structure as claimed in claim 12, which is characterized in that the material of the substrate is：InP,InxGa1-xAs
Or one or more of GaN.
14. semiconductor structure as claimed in claim 11, which is characterized in that the material of the high-K dielectric layer is：Al2O3Or
HfO2One or more of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710276849.5A CN108735576A (en) | 2017-04-25 | 2017-04-25 | Semiconductor structure and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710276849.5A CN108735576A (en) | 2017-04-25 | 2017-04-25 | Semiconductor structure and forming method thereof |
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| CN101894922A (en) * | 2010-06-29 | 2010-11-24 | 深圳丹邦投资集团有限公司 | Organic light-emitting device and composite anode and manufacturing method thereof |
| CN102938371A (en) * | 2012-11-28 | 2013-02-20 | 中国科学院微电子研究所 | Method for preparing n+/ p-type ultra-shallow junction on p-type Ge substrate |
| CN104157737A (en) * | 2014-08-18 | 2014-11-19 | 电子科技大学 | Method of manufacturing high-infrared absorption silicon material |
| US9553031B1 (en) * | 2016-04-01 | 2017-01-24 | Lam Research Corporation | Method for integrating germanides in high performance integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101894922A (en) * | 2010-06-29 | 2010-11-24 | 深圳丹邦投资集团有限公司 | Organic light-emitting device and composite anode and manufacturing method thereof |
| CN102938371A (en) * | 2012-11-28 | 2013-02-20 | 中国科学院微电子研究所 | Method for preparing n+/ p-type ultra-shallow junction on p-type Ge substrate |
| CN104157737A (en) * | 2014-08-18 | 2014-11-19 | 电子科技大学 | Method of manufacturing high-infrared absorption silicon material |
| US9553031B1 (en) * | 2016-04-01 | 2017-01-24 | Lam Research Corporation | Method for integrating germanides in high performance integrated circuits |
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