CN108695312B

CN108695312B - ESD protection circuit, ESD protection structure and forming method thereof

Info

Publication number: CN108695312B
Application number: CN201710229090.5A
Authority: CN
Inventors: 雷玮; 李宏伟; 罗婵; 季林燕
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-04-10
Filing date: 2017-04-10
Publication date: 2020-12-25
Anticipated expiration: 2037-04-10
Also published as: CN108695312A

Abstract

The invention provides an ESD protection circuit, an ESD protection structure and a forming method thereof, wherein the circuit comprises: the functional device comprises a device output end, a device input end and a first semiconductor transistor connected with the end, wherein the first semiconductor transistor comprises a first input end and a first output end, the first input end is connected with the device output end, the first output end is connected with the device input end, and when the first output end is higher than the first input end in potential and the potential difference between the first output end and the first input end is greater than the threshold on-state voltage of the first semiconductor transistor, the first semiconductor transistor is switched on; a second semiconductor transistor; a third semiconductor transistor. The ESD includes a circuit including a first semiconductor transistor. When the amount of charge on the first pad is large, the charge on the first pad can be released through the first semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit can be improved.

Description

ESD protection circuit, ESD protection structure and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to an ESD protection circuit, an ESD protection structure and a forming method thereof.

Background

Static electricity is an objective natural phenomenon, and various ways such as contact, friction, and induction between electrical appliances are generated. Static electricity has the characteristics of long-time accumulation, high voltage, low electric quantity, small current and short action time.

For electronic products, Electrostatic discharge (ESD) is a major factor affecting the reliability of integrated circuits. ESD is a rapid neutralization process of electrical charge. Due to the high electrostatic voltage, destructive consequences may be brought to the integrated circuit, resulting in failure of the integrated circuit. Therefore, in order to protect the integrated circuit from ESD, ESD protection circuits are also designed in the integrated circuit to protect the integrated circuit from ESD.

However, the protection performance of the ESD protection circuit formed in the prior art is poor.

Disclosure of Invention

The invention provides an ESD protection circuit, an ESD protection structure and a forming method thereof, which can improve the protection performance of the ESD protection circuit.

To solve the above problem, the present invention provides an ESD protection circuit, including: a functional device including a device output portion, a device input portion, and a connection portion; a first semiconductor transistor including a first input portion and a first output portion, the first input portion being connected to the device output portion, the first output portion being connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is larger than a threshold on voltage of the first semiconductor transistor; a second semiconductor transistor including a second input portion and a second output portion, the second output portion being connected to the device input portion, the second input portion being connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and a potential difference between the second output portion and the second input portion is larger than a threshold on voltage of the second semiconductor transistor; a third semiconductor transistor including a third input portion and a third output portion, the third output portion being connected to the connection portion, the third input portion being connected to the device output portion, the third semiconductor transistor being turned on when the third output portion potential is higher than the third input portion potential and a third output portion potential difference from the third input portion potential is larger than a threshold on voltage of the third semiconductor transistor.

Optionally, the first semiconductor transistor is a first PMOS transistor, a source of the first PMOS transistor is connected to the first input portion, the first output portion is connected to a drain of the first PMOS transistor, a gate of the first PMOS transistor is connected to the device input portion, and a threshold turn-on voltage of the first semiconductor transistor is a source-drain voltage when the first PMOS transistor is turned on; or, the first semiconductor transistor is a first diode, the first input part is connected with the anode of the first diode, the first output part is connected with the cathode of the first diode, and the threshold turn-on voltage of the first semiconductor transistor is the reverse breakdown voltage of the first diode; or, the first semiconductor transistor is a first PNP triode, the base of the first PNP triode is connected to the device input portion, the first input portion is connected to the collector of the first PNP triode, the first output portion is connected to the emitter of the first PNP triode, and the threshold turn-on voltage of the first semiconductor transistor is the turn-on voltage of the first PNP triode.

Optionally, the second semiconductor transistor is a second PMOS transistor, a gate of the second PMOS transistor is connected to the device input portion, the second input portion is connected to a source of the second PMOS transistor, the second output portion is connected to a drain of the second PMOS transistor, and a threshold turn-on voltage of the second semiconductor transistor is a source-drain voltage when the second PMOS transistor is turned on; or, the second semiconductor transistor is a second diode, the second input is connected to the anode of the second diode, the second output is connected to the cathode of the second diode, and the threshold turn-on voltage of the second semiconductor transistor is the reverse breakdown voltage of the second diode; or, the second semiconductor transistor is a second PNP triode, the base of the second PNP triode is connected to the device input portion, the second input portion is connected to the collector of the second PNP triode, the second output portion is connected to the emitter of the second PNP triode, and the threshold turn-on voltage of the second semiconductor transistor is the turn-on voltage of the second PNP triode.

Optionally, the third semiconductor transistor is a first NMOS transistor, a gate of the first NMOS transistor is connected to the device output portion, the third input portion is connected to a source of the first NMOS transistor, the third output portion is connected to a drain of the first NMOS transistor, and a threshold turn-on voltage of the third semiconductor transistor is a source-drain voltage when the first NMOS transistor is turned on; or the third semiconductor transistor is a third diode, the third input part is connected with the anode of the third diode, the third output part is connected with the cathode of the third diode, and the threshold on-voltage of the third semiconductor transistor is the reverse breakdown voltage of the third diode; or the third semiconductor transistor is a first NPN triode, a base of the first NPN triode is connected to the device output part, the third input part is connected to an emitter of the first NPN triode, the third output part is connected to a collector of the first NPN triode, and a threshold turn-on voltage of the third semiconductor transistor is a turn-on voltage of the first NPN triode.

Optionally, the method further includes: a fourth semiconductor transistor including a fourth input and a fourth output, the fourth output being connected to the device input, the fourth semiconductor transistor being turned on when the fourth output potential is higher than the fourth input potential and a fourth output potential is different from the fourth input potential by more than a threshold turn-on voltage of the fourth semiconductor transistor; a fifth semiconductor transistor including a fifth input and a fifth output, the fifth output being connected to the fourth input, the fifth input being connected to a device output, the fifth semiconductor transistor being turned on when the fifth output potential is higher than the fifth input potential and a fifth output potential is greater than a fifth input potential by a threshold turn-on voltage of the fifth semiconductor transistor.

Optionally, the fourth semiconductor transistor is a third PMOS transistor, a gate of the third PMOS transistor is connected to the device input portion, the fourth input portion is connected to a source of the third PMOS transistor, the fourth output portion is connected to a drain of the third PMOS transistor, and a threshold turn-on voltage of the fourth semiconductor transistor is a source-drain voltage when the third PMOS transistor is turned on; or, the fourth semiconductor transistor is a fourth diode, the fourth input part is connected to the anode of the fourth diode, the fourth output part is connected to the cathode of the fourth diode, and the threshold turn-on voltage of the fourth semiconductor transistor is the reverse breakdown voltage of the fourth diode; or, the fourth semiconductor transistor is a third PNP triode, the base of the third PNP triode is connected to the device input portion, the fourth input portion is connected to the collector of the third PNP triode, the fourth output portion is connected to the emitter of the third PNP triode, and the threshold turn-on voltage of the fourth semiconductor transistor is the turn-on voltage of the third PNP triode.

Optionally, the fifth semiconductor transistor is a second NMOS transistor, a gate of the second NMOS transistor is connected to the device output portion, the fifth input portion is connected to a source of the second NMOS transistor, the fifth output portion is connected to a drain of the second NMOS transistor, and a threshold turn-on voltage of the fifth semiconductor transistor is a source-drain voltage when the second NMOS transistor is turned on; or the fifth semiconductor transistor is a fifth diode, the fifth input part is connected with the anode of the fifth diode, the fifth output part is connected with the cathode of the fifth diode, and the threshold turn-on voltage of the fifth semiconductor transistor is the reverse breakdown voltage of the fifth diode; or the fifth semiconductor transistor is a second NPN triode, a base of the second NPN triode is connected to the device output part, the fifth input part is connected to an emitter of the second NPN triode, the fifth output part is connected to a collector of the second NPN triode, and the threshold turn-on voltage of the first semiconductor transistor is the turn-on voltage of the second NPN triode.

Optionally, the device further comprises a clamp circuit, wherein the clamp circuit comprises a clamp input end and a clamp output end, the clamp input end is connected with the device input portion, and the clamp output end is connected with the device output portion.

Optionally, the clamping circuit includes: the capacitor comprises a first capacitor end and a second capacitor end, the resistor comprises a first resistor end and a second resistor end, the second resistor end is connected with the first capacitor end, the clamping input end is connected with the first resistor end, and the clamping output end is connected with the second capacitor end.

Optionally, the device output is used for grounding.

Correspondingly, the invention also provides a method for forming the ESD protection structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a device region, a first protection region, a second protection region and a third protection region; forming a functional device in a device region of the substrate, the functional device including a device output, a device input, and a connection; forming a first semiconductor transistor in the first protection region of the substrate, wherein the first semiconductor transistor comprises a first input part and a first output part, the first input part is electrically connected with the device output part, the first output part is electrically connected with the device input part, and when the potential of the first output part is higher than that of the first input part and the potential difference between the first output part and the first input part is larger than the threshold turn-on voltage of the first semiconductor transistor, the first semiconductor transistor is turned on; forming a second semiconductor transistor in the second protection region of the substrate, wherein the second semiconductor transistor comprises a second input part and a second output part, the second output part is electrically connected with the device input part, the second input part is electrically connected with the connecting part, and when the second output part potential is higher than the second input part potential and the second output part potential difference with the second input part is larger than the threshold conducting voltage of the second semiconductor transistor, the second semiconductor transistor is conducted; and forming a third semiconductor transistor in the third protection region of the substrate, wherein the third semiconductor transistor comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with the device output part, the third output part is higher in potential than the third input part, and the third semiconductor transistor is turned on when the potential difference between the third output part and the third input part is greater than the threshold turn-on voltage of the third semiconductor transistor.

Optionally, the first semiconductor transistor is a first diode, and the first semiconductor transistor includes: the first P-type doped region is positioned in the first protection region substrate; a first N-type doped region in the first guard region substrate, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region; the second semiconductor transistor is a second diode, the second semiconductor transistor including: the second P-type doped region is positioned in the second protection region substrate; a second N-type doped region in the second guard region substrate, the second N-type doped region in contact with the second P-type doped region, the second input portion including the second P-type doped region, the second output portion including the second N-type doped region; the third semiconductor transistor is a third diode, the third semiconductor transistor including: a third P-type doped region in the third guard area substrate; a third N-type doped region in the third guard area substrate, the third N-type doped region in contact with the third P-type doped region, a third input portion comprising the third P-type doped region, and a third output portion comprising the third N-type doped region.

Optionally, the substrate includes a base and a fin portion located on the base; the functional device comprises a device conductive region in the device region substrate; a lightly doped region in the device conductive region, and a device doped region in the lightly doped region and the device conductive region; the first P-type doped region includes: a first P-type conductive region in the first protective region substrate; a first P-type heavily doped region in the first P-type conductive region; the step of forming the functional device and the first semiconductor transistor includes: forming a device conductive region in the device region substrate; forming a first P-type conductive region in the first protection region substrate; forming a mask layer on the first protection area substrate; performing light doping injection on the substrate by taking the mask layer as a mask to form a light doping area in the device area substrate; and forming a device doping area in the device area lightly doped area and the device conducting area, and forming a first P-type heavily doped area and a first N-type doping area in the first protection area first P-type conducting area.

Optionally, the mask layer further covers the second protection region and the third protection region.

Optionally, the substrate further includes a fourth protection region and a fifth protection region; further comprising: forming a fourth semiconductor transistor in a fourth protection region of the substrate, wherein the fourth semiconductor transistor comprises a fourth input portion and a fourth output portion, the fourth output portion is electrically connected with the device input portion, and when the potential of the fourth output portion is higher than that of the fourth input portion and the potential difference between the fourth output portion and the fourth input portion is larger than the threshold conducting voltage of the fourth semiconductor transistor, the fourth semiconductor transistor is conducted; and forming a fifth semiconductor transistor in a fifth protection area of the substrate, wherein the fifth semiconductor transistor comprises a fifth input part and a fifth output part, the fifth output part is electrically connected with the fourth input part, the fifth input part is electrically connected with a device output part, and when the potential of the fifth output part is higher than that of the fifth input part and the potential difference between the fifth output part and the fifth input part is greater than the threshold turn-on voltage of the fifth semiconductor transistor, the fifth semiconductor transistor is turned on.

Optionally, the fourth semiconductor transistor is a fourth diode, and the fourth semiconductor transistor includes: a fourth P-type doped region in the fourth guard area substrate; a fourth N-type doped region in the fourth guard region substrate, the fourth N-type doped region in contact with the fourth P-type doped region, the fourth input portion comprising the fourth P-type doped region, the fourth output portion comprising the fourth N-type doped region; the fifth semiconductor transistor is a fifth diode, the fifth semiconductor transistor including: a fifth P-type doped region in the fifth guard area substrate; a fifth N-type doped region in the fifth guard area substrate, the fifth N-type doped region being in contact with the fifth P-type doped region, the fifth input portion including the fifth P-type doped region, the fifth output portion including the fifth N-type doped region.

Optionally, the device output is used for grounding.

Correspondingly, the invention also provides an ESD protection structure, comprising: a substrate including a device region, a first protection region, a second protection region, and a third protection region; a functional device located in the substrate device region, the functional device including a device output, a device input, and a connection; a first semiconductor transistor located in the first protection region of the substrate, the first semiconductor transistor including a first input portion and a first output portion, the first input portion being electrically connected to the device output portion, the first output portion being electrically connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is greater than a threshold turn-on voltage of the first semiconductor transistor; a second semiconductor transistor located in a second protection region of the substrate, the second semiconductor transistor including a second input portion and a second output portion, the second output portion being electrically connected to the device input portion, the second input portion being electrically connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and the second output portion and second input portion potential difference is greater than a threshold turn-on voltage of the second semiconductor transistor; and the third semiconductor transistor is positioned in a third protection area of the substrate and comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with the device output part, the potential of the third output part is higher than that of the third input part, and when the potential difference between the third output part and the third input part is greater than the threshold conducting voltage of the third semiconductor transistor, the third semiconductor transistor is conducted.

Optionally, the first semiconductor transistor is a first diode, and the first semiconductor transistor includes: the first P-type doped region is positioned in the first protection region substrate; a first N-type doped region in the first guard region substrate, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region; alternatively, the first semiconductor transistor is a PMOS transistor, and the first semiconductor transistor includes: a first gate on the first protection region substrate, the first gate being connected to the first input; the first input part comprises a first source region, the first output part is connected with the first drain region; or, the first semiconductor transistor is a first PNP triode, and the first semiconductor transistor includes: the first base region is located between the first collector region and the first emitter region, the first base region is in contact with the first input portion, the first base region is in contact with the first emitter region, the first input portion comprises the first collector region, and the first output portion comprises the first emitter region.

Optionally, the substrate further includes a capacitor region and a resistor region, and the semiconductor structure further includes: a resistor in the substrate resistor area, the resistor including a first resistor portion and a second resistor portion, the first resistor portion being electrically connected to the device input portion; and the capacitor is positioned in the substrate capacitor area and comprises a first capacitor part and a second capacitor part, the first capacitor part is electrically connected with the second resistor part, and the second capacitor part is electrically connected with the device output part.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the ESD protection circuit according to the aspect of the present invention, the ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion connects static charge to the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

Further, the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor are diodes.

When the device output portion is grounded and the electrostatic charge accumulated on the connection portion is positive, the potential of the connection portion is high, the potential of the connection portion is higher than that of the device output portion, the first semiconductor transistor and the third semiconductor transistor are in reverse bias, and the second semiconductor transistor is in forward bias. The first semiconductor transistor is reverse breakdown turned on when a potential difference between the device input portion potential and the device output portion is greater than a reverse breakdown voltage of the first semiconductor transistor. The electrostatic charge can reach the device output part through the second semiconductor transistor and the first semiconductor transistor and be released, so that an electrostatic discharge path of the ESD protection circuit can be increased, and the performance of the formed ESD protection circuit is improved.

When the device output portion is grounded and the electrostatic charge accumulated at the connection portion is negative charge, the first semiconductor transistor is turned on in a forward direction. And when the potential difference between the device input part and the connecting part is larger than the reverse breakdown voltage of the second semiconductor transistor, the second semiconductor transistor is conducted in reverse breakdown mode, and the static charge can reach the device output part through the first semiconductor transistor and the second semiconductor transistor and be discharged.

When the device input part is grounded and the static charge accumulated on the connecting part is positive charge, the potential of the connecting part is higher, and the potential of the connecting part is higher than that of the device input part. When the potential difference between the connection portion potential and the device output portion is larger than the reverse breakdown voltage of the third semiconductor transistor, the third semiconductor transistor is in reverse breakdown and is conducted, and the first semiconductor transistor is in forward conduction. At this time, the electrostatic charge may reach the device input portion through the third semiconductor transistor and the first semiconductor transistor to be discharged.

When the device input portion is grounded and the electrostatic charge accumulated on the connection portion is negative charge, the third semiconductor transistor is turned on in a forward direction. When the potential difference between the device input section and the device output section is larger than the reverse breakdown voltage of the first semiconductor transistor, the first semiconductor transistor is reverse-broken down to be turned on. At this time, the electrostatic charge may reach the device output portion through the third semiconductor transistor and the first semiconductor transistor to be discharged.

In the method for forming a semiconductor structure according to the present invention, the ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion connects static charge to the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

Further, when the first semiconductor transistor is a diode, a mask layer is formed on the first protection region before the light doping injection, so that ions are not easily injected into the first protection region in the ion injection process, thereby being beneficial to reducing the reverse breakdown voltage of the first semiconductor transistor and improving the performance of the formed ESD protection structure.

Drawings

FIG. 1 is a schematic diagram of an ESD protection circuit;

FIG. 2 is a schematic diagram of an ESD protection circuit according to the present invention;

fig. 3 to fig. 6 are schematic structural diagrams of steps of a method for forming an ESD protection structure according to an embodiment of the present invention.

Detailed Description

Semiconductor structures have a number of problems, such as: the protection performance of the ESD protection circuit is poor.

The reason that the protection performance of the ESD protection circuit is poor is analyzed by combining a semiconductor structure forming method:

fig. 1 is a circuit diagram of an ESD protection circuit.

Referring to fig. 1, the ESD protection circuit includes: a functional device 100, the functional device 100 comprising a first end 121, a second end 122 and a connection 123; a pad 101 connected to the connection part 123; a first diode 111, the first diode 111 including a first input portion and a first output portion, the first input portion being connected to the connection portion 123, the first output portion being connected to the first end 121; a second diode 112, wherein the second diode 112 includes a second input portion and a second output portion, the second input portion is grounded, and the second output portion is connected to the connection portion 123.

When the second end 122 is used for grounding and a larger positive charge is accumulated on the pad 101, the voltage of the pad 101 is increased, which is easy to make the second diode 112 break down in the reverse direction, so that the positive charge on the pad 101 is released; when a large negative charge is accumulated on the pad 101, the voltage of the pad 101 is lowered, and the second diode 112 is easily turned on in the forward direction, so that the negative charge is released, and the functional device 100 can be protected. However, when the static electricity is discharged, the static electricity discharge path is less, so that the static electricity discharge speed is slower, and the protection effect on the functional device is less.

When a large positive charge is accumulated on the pad 101 when the first end 121 is grounded, the voltage of the pad 101 is increased, so that the first diode 111 is conducted in the forward direction, and the positive charge on the pad 101 is released; when a large negative charge is accumulated on the pad 101, the voltage of the pad 101 is lowered, and the first diode 111 is easily turned on in the forward direction, so that the negative charge is released, and the functional device 100 can be protected.

However, since static electricity can be discharged only through the first diode 111 or the second diode 112 when the static electricity is discharged, the path of the static electricity discharge is small, resulting in a slow static electricity discharge rate and thus a small protection effect on the functional device.

To solve the above technical problem, the present invention provides an ESD protection circuit, including: a functional device including a device output portion, a device input portion, and a connection portion; a first semiconductor transistor including a first input portion and a first output portion, the first input portion being connected to the device output portion, the first output portion being connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is larger than a threshold on voltage of the first semiconductor transistor; a second semiconductor transistor including a second input portion and a second output portion, the second output portion being connected to the device input portion, the second input portion being connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and a potential difference between the second output portion and the second input portion is larger than a threshold on voltage of the second semiconductor transistor; a third semiconductor transistor including a third input portion and a third output portion, the third output portion being connected to the connection portion, the third input portion being connected to the device output portion, the third semiconductor transistor being turned on when the third output portion potential is higher than the third input portion potential and a third output portion potential difference from the third input portion potential is larger than a threshold on voltage of the third semiconductor transistor.

Wherein the ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion couples a static charge into the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of the ESD protection circuit of the present invention.

Referring to fig. 2, the ESD protection circuit includes: a functional device 110, the functional device 110 including a device input section 111, a device output section 112, and a connection section 113; a first pad 141 connected to the connection portion 113; a first semiconductor transistor 121, wherein the first semiconductor transistor 121 includes a first input portion 121a and a first output portion 121b, the first input portion 121a is connected to the device output portion 112, the first output portion 121b is connected to the device input portion 111, and when the first output portion 121b is higher in potential than the first input portion 121a and a potential difference between the first output portion 121b and the first input portion 121a is larger than a threshold on voltage of the first semiconductor transistor 121, the first semiconductor transistor 121 is turned on; a second semiconductor transistor 122, the second semiconductor transistor 122 including a second input portion 122a and a second output portion 122b, the second output portion 122b being connected to the device input portion 111, the second input portion 122a being connected to the connection portion 113, the second semiconductor transistor 122 being turned on when the second output portion 122b is higher in potential than the second input portion 122a and the second output portion 122b is higher in potential difference from the second input portion 122a than a threshold on voltage of the second semiconductor transistor 122; and a third semiconductor transistor 123, wherein the third semiconductor transistor 123 includes a third input portion 123a and a third output portion 123b, the third output portion 123b is connected to the connection portion 113, the third input portion 123a is connected to the device output portion 112, and when the third output portion 123b is higher in potential than the third input portion 123a and the third output portion 123b is higher in potential difference from the third input portion 123a than a threshold on voltage of the third semiconductor transistor 123, the third semiconductor transistor 123 is turned on.

The functional device 110 is an integrated circuit for implementing different functions, and includes devices such as MOS transistors, triodes, inductors, and capacitors.

In this embodiment, the device output 112 is used for grounding. In other embodiments, the device input may also be grounded.

The first bonding pad 141 is used to electrically connect the functional device 110 to an external circuit. Static charge is easily accumulated on the first pad 141 due to the influence of the external environment.

The ESD protection circuit further comprises a clamp circuit 130, wherein the clamp circuit 130 comprises a clamp input 131 and a clamp output 132, the clamp input 131 is connected to the device input 111, and the clamp output 132 is connected to the device output 112. In other embodiments, the ESD protection circuit may also not include the clamp circuit.

In this embodiment, the first semiconductor transistor 121 is a first diode, the first input portion 121a is connected to an anode of the first diode, and the first output portion 121b is connected to a cathode of the first diode.

The threshold turn-on voltage of the first semiconductor transistor 121 is the reverse breakdown voltage of the first diode. When the voltage of the first input portion 121a is higher than the voltage of the first output portion 121b, the first diode is forward biased and the turn-on voltage of the first diode is lower, whereas when the voltage of the first input portion 121a is lower than the voltage of the first output portion 121b, the first diode is reverse biased and the reverse turn-on voltage of the first diode is high.

In another embodiment, the first semiconductor transistor is a first PMOS transistor, a source of the first PMOS transistor is connected to the first input portion, the first output portion is connected to a drain of the first PMOS transistor, a gate of the first PMOS transistor is connected to the device input portion, and a threshold turn-on voltage of the first semiconductor transistor is a source-drain voltage when the first PMOS transistor is turned on; or, the first semiconductor transistor is a first PNP triode, the base of the first PNP triode is connected to the device input portion, the first input portion is connected to the collector of the first PNP triode, the first output portion is connected to the emitter of the first PNP triode, and the threshold turn-on voltage of the first semiconductor transistor is the turn-on voltage of the first PNP triode.

In this embodiment, the second semiconductor transistor 122 is a second diode, the second input portion 122a is connected to an anode of the second diode, and the second output portion 122b is connected to a cathode of the second diode. The threshold turn-on voltage of the second semiconductor transistor 122 is the reverse breakdown voltage of the second diode.

When the voltage of the first pad 141 is higher than the voltage of the second output part 122b, the second diode is forward-biased and the turn-on voltage of the second diode is lower, whereas when the voltage of the first pad 141 is lower than the voltage of the second output part 122b, the second diode is reverse-biased and the reverse turn-on voltage of the second diode is high.

In another embodiment, the second semiconductor transistor is a second PMOS transistor, a gate of the second PMOS transistor is connected to the device input portion, the second input portion is connected to a source of the second PMOS transistor, the second output portion is connected to a drain of the second PMOS transistor, and a threshold turn-on voltage of the second semiconductor transistor is a source-drain voltage when the second PMOS transistor is turned on; or, the second semiconductor transistor is a second PNP triode, the base of the second PNP triode is connected to the device input portion, the second input portion is connected to the collector of the second PNP triode, the second output portion is connected to the emitter of the second PNP triode, and the threshold turn-on voltage of the second semiconductor transistor is the turn-on voltage of the first PNP triode.

In this embodiment, the third semiconductor transistor 123 is a third diode, the third input portion 123a is connected to the anode of the third diode, and the third output portion 132b is connected to the cathode of the third diode. The threshold turn-on voltage of the third semiconductor transistor 123 is the reverse breakdown voltage of the third diode.

When the voltage of the first pad 141 is lower than the voltage of the third input part 123a, the third diode is forward biased, and the turn-on voltage of the third diode is lower, whereas when the voltage of the first pad 141 is higher than the voltage of the third input part 123a, the third diode is reverse biased, and the reverse turn-on voltage of the third diode is high.

In other embodiments, the third semiconductor transistor is a first NMOS transistor, a gate of the first NMOS transistor is connected to the device output portion, the third input portion is connected to a source of the first NMOS transistor, the third output portion is connected to a drain of the first NMOS transistor, and a threshold turn-on voltage of the third semiconductor transistor is a source-drain voltage when the first NMOS transistor is turned on; or the third semiconductor transistor is a first NPN triode, a base of the first NPN triode is connected to the device output part, the third input part is connected to an emitter of the first NPN triode, the third output part is connected to a collector of the first NPN triode, and a threshold turn-on voltage of the third semiconductor transistor is a turn-on voltage of the first NPN triode.

Note that the ESD protection circuit includes a first semiconductor transistor 121, a second semiconductor transistor 122, and a third semiconductor transistor 123, and the connection portion 113 couples electrostatic charges into the first semiconductor transistor 121, the second semiconductor transistor 122, and the third semiconductor transistor 123. When the charge amount on the connection portion 113 is large, the charge on the connection portion 113 can be released through the first semiconductor transistor 121 and the second semiconductor transistor 122, or the first semiconductor transistor 121 and the third semiconductor transistor 123, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit can be improved.

Specifically, in this embodiment, the device output portion 112 is grounded. When the device output portion 112 is grounded and a large amount of positive charges are accumulated on the first pad 141, the connection portion 113 is higher in potential than the device output portion 112, the first and

third semiconductor transistors

121 and 123 are reverse-biased, and the second semiconductor transistor 122 is forward-biased. When the potential difference between the device input part 111 and the device output part 112 is larger than the reverse breakdown voltage of the first semiconductor transistor 121, the electrostatic charge can reach the device output part 112 through the second semiconductor transistor 122 and the first semiconductor transistor 121 to be discharged, so that the electrostatic discharge path of the ESD protection circuit can be increased, and the performance of the formed ESD protection circuit can be improved; and when the potential difference between the connection portion 113 and the device output portion 112 is greater than the reverse breakdown voltage of the third semiconductor transistor 123, the third semiconductor transistor 123 is turned on in the reverse direction, and the electrostatic charge can be discharged through the third semiconductor transistor 123.

When a large amount of negative charges accumulate on the first pad 141, the potential of the first pad 141 is low, and the device output portion 112 is higher than the connection portion 113; the first and

third semiconductor transistors

121 and 123 are forward biased and the second semiconductor transistor 122 is reverse biased. The static charge may be discharged through the third semiconductor transistor 123. Further, when the potential difference between the device input portion 111 and the connection portion 113 is larger than the reverse breakdown voltage of the second semiconductor transistor 122, the first semiconductor transistor 121 is reverse breakdown-conductive, the first semiconductor transistor 121 is forward-conductive, and the electrostatic charge may reach the device output portion 112 through the first and

second semiconductor transistors

121 and 122 to be discharged.

Thus, when the amount of positive or negative charges accumulated on the first pad 141 is large, the static charge can form a discharge path with the first semiconductor transistor 121 through one of the second semiconductor transistor 122 or the third semiconductor transistor 123, so that a discharge path of the static charge can be increased, and the protection performance of the ESD protection circuit can be increased.

In other embodiments, the device input may also be grounded. When the device input part is grounded and a large amount of positive charges are accumulated on the first bonding pad, the potential of the first bonding pad is higher, the potential of the connecting part is higher than that of the device input part at the moment, and the first semiconductor transistor is in forward bias. When a potential difference between the connection portion potential and the device input portion is larger than a reverse breakdown voltage of the third semiconductor transistor, the third semiconductor transistor is reversely broken down to be turned on. At this time, the electrostatic charge may reach the device input portion through the third semiconductor transistor and the first semiconductor transistor to be discharged.

When the device input portion is grounded and a large amount of negative charges accumulate on the first pad, the potential of the first pad is low, the potential of the device input portion is higher than that of the connecting portion at the moment, the first semiconductor transistor is in reverse bias, the third semiconductor transistor is in forward bias, and the third semiconductor transistor is in forward conduction. When the potential difference between the device input section and the device output section is larger than the reverse breakdown voltage of the first semiconductor transistor, the first semiconductor transistor is reverse-broken down to be turned on. At this time, the electrostatic charge may reach the device output portion through the third semiconductor transistor and the first semiconductor transistor to be discharged.

In this embodiment, the ESD protection circuit further includes: a clamp circuit 130, said clamp circuit 130 comprising a clamp input 131 and a clamp output 132, said clamp input 131 being connected to said device input 111 and said clamp output 132 being connected to said device output 112.

The clamp circuit 130 is configured to clamp a voltage between the device input portion 111 and the device output portion 112 so that the voltage between the device input portion 111 and the device output portion 112 is not too high.

Specifically, in this embodiment, the clamping circuit 130 includes a capacitor and a resistor, and the capacitor is connected in series with the resistor. The capacitor comprises a first capacitor end and a second capacitor end, the resistor comprises a first resistor end and a second resistor end, the second resistor end is connected with the first capacitor end, the clamping input end is connected with the first resistor end, and the clamping output end is connected with the second capacitor end. In other embodiments, the clamp circuit may further include a transistor.

The clamp circuit 130 has a small on-state voltage, and when the electrostatic charge accumulated on the first pad 141 is small, the clamp circuit 130 is also turned on to discharge the electrostatic charge on the first pad 141, so that the voltage between the device output portion 112 and the device input portion 111 maintains a small stable value. On the other hand, when the electrostatic charge accumulated on the first pad 141 is large, the electrostatic discharge capability of the clamp circuit 130 is limited, and it is difficult to suppress the influence of the electrostatic charge on the voltage between the device output portion 112 and the device input portion 111, and at this time, the first semiconductor transistor 121 is turned on, and a part of the electrostatic charge can be discharged, thereby reducing the influence of the electrostatic charge on the voltage between the device output portion 112 and the device input portion 111.

In this embodiment, the ESD protection circuit further includes a fourth semiconductor transistor 124, the fourth semiconductor transistor 124 includes a fourth input portion 124a and a fourth output portion 124b, the fourth output portion 124b is connected to the device input portion 111, and when the fourth output portion 124b is higher in potential than the fourth input portion 124a and the potential difference between the fourth output portion 124b and the fourth input portion 124a is greater than the threshold turn-on voltage of the fourth semiconductor transistor 124, the fourth semiconductor transistor 124 is turned on; a fifth semiconductor transistor 125, wherein the fifth semiconductor transistor 125 includes a fifth input 125a and a fifth output 125b, the fifth output 125b is connected to the fourth input 124a, the fifth input 125a is connected to the device output 112, and when the fifth output 125b is higher in potential than the fifth input 125a and the potential difference between the fifth output 125b and the fifth input 125a is greater than the threshold turn-on voltage of the fifth semiconductor transistor 125, the fifth semiconductor transistor 125 is turned on; and a second pad 142 connected to the fourth input portion 124 a.

The fourth semiconductor transistor 124, the fifth semiconductor transistor 125 and the second pad 142 are used to increase an electrostatic discharge path of the ESD protection circuit.

In this embodiment, the second pad 142 is grounded.

When a large amount of positive charges are accumulated on the first pad 141, the first pad 141 is higher in potential than the second pad 142, the second semiconductor transistor 122 and the fifth semiconductor transistor 125 are forward-biased, and the first semiconductor transistor 121, the third semiconductor transistor 123, and the fourth semiconductor transistor 124 are reverse-biased. When the potential difference between the device input section 111 and the device output section 112 is larger than the reverse breakdown voltage of the first semiconductor transistor 121, the electrostatic charge on the first pad 141 reaches the second pad 142 through the second semiconductor transistor 122, the first semiconductor transistor 121, and the fifth semiconductor transistor 125, and is discharged; when the difference between the potential of the device input portion 111 and the potential of the fourth input portion 124a is larger than the reverse breakdown voltage of the fourth semiconductor transistor 124, the electrostatic charge on the first pad 141 is discharged to the second pad 142 through the second semiconductor transistor 122 and the fourth semiconductor transistor 124.

When a large amount of negative charges are accumulated on the first pad 141, the third semiconductor transistor 123 and the fourth semiconductor transistor 124 are forward biased, and the first semiconductor transistor 121, the second semiconductor transistor 122 and the fifth semiconductor transistor 125 are reverse biased. When the potential difference between the device input section 111 and the device output section 112 is larger than the reverse breakdown voltage of the first semiconductor transistor 121, the electrostatic charge on the first pad 141 reaches the second pad 142 through the second semiconductor transistor 122, the first semiconductor transistor 121, and the fourth semiconductor transistor 125, and is discharged; when the potential difference between the device input portion 111 and the connection portion 113 is higher than the reverse breakdown voltage of the second semiconductor transistor 122, the electrostatic charge on the first pad 141 can be discharged by the electrostatic charge on the first pad 141 reaching the second pad 142 through the second semiconductor transistor 122 and the fourth semiconductor transistor 124; when the potential difference between the second pad 142 and the fifth input portion 125a is larger than the reverse breakdown voltage of the fifth semiconductor transistor, the electrostatic charge on the first pad 141 reaches the second pad 142 through the second semiconductor transistor 122 and the fifth semiconductor transistor 125, and is discharged.

In this embodiment, the fourth semiconductor transistor 124 is a fourth diode, the fourth input portion 124a is connected to the anode of the fourth diode, and the fourth output portion 124b is connected to the cathode of the fourth diode.

In other embodiments, the fourth semiconductor transistor is a third PMOS transistor, the gate of the third PMOS transistor is connected to the device input, the fourth input is connected to the source of the third PMOS transistor, and the fourth output is connected to the drain of the third PMOS transistor; or, the fourth semiconductor transistor is a third PNP triode, the base of the third PNP triode is connected to the device input portion, the fourth input portion is connected to the collector of the third PNP triode, and the fourth output portion is connected to the emitter of the third PNP triode.

In this embodiment, the fifth semiconductor transistor 125 is a fifth diode, the fifth input portion 125a is connected to the anode of the fifth diode, and the fifth output portion 125b is connected to the cathode of the fifth diode.

In other embodiments, the fifth semiconductor transistor is a second NMOS transistor, a gate of the second NMOS transistor is connected to the device output, the fifth input is connected to a source of the second NMOS transistor, and the fifth output is connected to a drain of the second NMOS transistor; or the fifth semiconductor transistor is a second NPN triode, a base of the second NPN triode is connected to the device output part, the fifth input part is connected to an emitter of the second NPN triode, and the fifth output part is connected to a collector of the second NPN triode.

In summary, in the ESD protection circuit according to the embodiment of the present invention, the ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion couples static charge into the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

Further, when the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor are diodes.

Referring to fig. 3, a substrate is provided, the substrate includes a device region a and a protection region B, and the protection region B includes a first protection region, a second protection region, and a third protection region.

The first protection region is subsequently used for forming a first semiconductor transistor, the second protection region is subsequently used for forming a second semiconductor transistor, and the third protection region is subsequently used for forming a third semiconductor transistor.

In this embodiment, the protection zone B further includes a fourth protection zone and a fifth protection zone.

The fourth protection region is used for forming a fourth semiconductor transistor subsequently, and the fifth protection region is used for forming a fifth semiconductor transistor subsequently.

In this embodiment, the substrate includes a base 100 and a fin 101 located on the base 100. In other embodiments, the substrate may also be a planar substrate.

In this embodiment, the substrate 100 and the fin 101 are made of silicon. In other embodiments, the material of the substrate and the fin portion may also be germanium or silicon germanium.

And subsequently forming a first semiconductor transistor in the first protection area of the substrate, wherein the first semiconductor transistor comprises a first input part and a first output part, the first input part is electrically connected with the device output part, the first output part is electrically connected with the device input part, and when the potential of the first output part is higher than that of the first input part and the potential difference between the first output part and the first input part is greater than the threshold turn-on voltage of the first semiconductor transistor, the first semiconductor transistor is turned on.

And forming a second semiconductor transistor in the second protection region of the substrate, wherein the second semiconductor transistor comprises a second input part and a second output part, the second output part is electrically connected with the device input part, the second input part is electrically connected with the connecting part, and when the potential of the second output part is higher than that of the second input part and the potential difference between the second output part and the second input part is greater than the threshold conducting voltage of the second semiconductor transistor, the second semiconductor transistor is conducted.

And forming a third semiconductor transistor in a third protection region of the substrate, wherein the third semiconductor transistor comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with the device output part, and when the third output part potential is higher than the third input part potential and the third output part potential difference and the third input part potential difference are larger than the reverse breakdown voltage of the third semiconductor transistor, the third semiconductor transistor is conducted.

In this embodiment, the first semiconductor transistor is a first diode. The first semiconductor transistor includes: the first P-type doped region is positioned in the first protection region substrate; a first N-type doped region in the first guard region substrate, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region.

The second semiconductor transistor is a second diode. The second semiconductor transistor includes: the second P-type doped region is positioned in the second protection region substrate; a second N-type doped region in the second guard region substrate, the second N-type doped region in contact with the second P-type doped region, the second input portion including the second P-type doped region, and the second output portion including the second N-type doped region.

The third semiconductor transistor is a third diode. The third semiconductor transistor includes: a third P-type doped region in the third guard area substrate; a third N-type doped region in the third guard region substrate, the third N-type doped region in contact with the third P-type doped region, a third input portion comprising the third P-type doped region, and a third output portion comprising the third N-type doped region;

in this embodiment, the functional device includes a MOS transistor.

In this embodiment, the first P-type doped region includes: a first P-type conductive region in the first protective region substrate; a first heavily P-doped region in the first P-type conductivity region.

The second P-type doped region includes: a second P-type conductivity region in the second guard area substrate and a second heavily P-type doped region in the second P-type conductivity region.

The third P-type doped region includes: a third P-type conductivity region in the third guard area substrate and a third heavily P-type doped region in the second P-type conductivity region.

In this embodiment, the step of forming the ESD protection structure further includes: forming a fourth semiconductor transistor in a fourth protection region of the substrate, the fourth semiconductor transistor comprising a fourth input and a fourth output, the fourth output being electrically connected to the device input; and forming a fifth semiconductor transistor in a fifth protection area of the substrate, wherein the fifth semiconductor transistor comprises a fifth input part and a fifth output part, the fifth output part is electrically connected with the fourth input part, and the fifth input part is electrically connected with the device output part.

The fourth semiconductor transistor includes: a fourth P-type doped region in the fourth guard area substrate; a fourth N-type doped region in the fourth guard area substrate, the fourth N-type doped region in contact with the fourth P-type doped region, the fourth input portion including the fourth P-type doped region, and the fourth output portion including the fourth N-type doped region.

The fifth semiconductor transistor includes: a fifth P-type doped region in the fifth guard area substrate; a fifth N-type doped region in the fifth guard area substrate, the fifth N-type doped region being in contact with the fifth P-type doped region, the fifth input portion including the fifth P-type doped region, the fifth output portion including the fifth N-type doped region.

In this embodiment, steps of forming the functional device, the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor are as shown in fig. 4 to 6.

Referring to fig. 4, conducting region ion implantation is performed on the substrate, a device conducting region is formed in the device region a of the substrate, a first P-type conducting region is formed in the first protection region substrate, a second P-type conducting region is formed in the second protection region substrate, and a third P-type conducting region is formed in the third protection region substrate.

The device conductive region, the first P-type conductive region, the second P-type conductive region, and the third P-type conductive region constitute a conductive region 102.

In this embodiment, the ion implantation of the conductive region further forms a fourth P-type conductive region in the fourth protection region substrate, and forms a fifth P-type conductive region in the fifth protection region substrate.

In this embodiment, the implanted ions of the conductive region ion implantation are P-type ions, such as boron ions or BF^2-Ions. In other embodiments, the implanted ions implanted by the conductive region ions may also be N-type ions, such as phosphorous ions or arsenic ions.

In this embodiment, the conductive region 102 is located in the fin 101 and a portion of the substrate 100. In other embodiments, the conductive region may also be located only in the fin.

The forming method further includes: a gate structure (not shown) is formed on the device region a substrate.

In this embodiment, the gate structure crosses over the fin 101 in the device region a, and covers sidewalls and a top surface of the fin 101.

Referring to fig. 5, a mask layer 120 is formed on the first protection region substrate; and performing light doping injection on the substrate by taking the mask layer 120 as a mask to form a light doping area 111 in the device area A substrate.

The lightly doped region 111 is used for forming a concentration gradient between a source region and an MOS transistor channel and between a drain region and the transistor channel formed in the subsequent process, and reducing the electric field intensity between the source region and the MOS transistor channel and between the drain region and the transistor channel.

The lightly doped implantation is used for implanting lightly doped ions in the substrate of the device region A.

In this embodiment, the MOS transistor is an NMOS transistor, and the lightly doped and implanted ions are N-type ions, such as phosphorus ions or arsenic ions. In other embodiments, the MOS transistor may be a PMOS transistor, and the lightly doped ions are P-type ions.

In this embodiment, the mask layer 120 further covers the second protection region, the third protection region, the fourth protection region, and the fifth protection region.

In the light doping injection process, the mask layer 120 covers the first protection region, the second protection region, the third protection region, the fourth protection region and the fifth protection region, so that light doping ions are not injected into the substrates of the first protection region, the second protection region, the third protection region, the fourth protection region and the fifth protection region, the reverse breakdown voltage of the first semiconductor transistor, the second semiconductor transistor, the third semiconductor transistor, the fourth semiconductor transistor and the fifth semiconductor transistor is favorably reduced, and the performance of the formed ESD protection structure is improved.

Referring to fig. 6, after the lightly doped region 111 is formed, a device doped region 112 is formed in the device region a substrate, and a first P-type heavily doped region 121 and a first N-type doped region 122 are formed in the first protection region substrate.

The forming method further includes: forming a second P-type heavily doped region and a second N-type doped region in the second protection region substrate; forming a third P-type heavily doped region and a third N-type doped region in the third protection region substrate; forming a fourth P-type heavily doped region and a fourth N-type doped region in the fourth protection region substrate; and forming a fifth P-type heavily doped region and a fifth N-type doped region in the fifth protective region substrate.

The device doping regions 112 are located in the substrate on both sides of the gate structure.

The process of forming the device doping region 112, the first N-type doping region 122, the second N-type doping region, the third N-heavy doping region, the fourth N-type doping region and the fifth N-type doping region includes an N-type ion implantation process.

The process of forming the first P-type heavily doped region 121, the second P-type heavily doped region, the third P-type heavily doped region, the fourth P-type heavily doped region and the fifth P-type heavily doped region includes a P-type ion implantation process.

In this embodiment, the device doping region 112 is an N-type semiconductor, and the device doping region 112 has N-type doped ions therein. In other embodiments, if the functional device is a PMOS transistor, the device doping region is a P-type semiconductor, and the device doping region has P-type doped ions therein.

In this embodiment, the first semiconductor transistor, the second semiconductor transistor, the third semiconductor transistor, the fourth semiconductor transistor, and the fifth semiconductor transistor are described as an example of a diode.

In other embodiments, the first semiconductor transistor is a first PMOS transistor, the first semiconductor transistor comprising: a first gate on the first protection region substrate, the first gate being electrically connected to the first input; the first input part comprises a first source region, the first output part comprises a first drain region; or, the first semiconductor transistor is a first PNP triode, and the first semiconductor transistor includes: the first base region is located between the first collector region and the first emitter region, the first collector region is adjacent to the first base region, the first base region is adjacent to the first emitter region, the first base region is connected with the first input portion, the first input portion comprises the first collector region, and the first output portion comprises the first emitter region.

The second semiconductor transistor is a second PMOS transistor, the second semiconductor transistor including: a second gate on the second guard area substrate; the second gate is electrically connected with the device input part, the second output part comprises the second drain region, the second input part comprises the second source region, and the conductivity types of the second source region and the second drain region are P type; or, the second semiconductor transistor is a second PNP triode, and the second semiconductor transistor includes: a second collector region in the second guard region substrate; the second base region is located between the second collector region and the second emitter region, the second base region is connected with the second device input portion, the second input portion comprises the second emitter region, the second output portion comprises the second collector region, the second emitter region and the second collector region are of a P type in conductivity type, and the second base region is of an N type in conductivity type.

The third semiconductor transistor is a first NMOS transistor, the third semiconductor transistor comprising: a third gate on the third guard area substrate; the third input part comprises the third source region, the third output part comprises the third drain region, and the conductivity types of the third source region and the third drain region are P type; alternatively, the third semiconductor transistor is a first NPN transistor, and the third semiconductor transistor includes: a third collector region in the third guard region substrate; the third base region is located between the third collector region and the third emitter region, the third base region is connected with the input portion of the third device, the third input portion comprises the third emitter region, the third output portion comprises the third collector region, the third emitter region and the third collector region are of a P type in the conductive type, and the third base region is of an N type in the conductive type.

The fourth semiconductor transistor is a third PMOS transistor, the fourth semiconductor transistor including: a fourth gate on the fourth guard area substrate; the fourth gate is electrically connected with the device input part, the fourth input part comprises the fourth source region, the fourth output part comprises the fourth drain region, and the conductivity types of the fourth source region and the fourth drain region are P type; or, the fourth semiconductor transistor is a third PNP triode, and the fourth semiconductor transistor includes: the fourth collector region, the fourth base region and the fourth emitter region are located in the fourth protection region substrate, the fourth base region is located between the fourth collector region and the fourth emitter region, the fourth base region is connected with the fourth device input portion, the fourth output portion comprises the fourth emitter region, the fourth input portion comprises the fourth collector region, the fourth emitter region and the fourth collector region are of a P-type conductivity type, and the fourth base region is of an N-type conductivity type.

The fifth semiconductor transistor is a second NMOS transistor, and the fifth semiconductor transistor includes: a fifth gate on the fifth guard area substrate; a fifth source region and a fifth drain region located in the substrate on two sides of the fifth gate, the fifth gate being electrically connected to the device output portion, the fifth input portion including the fifth source region, the fifth output portion including the fifth drain region, the fifth source region and the fifth drain region having a P-type conductivity; or, the fifth semiconductor transistor is a second NPN triode, and the fifth semiconductor transistor includes: the fifth base region is located between the fifth collector region and the fifth emitter region, the fifth base region is connected with the device output portion, the fifth input portion comprises the fifth emitter region, the fifth output portion comprises the fifth collector region, the fifth emitter region and the fifth collector region are of a P-type conductivity type, and the fifth base region is of an N-type conductivity type.

In this embodiment, the forming method further includes: forming a first pad connecting the connection part; forming a second pad connecting the fourth input portion.

The ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion couples static charge into the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

In summary, in the method for forming a semiconductor structure according to the embodiment of the present invention, the ESD protection circuit includes a first semiconductor transistor, a second semiconductor transistor, and a third semiconductor transistor, and the connection portion couples static charge into the first semiconductor transistor, the second semiconductor transistor, and the third semiconductor transistor. When the charge amount on the connecting part is larger, the charge on the connecting part can be released through the first semiconductor transistor and the second semiconductor transistor or the first semiconductor transistor and the third semiconductor transistor, so that a path for releasing the charge can be increased, and the performance of the ESD protection circuit is improved.

Further, when the first semiconductor transistor is a diode, a mask layer is formed on the first protection region before ion implantation, so that ions are not easily implanted into the first protection region in the ion implantation process, which is beneficial to reducing the reverse breakdown voltage of the first semiconductor transistor, thereby improving the performance of the formed ESD protection structure.

With continued reference to fig. 6, an embodiment of the present invention further provides an ESD protection structure, including: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises a device area A and a protection area B, and the protection area B comprises a first protection area, a second protection area and a third protection area; a functional device located in the substrate device region A, the functional device including a device output portion, a device input portion, and a connection portion; a first semiconductor transistor located in the first protection region of the substrate, the first semiconductor transistor including a first input portion and a first output portion, the first input portion being electrically connected to the device output portion, the first output portion being electrically connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is greater than a threshold turn-on voltage of the first semiconductor transistor; a second semiconductor transistor located in a second protection region of the substrate, the second semiconductor transistor including a second input portion and a second output portion, the second output portion being electrically connected to the device input portion, the second input portion being electrically connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and the second output portion and second input portion potential difference is greater than a threshold turn-on voltage of the second semiconductor transistor; and the third semiconductor transistor is positioned in a third protection area of the substrate and comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with the device output part, the potential of the third output part is higher than that of the third input part, and when the potential difference between the third output part and the third input part is greater than the threshold conducting voltage of the third semiconductor transistor, the third semiconductor transistor is conducted.

In this embodiment, the first semiconductor transistor is a first diode, and the first semiconductor transistor includes: the first P-type doped region is positioned in the first protection region substrate; a first N-type doped region in the first guard region substrate, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region;

in other embodiments, the first semiconductor transistor is a PMOS transistor, the first semiconductor transistor comprising: a first gate on the first protection region substrate, the first gate being connected to the first input; the first input part comprises a first source region, the first output part is connected with the first drain region; or, the first semiconductor transistor is a first PNP triode, and the first semiconductor transistor includes: the first base region is located between the first collector region and the first emitter region, the first base region is in contact with the first input portion, the first base region is in contact with the first emitter region, the first input portion comprises the first collector region, and the first output portion comprises the first emitter region.

In this embodiment, the substrate further includes a capacitor region and a resistor region, and the semiconductor structure further includes: a resistor in the substrate resistor area, the resistor including a first resistor portion and a second resistor portion, the first resistor portion being electrically connected to the device input portion; and the capacitor is positioned in the substrate capacitor area and comprises a first capacitor part and a second capacitor part, the first capacitor part is electrically connected with the second resistor part, and the second capacitor part is electrically connected with the device output part.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An ESD protection circuit, comprising:

a functional device including a device output portion, a device input portion, and a connection portion;

a first semiconductor transistor including a first input portion and a first output portion, the first input portion being connected to the device output portion, the first output portion being connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is larger than a threshold on voltage of the first semiconductor transistor;

a second semiconductor transistor including a second input portion and a second output portion, the second output portion being connected to the device input portion, the second input portion being connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and a potential difference between the second output portion and the second input portion is larger than a threshold on voltage of the second semiconductor transistor;

a third semiconductor transistor including a third input portion and a third output portion, the third output portion being connected to the connection portion, the third input portion being connected to the device output portion, the third semiconductor transistor being turned on when the third output portion potential is higher than the third input portion potential and a third output portion potential difference from the third input portion potential is larger than a threshold on voltage of the third semiconductor transistor.

2. The ESD protection circuit of claim 1, wherein the first semiconductor transistor is a first PMOS transistor, a source of the first PMOS transistor is connected to the first input, the first output is connected to a drain of the first PMOS transistor, a gate of the first PMOS transistor is connected to the device input, and a threshold turn-on voltage of the first semiconductor transistor is a source-drain voltage when the first PMOS transistor is on;

or, the first semiconductor transistor is a first diode, the first input part is connected with the anode of the first diode, the first output part is connected with the cathode of the first diode, and the threshold turn-on voltage of the first semiconductor transistor is the reverse breakdown voltage of the first diode;

or, the first semiconductor transistor is a first PNP triode, the base of the first PNP triode is connected to the device input portion, the first input portion is connected to the collector of the first PNP triode, the first output portion is connected to the emitter of the first PNP triode, and the threshold turn-on voltage of the first semiconductor transistor is the turn-on voltage of the first PNP triode.

3. The ESD protection circuit of claim 1, wherein the second semiconductor transistor is a second PMOS transistor, a gate of the second PMOS transistor is connected to the device input, the second input is connected to a source of the second PMOS transistor, the second output is connected to a drain of the second PMOS transistor, and a threshold turn-on voltage of the second semiconductor transistor is a source-drain voltage when the second PMOS transistor is turned on;

or the second semiconductor transistor is a second diode, the second input part is connected with the anode of the second diode, the second output part is connected with the cathode of the second diode, and the threshold on-voltage of the second semiconductor transistor is the reverse breakdown voltage of the second diode;

or, the second semiconductor transistor is a second PNP triode, the base of the second PNP triode is connected to the device input portion, the second input portion is connected to the collector of the second PNP triode, the second output portion is connected to the emitter of the second PNP triode, and the threshold turn-on voltage of the second semiconductor transistor is the turn-on voltage of the second PNP triode.

4. The ESD protection circuit of claim 1, wherein the third semiconductor transistor is a first NMOS transistor, a gate of the first NMOS transistor is connected to the device output, the third input is connected to a source of the first NMOS transistor, the third output is connected to a drain of the first NMOS transistor, and a threshold turn-on voltage of the third semiconductor transistor is a source-drain voltage when the first NMOS transistor is turned on;

or the third semiconductor transistor is a third diode, the third input part is connected with the anode of the third diode, the third output part is connected with the cathode of the third diode, and the threshold on-voltage of the third semiconductor transistor is the reverse breakdown voltage of the third diode;

or the third semiconductor transistor is a first NPN triode, a base of the first NPN triode is connected to the device output part, the third input part is connected to an emitter of the first NPN triode, the third output part is connected to a collector of the first NPN triode, and a threshold turn-on voltage of the third semiconductor transistor is a turn-on voltage of the first NPN triode.

5. The ESD protection circuit of claim 1, further comprising: a fourth semiconductor transistor including a fourth input and a fourth output, the fourth output being connected to the device input, the fourth semiconductor transistor being turned on when the fourth output potential is higher than the fourth input potential and a fourth output potential is different from the fourth input potential by more than a threshold turn-on voltage of the fourth semiconductor transistor; a fifth semiconductor transistor including a fifth input and a fifth output, the fifth output being connected to the fourth input, the fifth input being connected to a device output, the fifth semiconductor transistor being turned on when the fifth output potential is higher than the fifth input potential and a fifth output potential is greater than a fifth input potential by a threshold turn-on voltage of the fifth semiconductor transistor.

6. The ESD protection circuit of claim 5, wherein the fourth semiconductor transistor is a third PMOS transistor, a gate of the third PMOS transistor is connected to the device input, the fourth input is connected to a source of the third PMOS transistor, the fourth output is connected to a drain of the third PMOS transistor, and a threshold turn-on voltage of the fourth semiconductor transistor is a source-drain voltage when the third PMOS transistor is on;

or, the fourth semiconductor transistor is a fourth diode, the fourth input part is connected to the anode of the fourth diode, the fourth output part is connected to the cathode of the fourth diode, and the threshold turn-on voltage of the fourth semiconductor transistor is the reverse breakdown voltage of the fourth diode;

or, the fourth semiconductor transistor is a third PNP triode, the base of the third PNP triode is connected to the device input portion, the fourth input portion is connected to the collector of the third PNP triode, the fourth output portion is connected to the emitter of the third PNP triode, and the threshold turn-on voltage of the fourth semiconductor transistor is the turn-on voltage of the third PNP triode.

7. The ESD protection circuit of claim 5, wherein the fifth semiconductor transistor is a second NMOS transistor, a gate of the second NMOS transistor is connected to the device output, the fifth input is connected to a source of the second NMOS transistor, the fifth output is connected to a drain of the second NMOS transistor, and a threshold turn-on voltage of the fifth semiconductor transistor is a source-drain voltage when the second NMOS transistor is turned on;

or the fifth semiconductor transistor is a fifth diode, the fifth input part is connected with the anode of the fifth diode, the fifth output part is connected with the cathode of the fifth diode, and the threshold turn-on voltage of the fifth semiconductor transistor is the reverse breakdown voltage of the fifth diode;

or the fifth semiconductor transistor is a second NPN triode, a base of the second NPN triode is connected to the device output part, the fifth input part is connected to an emitter of the second NPN triode, the fifth output part is connected to a collector of the second NPN triode, and the threshold turn-on voltage of the first semiconductor transistor is the turn-on voltage of the second NPN triode.

8. The ESD protection circuit of claim 1, further comprising a clamp circuit comprising a clamp input and a clamp output, the clamp input connected to the device input and the clamp output connected to the device output.

9. The ESD protection circuit of claim 8, wherein the clamp circuit comprises: the capacitor comprises a first capacitor end and a second capacitor end, the resistor comprises a first resistor end and a second resistor end, the second resistor end is connected with the first capacitor end, the clamping input end is connected with the first resistor end, and the clamping output end is connected with the second capacitor end.

10. The ESD protection circuit of claim 1, wherein the device output is for ground.

11. A method for forming an ESD protection structure, comprising:

providing a substrate, wherein the substrate comprises a device region, a first protection region, a second protection region and a third protection region;

forming a functional device in the device region, the functional device including a device output portion, a device input portion, and a connection portion;

forming a first semiconductor transistor in the first protection region, the first semiconductor transistor including a first input portion and a first output portion, the first input portion being electrically connected to the device output portion, the first output portion being electrically connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is greater than a threshold turn-on voltage of the first semiconductor transistor;

forming a second semiconductor transistor in the second protection region, wherein the second semiconductor transistor comprises a second input part and a second output part, the second output part is electrically connected with the device input part, the second input part is electrically connected with the connecting part, and when the second output part is higher than the second input part in potential and the second output part and the second input part are higher in potential difference than the threshold conducting voltage of the second semiconductor transistor, the second semiconductor transistor is conducted;

and forming a third semiconductor transistor in the third protection region, wherein the third semiconductor transistor comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with a device output part, the third output part is higher in potential than the third input part, and the third semiconductor transistor is conducted when the potential difference between the third output part and the third input part is larger than the threshold conducting voltage of the third semiconductor transistor.

12. The method of claim 11, wherein the first semiconductor transistor is a first diode, the first semiconductor transistor comprising: the first P-type doped region is positioned in the first protection region; a first N-type doped region in the first protection region, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region;

the second semiconductor transistor is a second diode, the second semiconductor transistor including: the second P-type doped region is positioned in the second protection region; a second N-type doped region in the second protection region, the second N-type doped region being in contact with the second P-type doped region, the second input portion including the second P-type doped region, the second output portion including the second N-type doped region; the third semiconductor transistor is a third diode, the third semiconductor transistor including: a third P-type doped region in the third protection region; a third N-type doped region in the third protection region, the third N-type doped region being in contact with the third P-type doped region, a third input portion including the third P-type doped region, and a third output portion including the third N-type doped region.

13. The method of claim 12, wherein the substrate comprises a base and a fin on the base;

the functional device includes a device conductive region located in the device region; a lightly doped region in the device conductive region, and a device doped region in the lightly doped region and the device conductive region;

the first P-type doped region includes: a first P-type conductivity region in the first protection region; a first P-type heavily doped region in the first P-type conductive region;

the step of forming the functional device and the first semiconductor transistor includes: forming a device conductive region in the device region; forming a first P-type conductive region in the first protection region; forming a mask layer on the first protection area; performing light doping injection on the substrate by taking the mask layer as a mask to form a light doping area in the device area; and forming a device doping area in the device area lightly doped area and the device conductive area, and forming a first P-type heavily doped area and a first N-type doping area in the first P-type conductive area.

14. The method of claim 13, wherein the mask layer further covers the second protection region and the third protection region.

15. The method of forming an ESD protection structure of claim 11, wherein the substrate further comprises a fourth protection region and a fifth protection region;

further comprising: forming a fourth semiconductor transistor in the fourth protection region, wherein the fourth semiconductor transistor comprises a fourth input portion and a fourth output portion, the fourth output portion is electrically connected with the device input portion, and when the fourth output portion is higher in potential than the fourth input portion and the potential difference between the fourth output portion and the fourth input portion is larger than the threshold on voltage of the fourth semiconductor transistor, the fourth semiconductor transistor is turned on;

and forming a fifth semiconductor transistor in the fifth protection region, wherein the fifth semiconductor transistor comprises a fifth input part and a fifth output part, the fifth output part is electrically connected with the fourth input part, the fifth input part is electrically connected with a device output part, and when the potential of the fifth output part is higher than that of the fifth input part and the potential difference between the fifth output part and the fifth input part is greater than the threshold turn-on voltage of the fifth semiconductor transistor, the fifth semiconductor transistor is turned on.

16. The method of forming an ESD protection structure of claim 15, wherein the fourth semiconductor transistor is a fourth diode, the fourth semiconductor transistor comprising: a fourth P-type doped region in the fourth protection region; a fourth N-type doped region in the fourth protection region, the fourth N-type doped region in contact with the fourth P-type doped region, the fourth input portion comprising the fourth P-type doped region, the fourth output portion comprising the fourth N-type doped region;

the fifth semiconductor transistor is a fifth diode, the fifth semiconductor transistor including: a fifth P-type doped region in the fifth guard region; a fifth N-type doped region in the fifth guard region, the fifth N-type doped region in contact with the fifth P-type doped region, the fifth input portion including the fifth P-type doped region, and the fifth output portion including the fifth N-type doped region.

17. The method of forming an ESD protection structure of claim 11, wherein the device output is for ground.

18. An ESD protection structure, comprising:

a substrate including a device region, a first protection region, a second protection region, and a third protection region;

a functional device located in the device region, the functional device including a device output, a device input, and a connection;

a first semiconductor transistor located in the first protection region, the first semiconductor transistor including a first input portion and a first output portion, the first input portion being electrically connected to the device output portion, the first output portion being electrically connected to the device input portion, the first semiconductor transistor being turned on when the first output portion potential is higher than the first input portion potential and a potential difference between the first output portion and the first input portion is greater than a threshold turn-on voltage of the first semiconductor transistor;

a second semiconductor transistor located in the second protection region, the second semiconductor transistor including a second input portion and a second output portion, the second output portion being electrically connected to the device input portion, the second input portion being electrically connected to the connection portion, the second semiconductor transistor being turned on when the second output portion potential is higher than the second input portion potential and the second output portion and the second input portion potential difference is greater than a threshold turn-on voltage of the second semiconductor transistor;

and the third semiconductor transistor is positioned in the third protection region and comprises a third input part and a third output part, the third output part is electrically connected with the connecting part, the third input part is electrically connected with the device output part, the third output part is higher in potential than the third input part, and when the potential difference between the third output part and the third input part is greater than the threshold conducting voltage of the third semiconductor transistor, the third semiconductor transistor is conducted.

19. The ESD protection structure of claim 18, wherein the first semiconductor transistor is a first diode, the first semiconductor transistor comprising: the first P-type doped region is positioned in the first protection region; a first N-type doped region in the first protection region, the first N-type doped region in contact with the first P-type doped region, the first input portion including the first P-type doped region, the first output portion including the first N-type doped region;

alternatively, the first semiconductor transistor is a PMOS transistor, and the first semiconductor transistor includes: a first gate on the first protection region, the first gate being connected to the first input; the first input part comprises a first source region, the first output part is connected with the first drain region;

or, the first semiconductor transistor is a first PNP triode, and the first semiconductor transistor includes: the first base region is located between the first collector region and the first emitter region, the first base region is in contact with the first input portion, the first base region is in contact with the first emitter region, the first input portion comprises the first collector region, and the first output portion comprises the first emitter region.

20. The ESD protection structure of claim 18, wherein the substrate further comprises a capacitive region and a resistive region, the semiconductor structure further comprising: a resistor in the substrate resistor area, the resistor including a first resistor portion and a second resistor portion, the first resistor portion being electrically connected to the device input portion; and the capacitor is positioned in the substrate capacitor area and comprises a first capacitor part and a second capacitor part, the first capacitor part is electrically connected with the second resistor part, and the second capacitor part is electrically connected with the device output part.