CN108695250A - 半导体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 107
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 34
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Abstract
本发明提供半导体装置,其具有熔断元件,该熔断元件配置于半导体衬底上形成的层间绝缘膜上,所述熔断元件由多晶硅和设置在所述多晶硅的上表面的硅化物形成,俯视观察时,所述多晶硅的被包含在激光照射的范围内的区域为未导入杂质的非掺杂多晶硅,从而成为具有不对基底带来损伤而能够利用激光稳定地切断的熔断元件的半导体装置。
Description
技术领域
本发明涉及半导体装置。特别是涉及具有能够通过切断而变更电路结构的熔断元件的半导体装置。
背景技术
在半导体装置的制造工序中,有下述方法:在晶片制造工序结束之后,例如使用激光将例如采用了多晶硅或金属的熔断元件切断而进行电路结构的变更。通过使用该方法,在对半导体装置的电特性进行测定之后,通过修正电阻的值,能够得到期望的特性,在重视模拟特性的半导体装置中是特别有效的方法。
在该方法中,要求熔断元件能够在激光下稳定地切断。
在专利文献1中,提出了下述方法:通过使熔断元件的激光照射部的形状为圆形,能够将激光能量高效地用于熔断,由此稳定地将熔断元件切断。
专利文献1:日本特开2000-30587号公报
首先,对通常使用的以往的熔断元件的剖面构造进行说明。图7是示出熔断元件的剖面构造的示意图,是熔断元件的与在熔断元件中流动的电流成垂直方向的宽度方向的剖视图。在硅衬底等半导体衬底11上配置有第1层间绝缘膜21,在第1层间绝缘膜21上形成有多晶硅12。多晶硅12是熔断元件。按照覆盖该多晶硅12的方式形成有第2层间绝缘膜22。在第2层间绝缘膜22上形成有最终保护膜23。最终保护膜23具有保护膜开口区域32,在形成有熔断元件的区域的上部开口。从上方覆盖作为熔断元件的多晶硅12的仅为第2层间绝缘膜22。激光光斑区域31是用于切断熔断元件的激光所照射的区域,该激光光斑区域31在熔断元件的宽度方向上完全覆盖构成熔断元件的多晶硅12的要被切断的区域。
接着,关于熔断元件基于激光的切断,对切断的原理进行说明。当对熔断元件照射激光时,被激光照射的熔断元件吸收热而发生熔融气化。由此,由于体积膨胀的熔断元件,配设在熔断元件上部的第2层间绝缘膜22被熔断元件内部的压力吹飞。此时,在多晶硅12的内部压力升高时,受到压力的除了多晶硅12的上方之外,也对侧面以及底面的第1层间绝缘膜21施加压力。一旦上方敞开,熔断元件的多晶硅12发生气化并向外扩散,从而成为被切断的状态。
这样,作为通过激光进行切断的熔断元件的物理特性之一,可以举出对熔断元件周边的损伤的影响。由于利用激光对熔断元件施加热而导致的体积膨胀,物理地将膜破坏,因此该影响有可能给与作为熔断元件的多晶硅12的底面相接的第1层间绝缘膜21带来损伤,产生裂纹。当在第1层间膜21上产生裂纹时,气化的多晶硅12进入并附着,从而也有熔断元件与半导体衬底11电短路的情况。
为了不产生这样的裂纹,考虑了减薄熔断元件上部的层间绝缘膜、或者降低激光的能量等对策,但对熔断元件上部的层间绝缘膜的膜厚进行控制在制造工序中难度较高,有可能成为工序上的负担。另外,若降低激光的能量,则由于能量不足而导致多晶硅12的气化不完全,从而导致熔断元件的切割残留。
如上所述,在采用了多晶硅的激光熔断型的熔断元件中,对熔断元件周边的损伤和熔断元件切割残留的风险存在权衡的关系。特别是在专利文献1记载的激光照射部成为圆形的形状的情况下,在按照剖面进行考虑时,垂直方向的压力变高,因此熔断元件的上方的层间绝缘膜容易被吹飞。同时,对熔断元件的下方的层间绝缘膜的压力也变高,因此成为容易产生裂纹的状况。
发明内容
本发明是鉴于上述状况而完成的,其课题在于提供半导体装置,其具有切割残留的风险小、在利用激光的切断时不易产生对熔断元件周边的损伤的熔断元件。
本发明为了实现上述课题,采用下述结构。
即,提供半导体装置,其特征在于,该半导体装置具有:
半导体衬底;以及
熔断元件,其配置于所述半导体衬底上形成的层间绝缘膜上,
所述熔断元件由多晶硅和设置在所述多晶硅的上表面的硅化物形成,俯视观察时,所述多晶硅的被包含在激光照射的范围内的区域为未导入杂质的非掺杂多晶硅。
根据本发明,熔断元件的被激光照射的区域由上表面被硅化物化的未导入杂质的非掺杂多晶硅构成,而且能够使所照射的激光的波长为长波长,因此成为由于多晶硅部分为非掺杂而不吸收激光,仅被硅化物化的上表面部分容易吸收激光的构造。由此,在激光照射时仅对被硅化物化的上表面部分进行加热并切断。另外,非掺杂的多晶硅部分起到保护的作用,从而能够提供不对基底产生损伤而能够切断的熔断元件。
附图说明
图1是示出本发明中的半导体装置的俯视图。
图2是示出本发明中的半导体装置的剖视图。
图3是示出本发明中的半导体装置的剖视图。
图4是示出本发明中的半导体装置的俯视图。
图5是示出本发明中的半导体装置的剖视图。
图6是示出本发明中的半导体装置的剖视图。
图7是示出以往的半导体装置的剖视图。
标号说明
11:半导体衬底;12:多晶硅;13:掺杂多晶硅;14:非掺杂多晶硅;15:硅化物;21:第1层间绝缘膜;22:第2层间绝缘膜;23:最终保护膜;31:激光光斑区域;32:保护膜开口区域;41:熔断元件。
具体实施方式
以下,参照附图对本发明的实施方式进行说明。
图1是本发明的第1实施方式中的半导体装置的俯视图。该半导体装置配置有熔断元件41,并且覆盖熔断元件41的一部分的区域而配置有保护膜开口区域32。熔断元件41存在两个区域。图1所示的(A)区域成为激光照射的区域,(B)区域成为激光不照射的区域。在图1中,熔断元件41俯视观察时的形状为哑铃型。但是,并不限于哑铃型。
图2是示出沿图1所示的单点划线a-a’的剖面的图。使用图2对剖面构造进行详细说明。首先,在半导体衬底11上形成有第1层间绝缘膜21。在第1层间绝缘膜21上形成有作为熔断元件的层。作为该熔断元件的层由三个区域形成。该三个区域为俯视时比激光光斑区域31大的由非掺杂多晶硅14形成的区域以及与其两端相邻地配置的掺杂多晶硅13的区域。掺杂多晶硅13和非掺杂多晶硅14由多晶硅12形成。掺杂多晶硅13例如是采用离子注入法等对非掺杂多晶硅导入杂质而具有导电性的多晶硅。有时会通过杂质的离子注入使得掺杂多晶硅13的上表面非晶化,不过,在后续的硅化物形成中使多晶硅非晶化会实现更低的电阻化,从这样的方面等考虑,可以姑且保持非晶硅的状态。
另外,在掺杂多晶硅13和非掺杂多晶硅14这两者的上表面形成有硅化物15。在如上述那样构成的熔断元件的上部形成并配置有第2层间绝缘膜22,进一步在第2层间绝缘膜22上的一部分区域形成有最终保护膜23。
如图2所示,最终保护膜23设置有保护膜开口区域32,在包含激光光斑区域31在内的熔断元件的上部开口。另外,第2层间绝缘膜22的形成有保护膜开口区域32的区域的膜厚比除了保护膜开口区域32以外的第2层间绝缘膜22薄。这是因为,如在切断的原理中所说明的那样,为了使基于激光的熔断切断容易,需要减薄一定程度,以便成为适合激光切断的厚度。并且,最终保护膜23开口的原因是为了避免最终保护膜23对激光的吸收,不阻碍激光对熔断元件的照射。
接着,对基于激光的切断进行说明。当对图2所示的激光光斑区域31照射激光时,吸收了激光能量的硅化物15发生熔融气化。此时,作为激光的波长,当选择不太被硅吸收而容易被作为金属与硅的化合物的硅化物吸收的波长时,更有效。例如,可以为1.3μm的波长。从长波长还能够抑制在硅衬底等半导体衬底11上产生热的方面出发,成为对损伤的抑制有效的手段。
另外,在熔断元件上被激光照射的区域为非掺杂多晶硅14上的硅化物。这是因为,在激光照射的区域存在掺杂多晶硅13的情况下,掺杂多晶硅13显示出接近金属的激光吸收特性,因此会导致本实施方式与以往方法相同,由于掺杂多晶硅13的熔融气化而产生的基底损伤会成为问题。由此,考虑到制造上的加工偏差、激光的对准精度等,激光光斑区域31与掺杂多晶硅13的区域之间需要以充分的余量来进行设计,以使得两者不重叠。俯视时非掺杂多晶硅14的区域在图1中完全包含激光照射的区域(A),非掺杂多晶硅14与掺杂多晶硅13的边界位于激光不照射的区域(B)。
在本实施方式中,特征之一在于使硅化物15有效地吸收激光能量、使非掺杂多晶硅14不吸收激光能量。基于激光的切断通过硅化物15的熔融气化来进行,非掺杂多晶硅14作为用于缓和对基底的第1层间绝缘膜21的损伤的保护层发挥功能。
图3是示出利用激光将熔断元件切断后的情况的与图2对应的剖视图。如图3所示,激光照射后,硅化物15发生熔融气化,从而成为上部的第2层间绝缘膜22被去除的状态。非掺杂多晶硅14的一部分也由于硅化物15的热而发生熔融气化。在本发明中,非掺杂多晶硅14作为保护层发挥功能,因此实现了对损伤的抑制,从而能够进行激光的高能量化。另外,从基底保护的观点出发,非掺杂多晶硅14的膜厚需要设定得比硅化物15厚。由此,能够利用高能量化降低熔断元件的切割残留的风险。
在图3的状态下,硅化物15被切断,非掺杂多晶硅14的一部分连接但未导入导电性杂质,因此没有电流流过,熔断元件成为等同于被切断的状态。
在本实施方式中,熔断元件的被激光照射的区域为上表面被硅化物化的未导入杂质的非掺杂多晶硅,从而成为由于多晶硅部分为非掺杂而不吸收激光,仅被硅化物化的上表面部分容易吸收激光的构造。由此,成为在激光照射时仅对被硅化物化的上表面部分进行加热并切断的构造,从而非掺杂的多晶硅部分起到保护的作用,能够提供不对基底产生损伤而能够切断的熔断元件。使所照射的激光的波长为长波长,从而能够进一步增大效果。
接着,对本发明的第2实施方式进行说明。
图4是示出本发明的第2实施方式中的半导体装置的俯视图。该半导体装置配置有熔断元件41,并且覆盖熔断元件41的一部分的区域而配置有保护膜开口区域32。熔断元件41存在两个区域。图4所示的(A)区域成为激光照射的区域,(B)成为激光不照射的区域。另外,熔断元件41俯视时由硅化物15和不为硅化物的两个区域构成。在该熔断元件中,激光照射的区域(A)中的不是硅化物15的区域成为非掺杂多晶硅14。在图4中,俯视观察时硅化物15的区域为哑铃型的形状,俯视观察时熔断元件41的形状为长方形。但是,硅化物15和熔断元件41的平面形状分别不限于哑铃型和长方形。
图5是示出沿图4所示的单点划线b-b’的剖面的图。参照图5,对剖面构造进行详细说明。在半导体衬底11上形成有第1层间绝缘膜21。在第1层间绝缘膜21上形成有作为熔断元件的层。作为该熔断元件的层由三个区域形成。该三个区域为俯视时比激光光斑区域31大的由非掺杂多晶硅14形成的区域以及配置在其两端的掺杂多晶硅13的区域。掺杂多晶硅13和非掺杂多晶硅14由多晶硅12形成。掺杂多晶硅13例如是采用离子注入法等对非掺杂多晶硅导入杂质而具有导电性的多晶硅。掺杂多晶硅13的上表面有时由于杂质的离子注入而非晶化,但从在硅化物形成中使多晶硅非晶化会更低电阻化等的观点出发,可以保持非晶硅的状态。
另外,在掺杂多晶硅13和非掺杂多晶硅14这两者的上表面形成有硅化物15。在由它们构成的熔断元件的上部配置有第2层间绝缘膜22,在第2层间绝缘膜22的一部分的区域上进一步形成有最终保护膜23。
如图5所示,最终保护膜23设置有保护膜开口区域32,在包含激光光斑区域31在内的熔断元件上部开口。另外,第2层间绝缘膜22的形成有保护膜开口区域32的区域的膜厚比除了保护膜开口区域32以外的第2层间绝缘膜22薄。这是因为,如在切断的原理中所说明的那样,为了使基于激光的熔断切断容易,需要减薄一定程度。并且,最终保护膜23开口的原因是为了避免最终保护膜23对激光的吸收,不阻碍激光对熔断元件的照射。
图6是示出沿图4所示的单点划线c-c’的剖面的图。参照图6,对剖面构造的详细情况进行说明。在本实施例中,熔断元件的被激光照射的区域如上述那样由硅化物15和非掺杂多晶硅14形成。如图6所示,硅化物15形成在包含非掺杂多晶硅14的中心在内的一部分的区域。该硅化物15成为被激光切断的部分。
在熔断元件上被激光照射的区域为非掺杂多晶硅14上的硅化物。这是因为,在激光照射的区域存在掺杂多晶硅13的情况下,掺杂多晶硅13显示出接近金属的激光吸收特性,因此会导致与以往方法相同,由于掺杂多晶硅13的熔融气化而产生的基底损伤会成为问题。由此,考虑到制造上的加工偏差、激光的对准精度等,激光光斑区域31与掺杂多晶硅13的区域之间需要以充分的余量进行设计,以使得两者不重叠。俯视时非掺杂多晶硅14的区域在图4中完全包含激光照射的区域(A),非掺杂多晶硅14与掺杂多晶硅13的边界位于激光不照射的区域(B)。
关于基于激光的切断,与第1实施方式相同。
在本实施方式中,特征之一在于使硅化物15有效地吸收激光能量、使非掺杂多晶硅14不吸收激光能量。通过该结构,基于激光的切断通过硅化物15的熔融气化来进行,非掺杂多晶硅14作为用于缓和对基底的第1层间绝缘膜21的损伤的保护层发挥功能。激光照射后,硅化物15发生熔融气化,从而成为硅化物15的上部的第2层间绝缘膜22被去除的状态。
非掺杂多晶硅14也由于硅化物15的热而一部分发生熔融气化,但在本实施方式中,非掺杂多晶硅14作为保护层发挥功能,因此实现了损伤的抑制,从而能够进行激光的高能量化。从基底保护的观点出发,非掺杂多晶硅14的膜厚需要设定得比硅化物15厚。
在第2实施方式中,如图6所示那样作为保护层的非掺杂多晶硅14比硅化物15大,因此俯视观察时成为针对基底的损伤的保护性更高的构造。因此,能够利用高能量化降低熔断元件的切割残留的风险。
被激光照射的区域的硅化物15由于熔融气化而被切断。一部分非掺杂多晶硅14连接但在非掺杂多晶硅14中未导入导电性杂质,因此熔断元件成为被切断的状态。
如以上说明那样,通过使熔断元件的被激光照射的区域为上表面被硅化物化的未导入杂质的非掺杂多晶硅,并且使所照射的激光为长波长,从而成为由于多晶硅部分为非掺杂而不吸收激光,仅被硅化物化的上表面部分容易吸收激光的构造。由此,成为在激光照射时仅对被硅化物化的上表面部分进行加热并切断的构造,从而非掺杂的多晶硅部分起到保护的作用,能够提供不对基底产生损伤而能够切断的熔断元件。
Claims (9)
1.一种半导体装置,其特征在于,该半导体装置具有:
半导体衬底;以及
熔断元件,其配置于所述半导体衬底上形成的层间绝缘膜上,
所述熔断元件由多晶硅和设置在所述多晶硅的上表面的硅化物形成,俯视观察时,所述多晶硅的被包含在激光照射的范围内的区域为未导入杂质的非掺杂多晶硅。
2.根据权利要求1所述的半导体装置,其特征在于,
对于形成所述熔断元件的所述多晶硅,与所述非掺杂多晶硅的区域相邻地具有导入了杂质的掺杂多晶硅的区域。
3.根据权利要求1所述的半导体装置,其特征在于,
所述激光将所述硅化物切断。
4.根据权利要求1所述的半导体装置,其特征在于,
俯视观察时,在所述激光照射的范围内,所述非掺杂多晶硅的区域比所述硅化物的区域大。
5.根据权利要求1所述的半导体装置,其特征在于,
所述非掺杂多晶硅的区域的膜厚比所述硅化物厚。
6.根据权利要求2所述的半导体装置,其特征在于,
所述激光将所述硅化物切断。
7.根据权利要求2所述的半导体装置,其特征在于,
俯视观察时,在所述激光照射的范围内,所述非掺杂多晶硅的区域比所述硅化物的区域大。
8.根据权利要求2所述的半导体装置,其特征在于,
所述非掺杂多晶硅的区域的膜厚比所述硅化物厚。
9.一种半导体装置,其特征在于,该半导体装置具有:
半导体衬底;以及
熔断元件,其配置于所述半导体衬底上形成的层间绝缘膜上,
所述熔断元件包含:
非掺杂多晶硅的区域,在该非掺杂多晶硅中未导入杂质;
掺杂多晶硅的区域,该掺杂多晶硅的区域设置在所述非掺杂多晶硅的区域的两端;以及
硅化物,其设置在所述非掺杂多晶硅的区域以及在所述两端设置的掺杂多晶硅的区域的上表面,
通过激光的照射,将设置于所述非掺杂多晶硅的区域的上表面的硅化物切断。
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Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154532A (ja) * | 1987-12-11 | 1989-06-16 | Nec Corp | 半導体装置 |
JPH05235170A (ja) * | 1992-02-24 | 1993-09-10 | Nec Corp | 半導体装置 |
JP2000353748A (ja) * | 1999-04-06 | 2000-12-19 | Sony Corp | 半導体装置の製造方法 |
US20070222027A1 (en) * | 2006-03-27 | 2007-09-27 | Yang Jeong-Hwan | Electronic fuse elements with constricted neck regions that support reliable fuse blowing |
CN101170099A (zh) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | 多晶硅硅化物电熔丝器件 |
US20080185678A1 (en) * | 2007-02-07 | 2008-08-07 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
CN101681879A (zh) * | 2007-05-09 | 2010-03-24 | 飞思卡尔半导体公司 | 操作存储器电路的电子装置和方法 |
JP2012129403A (ja) * | 2010-12-16 | 2012-07-05 | Panasonic Corp | 半導体装置及びその製造方法 |
JP2013140871A (ja) * | 2012-01-05 | 2013-07-18 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
US20140131764A1 (en) * | 2011-11-15 | 2014-05-15 | Shine C. Chung | Structures and techniques for using semiconductor body to construct scr, diac, or triac |
US20150221594A1 (en) * | 2014-01-31 | 2015-08-06 | Seiko Instruments Inc. | Semiconductor device |
US20160260668A1 (en) * | 2015-03-06 | 2016-09-08 | Sii Semiconductor Corporation | Semiconductor integrated circuit device and method of manufacturing the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708291A (en) * | 1995-09-29 | 1998-01-13 | Intel Corporation | Silicide agglomeration fuse device |
US5949323A (en) | 1998-06-30 | 1999-09-07 | Clear Logic, Inc. | Non-uniform width configurable fuse structure |
US6225652B1 (en) * | 1999-08-02 | 2001-05-01 | Clear Logic, Inc. | Vertical laser fuse structure allowing increased packing density |
JP3485110B2 (ja) * | 2001-07-25 | 2004-01-13 | セイコーエプソン株式会社 | 半導体装置 |
US7211843B2 (en) * | 2002-04-04 | 2007-05-01 | Broadcom Corporation | System and method for programming a memory cell |
US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
JP4127678B2 (ja) * | 2004-02-27 | 2008-07-30 | 株式会社東芝 | 半導体装置及びそのプログラミング方法 |
JP2015185583A (ja) * | 2014-03-20 | 2015-10-22 | 旭化成エレクトロニクス株式会社 | フューズ素子の製造方法及び半導体装置の製造方法、チタンシリサイド膜の製造方法 |
JP2018170455A (ja) * | 2017-03-30 | 2018-11-01 | エイブリック株式会社 | 半導体装置 |
-
2017
- 2017-03-30 JP JP2017068170A patent/JP2018170455A/ja active Pending
-
2018
- 2018-03-27 US US15/937,200 patent/US10615120B2/en not_active Expired - Fee Related
- 2018-03-29 KR KR1020180036524A patent/KR20180111644A/ko unknown
- 2018-03-29 TW TW107110825A patent/TW201904008A/zh unknown
- 2018-03-30 CN CN201810297141.2A patent/CN108695250A/zh not_active Withdrawn
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154532A (ja) * | 1987-12-11 | 1989-06-16 | Nec Corp | 半導体装置 |
JPH05235170A (ja) * | 1992-02-24 | 1993-09-10 | Nec Corp | 半導体装置 |
JP2000353748A (ja) * | 1999-04-06 | 2000-12-19 | Sony Corp | 半導体装置の製造方法 |
US20070222027A1 (en) * | 2006-03-27 | 2007-09-27 | Yang Jeong-Hwan | Electronic fuse elements with constricted neck regions that support reliable fuse blowing |
US20080185678A1 (en) * | 2007-02-07 | 2008-08-07 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
CN101681879A (zh) * | 2007-05-09 | 2010-03-24 | 飞思卡尔半导体公司 | 操作存储器电路的电子装置和方法 |
CN101170099A (zh) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | 多晶硅硅化物电熔丝器件 |
JP2012129403A (ja) * | 2010-12-16 | 2012-07-05 | Panasonic Corp | 半導体装置及びその製造方法 |
US20140131764A1 (en) * | 2011-11-15 | 2014-05-15 | Shine C. Chung | Structures and techniques for using semiconductor body to construct scr, diac, or triac |
JP2013140871A (ja) * | 2012-01-05 | 2013-07-18 | Asahi Kasei Electronics Co Ltd | 半導体装置の製造方法 |
US20150221594A1 (en) * | 2014-01-31 | 2015-08-06 | Seiko Instruments Inc. | Semiconductor device |
US20160260668A1 (en) * | 2015-03-06 | 2016-09-08 | Sii Semiconductor Corporation | Semiconductor integrated circuit device and method of manufacturing the same |
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US10615120B2 (en) | 2020-04-07 |
KR20180111644A (ko) | 2018-10-11 |
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