TW531836B - An integrated circuit having a passive device integrally formed therein - Google Patents

Abstract

The invented method and device provide a reliable contact to a passive device of a semiconductor circuit device, the passive device being, for example, a resistor, an inductor, a fuse or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under the portions of the passive device on which the contact hole is formed. The shoulder region is formed of the same material as the first conductive layer of the gate of the peripheral transistor. The electrode may be formed through the contact hole to be a reliable contact to the integrated passive device.

Description

531836 V. Description of the invention α), the scope of the invention The present invention relates to an integrated circuit device having a passive device, and more particularly to an integrated circuit (ic) having a passive device integrated therein. BACKGROUND OF THE INVENTION Generally, a non-volatile memory device includes a memory cell transistor having a stacked gate, a source, and a drain, and a peripheral circuit transistor having a single-layer gate, a source, and a drain. To drive the memory cell transistor in the peripheral circuit area. The stacked gate of the memory cell transistor includes a floating gate capable of storing data, a control gate capable of controlling the floating gate, and an intermediate dielectric layer formed therebetween. The single-layer gate is formed by a single-stage conductive layer. However, in recent years, peripheral circuit transistors in the peripheral circuit area also have stacked gate structures and memory cell transistors. For example, disclosed in the VLS I Technical Seminar Technical Report% Digest, 1998, pp. 102, 103, titled "Low-cost high-reliability 10-if-bit flash memory self-aligning ST I process integration. " According to this prior art teaching, the first part of the peripheral circuit transistor gate and the memory cell transistor floating gate are made of the first conductive layer; and the second part of the peripheral circuit transistor gate and the memory cell transistor The control gate is formed by a second conductive layer. The first part and the second part of the transistor gate of the peripheral circuit are connected to each other via a boundary contact. Non-volatile memory devices use passive devices, such as fuses, to repair faulty memory cells. The fuse is only formed by the second conductive layer. It does not affect the first conductive layer below it to prevent the fuse from being cut off. For example, the laser is short-circuited on the first conductive layer after being blown (turned on). Passive devices include resistors, inductors and capacitors

531836 V. Description of the invention (2) In the 1C of semiconductors, for example, Ar Buckle et al. In "Integrated Passive Processing Technology", Solid State Technology, November 2000. The map (layout) diagram of Figure 1 and the cross-sectional view of Figure 2-5 illustrate a non-volatile memory device including a spun silk formed by a second conductive layer and related methods. FIG. 1 is a layout diagram illustrating that the passive device region 10 includes a fuse, a peripheral transistor (peripheral transistor) region 12 having a crystal 18, and a memory cell array region 14 including a memory cell 16. Figure] also shows metal wires 5a, 5b, and 5 (:) for electrical interconnection. The peripheral transistor region 12 includes-a transistor 18 having a second conductive layer 22a and a first conductive layer. The gate formed by 20a, and the memory cell array region 4 include—the memory cell 16 has a control gate 22b and a floating gate 20b. A figure 2 to 5 are schematic diagrams along the line}, and the correlation is taken. The technical structure diagram is not shown in Figure 1 or Figure 2. The first conductive layer is formed by the first polycrystalline silicon layer 24, and the field oxide layer 26 is overlying the substrate over the field oxide layer. The insulating layer 28 is typically formed of a first oxide film / nitrogen 26. A second oxide film (0N〇) is formed. A field oxide layer is covered on the gate ^: ^ 9 The conductive layer is formed by a second polycrystalline silicon. The Shixi layer 30 & and the Shixi chemical crane layer 30b and the layer 2 are formed. Finally, a capped oxide layer circuit transistor is formed. The memory cell closed-poles 20b, 22b, and peripheral electrical binary values ... The poles 20a and 22a are formed through the patterned cover oxide layer 32 and the second layer of the i-th region: the conductive layer. The source of the memory cell 16 " and « υ is formed next to the memory cell gate 20b, Mb.

Page 6 531836 V. Description of the invention (3) The pole / non-polar region (not shown) of the crystal is formed on the substrate i. ,-People form boundary contacts as part of the patterning step shown in FIG. 4. 〶Understanding boundary contact can provide direct measurement of the first-conducting layer of a, 22a (part-part is very wide. Edge m is between the body 34Γ: shown in the figure: the peripheral transistor region 12 of the device forms a boundary contact area. : Two V This mask covers the oxide layer 32, the Shixi chemical crane layer_, and the predetermined part of the Xixi Rixi Shixi layer 30a is selectively removed. The same day guard, in other words, forms the boundary of the peripheral transistor region 丨 2 During the contact period, the fuse 11 in the passive device region 10 is formed by patterning the second conductive layer as shown in FIG. 5. It can be seen that the first nitrogen cut layer 36 and the first interlayer dielectric (one layer is a lice layer 40 (do Is an etching stop layer) and a second interlayer (ILD2) layer 42 are sequentially formed over the passive device region 10, the peripheral transistor region 12 and the memory cell array region 14 of the memory device. One or more contact holes are formed by etching the first and second, ILD1, ILD2 layers 38, 42, the first and second silicon nitride layers 36, 40, and a small portion of the cover oxide layer 32. Unfortunately, during the formation of contact holes in the ILD1 layer 38, 42 and the silicon nitride layer 36, 40 俾, the surface of the fuse 11 may be completely opened. The reason lies in the class difference between the fuses 丨 丨 the gate electrodes 22a ^, 22b. These two features can be seen in two parallel planes at different heights on the substrate. This class difference is most obvious in the center of the structure shown in Figure The surface of the tungsten silicide layer of the gate 22a which is higher than the fuse is opened before the surface of the tungsten silicide layer forming the fuse 11 is exposed. As a result, the contact hole 5a of the fuse 11 is completely open. Thus, the metal contact hole 5 a formed electrode or conducting path 5 5 a

Page 7 531836 V. Description of the invention (4) '' ------------ Linked to the refining silk '^ ^' as shown in the passive device area 10 of Figure 5. The credibility of such a memory device is poor — for details, as will be described later. Figure 5 illustrates the final associated memory steps that shape the conduction paths 55b and 55c. This step may include depositing a first silicon nitride layer 36, an ILD1 layer 38, a second nitride stopper M''Λ ^, a 4 layer 40, and a second ILD2 layer 42 on the entire surface of the memory device. , Including # ^ # such as α PU into the Leyi placement area 10, the peripheral transistor area 12 and the memory cell array area 1 4 of the main I # pattern, and then use conductive materials to fill the shape FIG. 5 shows that the contact hole 5 b ′ 5 c 俾 forms a plurality of conductive paths 55 b ′ 5 5 c. And 5 5a husband & 丨, Γ In the passive device area 10 where the fuse 11 is formed, the fuse of the conduction circuit 丨 丨 is a thin oxide layer, so it cannot be completed due to the class difference indicated in the 5C instructions discussed above. The tungsten silicide layer 30b is exposed to the airless area of the dagger. ^ Depending on the structure of the relevant technical method, electrical reception is impeded. This π 1 „electrical contact inhibition is also often a source of reliability problems for textual and memory devices and other semiconductor dreams. Daggers > Bodywear can be easily placed ^ Μ / ι ψχ ^ This Maoming provides a For passive contact of integrated circuit devices, the #said kind of strike 丨 a & + clothing area provides reliable let the selected circuit legislative energy gain &% / 1 to shoot: 谷 谷 吹 and other so-called virtual map 檨 fγI人 # 崎 的 升 咼 的 户口 Kouyu (shoulder J) is formed below the part η formed on it. The shoulder area is made of the peripheral transistor junction _ passive device material. The contact hole is formed reliably It extends above the same material device that extends through the layer and extends to the integrated passive device. The electrical layer and the passive electrode can penetrate through.

531836, description of the invention (5) Hole formation: Reliable contact with integrated passive device. Fig. 1 is a brief description of the relevant technology. Fig. 2'5 is a top plan view of the βΐι 支 Tibetan Zhuang device. FIG. 6 is a non-volatile embodiment of a passive memory device with a passive device area in a specific embodiment of the sequential manufacturing method. Invention of the;-:: = line: -J, taken ... ^ "Sequential method steps of device manufacturing in column m. This bamboo shoot + μ details of a preferred embodiment of a memory cell, =: = 丨The device is divided into a memory cell area, multiple passive areas, a peripheral circuit transistor area, and-to drive 呓 r II .: said: the circuit transistor area contains peripheral circuit transistors with ΐ; =: electricity includes stacking Question structure. The skin-moving device area includes resistors, inductors, or fuses in a Shute structure and form. The top view of the non-volatile memory device cloth according to the present invention is illustrated here! Lines are used to describe passive devices such as fuses, and a little comparison: the structure of the body and memory cells. Figure 6 is very similar to Figure 1, but the fuse ln is special because it cooperates with the invention according to a preferred embodiment. Unique. A rectangular dummy pattern or raised shoulder area 44 is formed below the fuse U1 105a line 105! The raised shoulder area 44 is formed on the metal wiring side, and these areas will provide advantages over related ones. The main advantages of the technique. 〇 is the γ-γ along the line of FIG. Volatile snoring Xia ',, .... Sectional view of the structure ...

531836

The field oxide layer 1 2 6 is formed in the semiconducting yam and isolation region. The field oxide layer 126 is formed by defining an active region and a LOCOS type isolation and forming a dielectric material on a wooden surface of a substrate or by using a memory cell array region 114, a hi region 170, and a dip region 180 formed at the center. Each package 116 includes a source 120b (the first polycrystalline silicon layer), as shown in FIG. 1 and an oceanic moving gate 128, which controls the interrogation pole (the second-to-two-layer absolute silicon layer 136). The first interlayer is Γ gate 8 2: m, the second silicon nitride layer 140 is used as a stop layer and the second and H y "ILD2" 142. Finally, as shown in the figure, the bit line electrode 155c is connected to> and the pole 1 8 0. In the peripheral transistor region 112, the peripheral circuit transistor 118 includes a source / drain region 17 0, 1 0 0 and a substrate 1 0, and the gate is provided with a first conduction Layer (first part) 120a, interlayer insulating film (0N〇) layer 128 is formed on the first conductive layer 1220a and the second conductive layer 2 2a is formed on the interlayer insulating film (0N0) layer 1 28. The gate extends along the field oxide layer 丨 2 6 to form a boundary conduction path 155b connecting the second conductive layer 122a and the first conductive layer 120a, as shown in the figure. Part of the second transmission The conductive layer 1 22a is exposed through the adjacent contact pattern, and it is convenient to form the contact between the first conductive layer 120a and the second conductive layer 122a through the conductive path 155b through the contact hole 105b. In the passive device region 1 1 0, the first conductive The first and second laterally spaced dummy patterns or shoulder regions 44 (44a, 44b) of the layer are formed on the field oxide layer 1 26. Each of the dummy patterns 44 is made of a plurality of small dummy patterns. The dummy pattern 4 The thickness of 4 is a virtual pattern defining a near vertical 4+ on the field oxide layer

Page 10 531836 V. Description of the invention (7) The ΤΛV dummy pattern 44a '445 is located between the lower degree and lateral width of the field oxide layer 126 to define the storm region. The fuse is formed by the second conductive layer (the first layer and the 13th layer of the Shixihua cast layer), and covers the lateral width of the exposed area of the dummy layer 126 in FIG. The dissolving filament includes a part covered on the lateral direction exposed by the field oxide layer 126, a second part covered on the first dummy pattern 44a, and a third part covered on the first dummy pattern 44b. The fuse ill is insulated from the dummy pattern 44 by the interlayer insulating layer (0N〇) i28. A cap oxide layer 132 as a protective layer is formed over the second conductive layer. The contact hole 104 of the contact path 155a is formed in the dummy pattern 44 and penetrates the ILD2 layer 142, the second silicon nitride layer 14o, the ILD1 layer 138, the first silicon nitride layer 136, and the cover oxide layer.丨 3 2. Therefore, the conductive path 155a formed via the contact hole 105a is substantially aligned with the dummy pattern 44. The formation of the dummy pattern 44 under the fused wire π 1 electrode 1 55a is such that the fuse 1 1 1 and the second conductive layer 122a of the gate transistor 8a are substantially coplanar. As such, according to a specific embodiment of the present invention, the related technical problem of the surface of the fuse 1 11 not being fully exposed during the formation of the fuse i i i contact hole 105a can be prevented. 7 to 11 are cross-sectional views showing a manufacturing method of a non-volatile material according to a specific embodiment of the present invention. Fig. 7 shows a method of forming the dummy pattern 44. A field oxide layer 126 defining an active region is formed on the semiconductor substrate 101. A tunnel oxide layer 106 is formed on the memory cell array region 114 active region, and a gate oxide layer 108 is formed on the peripheral circuit region 112 active region. As shown in FIG. 7, the first polycrystalline silicon layer 丨 2 4 is patterned in the passive device area 11 531 836 5. Description of the invention (8) The dummy pattern 44 is formed. 'Figure 8 shows the memory cell 1 16 stack Nie M ^., The interrogator and the peripheral circuit transistor 1 18 stack: the formation method. The interlayer insulating layer 128, the second polycrystalline silicon layer 130a, a layer 130b on top of it, and a protective layer < a cover oxide layer 132 are sequentially formed on the substrate 101 structure. The tungsten silicide layer i30b reduces the resistance of the second side a. The Wei insulating layer 128 is preferably formed of a first oxide-produced fossil evening film 'and a second oxide film (ON.).

The current oxide layer 1 3 2, the tungsten silicide layer i 3 〇b, the second polycrystalline silicon layer i 3 〇 & %% edge layer 1 2 8 and the first polycrystalline silicon layer 丨 2 4 in the peripheral transistor circuit The gates of the peripheral circuit transistor 1 1 8 are etched to form 1 2 0 a, 1 2 2 a. = Pole 120a, 1228 is patterned and extends above the field oxide layer i26. The conventional method of ion implantation is to introduce the substrate 101 to form the memory cell 116, and the regions 170, 18 and the source / sink regions of the peripheral circuit transistor 118 (not shown in the figure). According to a preferred embodiment of the invention, the thicknesses of the layers in the patterned gate region are as follows: The first polycrystalline layer is about 2000 angstroms; the OO layer is about 155 angstroms; the second polycrystalline layer = layer " silicide The tungsten layer and the cap oxide layer are each about 10 Angstroms; the first and second silicon nitride layers are each about 500 Angstroms; the first ILD layer is about 8,000 Egypt; the second ILD layer (ILD2) is about 2, 500 Angstroms. .

Of course, those skilled in the art will understand that the thickness of the specific layer has no particular limitation on the present invention ~ It is expected that they can be alternately stacked and still belong to the essence and scope of the present invention. The method of forming the boundary contact area 134 and the fuse 111 is shown in FIG. Peripheral electricity f: The first part of the body electrode 12a uses a boundary contact mask to expose the pattern by oxidizing the cover and a part of the gate electrode 1 2 2a.

Page 12 531836 V. Description of the invention (9) A zone 134 is as described above with reference to FIG. 4. During the formation of the boundary contact region 134, the fuse 1 1 1 covers the oxide layer through the etching mask 3, the second polycrystalline silicon layer 130a, and the tunnel over the field oxide layer 126 of the passive device region 110. A compound layer 1 3 0 b is formed. The preferred fuses 1 1 1 have their source parts overlapped, in other words cover or surround the dummy pattern 44 as shown in the figure. FIG. 10 illustrates a method of forming the contact holes 105a, 105b, and 105c. A first trapped nitride nitride layer 1 3 6 (hereinafter referred to as an etching stopper or simply a stopper layer) is deposited on the surface of the obtained structural substrate. A first ILD (ILD1) layer 38, a second stop silicon nitride layer 140, and a second ILD (ILD2) layer 142 are formed on the first stop silicon nitride layer 136 in this order. Then, the second ILD layer 142, the second nitrogen blocking layer 140, the first ILD layer 138, the first nitride blocking layer 13Θ, and the cap oxide layer 1 3 2 are used in this order and formed on The metal contact mask patterns (not shown in the figure) on the second I Ld layer 1 42 are used as etching masks to form the contact holes 105a, 105b, and 105c. The contact holes 105a, 105b, and 105c are filled with a conductive material to form conductive paths 1 5 5 a, 1 5 5 b, and 1 5 5 c. The contact holes 1 0 5 a and 10 5 b according to the present invention are tightly stretched through two layers to make a complete a contact with the tungsten oxide layer 1 3 0b in the fuse region of the passive device region π 0 'and Make a complete electrical contact with the first conductive layer 120a at the boundary contact region 134 of the peripheral transistor region 112. It was also found in the contact hole 10 5c in the memory cell array area 4 that stretched through the multilayer to the substrate 10m, but did not open in the active area > into an undesired recess. . The contact holes 105a, 105b, and 105c expose the first conductive layer (the first part) and the first conductive layer (the first part) and the first conductive layer (the first part of the gate electrode) of the memory cell transistor 116 and the peripheral circuit transistor. Part two) i22a surface and Hyun silk 111 watch

Page 13 531836

. Seeing the solder wire i and w, the pattern a is formed strictly 44. The surface of the fuse 1 1 1 and the peripheral circuits are light, and the surface of the m1A solar heliosphere is preferably a substantial hill surface, as shown in Figure I. . Therefore, it is possible to avoid the problems related to the technical interface 1 and instrument 1 that are not fully exposed during the engraving of the contact hole I 05a. The electrode or conduction circuit 1 5 5 a, 1 5 5 b, and 1 5 5 c are deposited on the second ILD layer 142 by using the shizhisha technology, and the structure plane 4 of the resulting structure is cracked. Thus, the shape The bit line electrode 155c is connected to the memory cell crystal chip to take %% daily gain 1 1 6 drain 1 8 0, fuse thunder 1 5 5 a is connected to the fuse 1 1 1 and the electrode 1 51h,% Let Ub b be connected to the peripheral circuit lightning crystal 1 1 8 gate first part 1 2 0 a and second part 1 2 2 a.

FIG. 11 is similar to FIG. 10 and shows a particularly useful embodiment of the present invention. The passive device in 1 is fused. From Figure 1, it can be seen that the laser cutting beam is applied in a controlled manner to the fuse inside the semiconductor passive device area 110. The i can generate the thin film spinning nl in the substantial middle area of the dummy area 4 through laser melting and blowing. Opening 48. People who understand the important structural advantages of hot buckle technology are better than the conventional thick fuses. Thick melted filaments may be undesirably reconnected after laser melting (the credibility is caused by conductive or semi-conductive debris m flail).

The foregoing preferred embodiments disclose and present methods and structures that can implement some of the exemplary embodiments of the present inventor. Those skilled in the art can derive other methods and structures within the spirit and scope of the present invention. Therefore, the scope of the method and structure according to the present invention is not limited to the preferred embodiments shown and described herein.

Page 14 531836 Schematic description

Page 15

Claims (1)

531836 __Case No. 90116245_f / year // month on month / ______ 6. Patent application scope 1. A passive device structure includes: an insulating layer formed on a semiconductor substrate; the edges of Tian Bilin The dummy pattern is composed of a patterned conductive layer formed on the insulating layer. The thickness of the dummy pattern defines the vertical width of the dummy pattern on the insulating layer. The dummy pattern is between the exposed areas of the insulating layer during the period Lower limit height lateral width; a second patterned conductive layer covering the dummy pattern and the lateral width of the exposed insulating layer to form a passive device; and adjacent electrodes that are substantially aligned with the laterally spaced dummy pattern and connected To the second patterned conductive layer. 2. The passive device structure according to item 1 of the patent application scope, further comprising: a layer of a first oxide film / a silicon nitride film / a second oxide film (0 N 0) covering the horizontally spaced dummy pattern The 0 N 0 layer is inserted between the separate dummy patterns and overlies the second patterned conductive layer. 3. The passive device structure according to item 1 of the patent application scope, further comprising: one or more pairs of composite layers, including an etch stop layer covering the second patterned conductive layer, and a layer of interlayer dielectric ( An ILD) layer covers the etch stop layer. 4. The passive device structure according to item 1 of the patent application scope, wherein the passive device is selected from the group consisting of a resistor, an inductor, and a fuse. 5. The passive device structure according to item 1 of the patent application scope, wherein the first patterned conductive layer is a first polycrystalline silicon layer. O: \ 72 \ 72272-91112l.ptc Page 16 531836 Amendment No. 90116245 6. Scope of patent application 6. For the passive device structure of the first scope of patent application, the second patterned conductive layer is a composite material layer including a layer The second polycrystalline silicon layer and a silicide layer cover the second polycrystalline silicon layer. 7. An integrated circuit device formed on a semiconductor substrate, comprising: a transistor formed on the substrate, the transistor including a source region, a non-region, a first part of the gate, and a second part of the gate And a first insulator is interposed between the first part and the second part; the first and second shoulders have a predetermined vertical width and are formed on the substrate and spaced apart from each other in the lateral direction; a layer is formed on the substrate A first patterned conductive layer, the first patterned conductive layer includes a first portion covered on a first substrate, a second portion covered on a first shoulder, and a first portion covered on a second shoulder Three parts; a second insulator inserted between the first and second shoulders and a first patterned conductive layer; and a conductive path connected to the first patterned conductive layer formed on the substrate The second and third parts. 8. The integrated circuit device according to item 7 of the patent application scope, wherein the first patterned conductive layer is a passive device. 9. The integrated circuit device according to item 8 of the patent application scope, wherein the passive device is selected from the group consisting of a resistor, an inductor and a fuse. 10. The integrated circuit device according to item 7 of the patent application scope, wherein the shoulder portion is formed of a polycrystalline thin film. 11. The integrated circuit device according to item 7 of the scope of patent application, wherein the first patterned conductive layer is conducted by a composite material including a polycrystalline silicon film and a silicide film O: \ 72 \ 72272-911121.ptc Page 17 531836 _ Case No. 90116245_f / year // 2nd month / _ ^ __ VI. Patent application scope Film composition. 12. The integrated circuit device according to item 7 of the patent application scope, further comprising: an insulating layer interposed between the shoulder and the first portion of the first patterned conductive layer, and a substrate. 1 3. The integrated circuit device according to item 7 of the scope of patent application, wherein the first and second insulation systems are formed of a first oxide film / silicon nitride film / second oxide film (ONO). 14. A integrated circuit device formed on a semiconductor substrate, comprising: a transistor formed on the substrate; the transistor includes a source region, a > region, a gate first part, and a gate second part And a first insulator are interposed between the first part and the second part; the first and second shoulders have a predetermined vertical width and are formed on the substrate and spaced apart from each other in the lateral direction; a layer is formed on the substrate A first part covered on the first substrate, a second part covered on the first shoulder, and a third part covered on the second shoulder; a second insulator, which is plugged Placed between the first and second shoulders, and the first patterned conductive layer; and a conductive path, which is connected to the second and third portions of the first patterned conductive layer, wherein the first part of the gate and The shoulder is made of the first thin film of the same material, O: \ 72 \ 72272-911121.ptc page 18 531836 _ case number 90116245_f / year // month name ___ 6. The scope of the patent application and the second part of the gate and the first patterned conductive layer are from the second Made of thin film of the same material. 15. The integrated circuit device of item 14 in the scope of patent application, wherein the first patterned conductive layer is a passive device. 16. The integrated circuit device according to item 15 of the scope of patent application, wherein the passive device is installed in a group selected from a resistor, an inductor and a fuse. 17. The integrated circuit device according to item 14 of the patent application scope, wherein the first same material is a polycrystalline thin film. 18. The integrated circuit device according to item 14 of the scope of patent application, wherein the second same material is a composite conductive film including a polycrystalline silicon film and a silicide film. 19. The integrated circuit device according to item 14 of the patent application scope, further comprising: an insulating layer interposed between the shoulder and the first portion of the first patterned conductive layer, and the substrate. 20. The integrated circuit device according to item 14 of the patent application scope, wherein the first and second insulation systems are formed of a first oxide film / a silicon nitride film / a second oxide film (0 N 0). 2 1. A semiconductor device having a memory cell array region and a peripheral circuit region formed on a semiconductor substrate. The device includes: a memory cell transistor including a source / drain region, a floating gate, and a control gate. And a first insulator which is inserted between the control gate and the floating gate and is formed in the memory cell array region of the semiconductor substrate; a peripheral circuit transistor including a source / drain region and a first gate O: \ 72 \ 72272-911121.ptc page 19 531836 _ case number 90116245_f / year // month △ / a _ «__ VI. The scope of patent application, the second part of the gate, and the part formed in the first part A second insulator and a second part formed on the second insulator, which are formed on the substrate of the peripheral circuit transistor; the first and second shoulders, which are made of the first patterned conductive layer and are on the substrate The peripheral circuit area has a defined vertical extension 'and is spaced from each other in the lateral extension direction; a passive device is a peripheral circuit area formed on the substrate by a second patterned conductive layer, and includes a A first portion, a second portion covering the first shoulder, and a third portion covering the second shoulder; a third insulator inserted between the shoulder and the passive device; and The conductive path is connected to the second and third portions of the second patterned conductive layer in the peripheral circuit area. 2 2. The device according to item 21 of the patent application, wherein the conduction path is substantially aligned with the shoulder. 2 3. The device according to item 21 of the patent application, wherein the first part of the gate and the shoulder are made of the first thin film of the same material. 2 4. The device according to item 21 of the scope of patent application, wherein the first thin film of the same material is a polycrystalline silicon thin film. 25. The device according to item 21 of the scope of patent application, wherein the second part of the gate electrode and the second patterned conductive layer are made of a second thin film of the same material. 26. The device according to item 21 of the scope of patent application, wherein the second thin film of the same material is a composite conductive film including a polycrystalline stone film and a stone material film. O: \ 72 \ 72272-911121.ptc Page 20 531836 Case No. 90116245 f / year // montha / Amendment VI. Application for patent scope 2 7. For the device of scope 21 for patent application, it further includes: An insulating layer is inserted between the shoulder and the first part of the passive device and the substrate. 28. The device according to item 27 of the patent application scope, wherein the insulating layer is a field oxide layer. 29. The device according to item 21 of the scope of patent application, wherein the first insulator, the second insulator and the third insulation system are formed of an oxide film / silicon nitride film / oxide film (ONO). 30. The device according to item 21 of the patent application scope, wherein the passive device is selected from the group consisting of a resistor, an inductor and a fuse. 31. The device according to item 21 of the patent application scope, wherein the passive device is a fuse. 3 2. — An integrated circuit device having a memory cell array region and a peripheral circuit region formed on a semiconductor substrate. The device includes: a memory cell transistor including a source / drain region, a floating gate, and a control. The gate and the first insulator are inserted between the control gate and the floating gate and are formed in the memory cell array region of the semiconductor substrate; a peripheral circuit transistor including a source / drain region, a first part of the gate, The second part of the gate, the second insulator formed on the first part and the second part formed on the second insulator, the peripheral circuit transistor system is formed on the substrate and the peripheral circuit transistor; Two shoulders, which are made of the first patterned conductive layer and have a defined vertical extension on the substrate and the peripheral circuit area, and are separated from each other in the lateral extension direction; O: \ 72 \ 72272-911121.ptc Page 21 531836 _ Case No. 90116245_ Foreign Year // Month / Day Amendment__ VI. Patent application scope A fuse is formed by a second patterned conductive layer on the substrate The peripheral circuit area on the top includes a first portion covered on the substrate, a second portion covered on the first shoulder, and a third portion covered on the second shoulder; a third insulator, It is inserted into the shoulder and the fuse; the conduction path is connected to the second and third parts of the fuse in the peripheral circuit area, where the first part of the gate, the floating gate and the first patterned conduction The layer is made of the first same material, and the second part of the gate electrode, the control gate, and the second patterned conductive layer are made of the second same material. 3 3. The integrated circuit device according to item 32 of the scope of patent application, wherein the first same material is a polycrystalline silicon thin film. 3 4. The integrated circuit device according to item 32 of the scope of patent application, wherein the second same material is a composite conductive film including a polycrystalline silicon film and a silicide film. 35. The integrated circuit device according to item 32 of the patent application scope, further comprising: an insulating layer interposed between the shoulder and the first part of the wire, and the substrate. 36. The integrated circuit device according to item 32 of the patent application scope, wherein the first, second and third insulation systems are formed of a first oxide film / silicon nitride film / second oxide film (NO) . O: \ 72 \ 72272-911121.ptc Page 22