CN108683414A - General mode filter - Google Patents
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- CN108683414A CN108683414A CN201810814383.4A CN201810814383A CN108683414A CN 108683414 A CN108683414 A CN 108683414A CN 201810814383 A CN201810814383 A CN 201810814383A CN 108683414 A CN108683414 A CN 108683414A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
The invention discloses a kind of general mode filters, including：Data delay deposit unit, including：Two input terminals；Four output ends；Be time-multiplexed logical operation cumulative unit, including：Five data input pins, five filtering parameter input terminals；The logical operation cumulative unit that is time-multiplexed is used for the second difference in rear four beats output of the predetermined tempo of clock signal, second difference by the first, second and third product and value subtract the 4th and the 5th product and obtain, wherein, the first product is the product of digital input signals and the first filtering parameter；The second/tri- product is the product of the first/bis- delay digital input signals and the second/tri- filtering parameter；Four/five product is the product of the first/bis- delay digital output signal and the four/five filtering parameter；Saturation arithmetic unit, for obtaining digital output signal according to the second difference.Effectively save resources of chip can be realized by implementing the present invention, and data input signal is effectively treated.
Description
Technical field
The present invention relates to wave filter technology field, more particularly to a kind of general mode filter.
Background technology
Filter is widely used in amplifier, analog-digital converter, digital analog converter, radio frequency, sensing as a basic module
In the chips such as device.The design of general mode filter can neatly obtain high pass, low pass, band logical, band according to configuration and fall into filtering
Device, the design of filter can effectively handle the filtering of digital signal, be widely applied.The transmission letter of universal filter
Number can be expressed as：
It can be to the frequency of input as the signal that the time increaseds or decreases is realized not by configuring b0, b1, b2, a1, a2
Same filter effect.Fig. 1 show design in the prior art, it is seen that needs at least five multiplier, two accumulators, one
A tape symbol saturation arithmetic unit and delay time register unit.Resource occupation is quite big, it is difficult to meet and Audio Design is led
Chip miniaturization in domain and efficiently requirement.
Invention content
In view of this, the present invention is intended to provide a kind of general mode filter is effectively located with realizing effectively save resources of chip
Manage data input signal.
Specifically, the present invention provides a kind of general mode filter, including：
Data delay deposit unit, including：Clock signal input terminal, for receiving clock signal；First clock signal meter
Number result input terminal, for receiving the count results to the clock signal；First input end is for receiving digital input signals；
Second input terminal is for receiving digital output signal；First output end is for exporting the digital input signals when postponing described
First after the one of clock signal claps postpones digital input signals；Second output terminal is postponing for exporting the digital input signals
Second after the two of the clock signal clap postpones digital input signals；Third output end is for exporting the digital output signal
The first delay digital output signal after postpone the clock signal one claps；4th output end is defeated for exporting the number
Enter second delay digital output signal of the signal after postpone the clock signal two clap；
Be time-multiplexed logical operation cumulative unit, including：
First data input pin, for receiving the digital input signals；
Second data input pin, for receiving the first delay digital input signals；
Third data input pin, for receiving the second delay digital input signals；
4th data input pin, for receiving the first delay digital output signal；
5th data input pin, for receiving the second delay digital output signal；
Second clock signal-count result input terminal, for receiving the count results to the clock signal；
First filtering parameter input terminal, the second filtering parameter input terminal, third filtering parameter input terminal, the 4th filtering parameter
Input terminal, the 5th filtering parameter are according to input terminal and logical operation accumulating signal output end；
The time division multiplexing logical operation cumulative unit is used to obtain the number in the predetermined tempo of the clock signal
First product of input signal and the first filtering parameter；It is obtained in the latter beat of the predetermined tempo of the clock signal described
Second product of the first delay digital input signals and the second filtering parameter, and then obtain first product and multiply with described second
First and the value that product is added；The second delay numeral input is obtained in latter two beat of the predetermined tempo of the clock signal
The third product of signal and third filtering parameter, so obtain described first and value and the third product addition second and
Value；The first delay digital output signal and the 4th filtering are obtained in rear three beats of the predetermined tempo of the clock signal
4th product of parameter, and then obtain described first and the first difference for subtracting each other of value and the 4th product；Believe in the clock
Number predetermined tempo rear four beats obtain it is described second delay digital output signal and the 5th filtering parameter the 5th product,
And then the second difference that first difference is subtracted each other with the 4th product is obtained, and it is defeated by the logical operation accumulating signal
Outlet exports the second difference；
Saturation arithmetic unit, for carrying out saturation arithmetic to second difference, obtaining and exporting the numeral output letter
Number.
Further, the general mode filter further includes bypass selecting unit, including：
First by-passing signal input terminal, for receiving the digital input signals；
Second by-passing signal input terminal, for receiving the digital output signal or the first delay digital output signal；
Enable signal input terminal is bypassed, for receiving bypass enable signal；
Filtering signal output end, for according to the bypass enable signal, selection to export the first by-passing signal input
The input signal at end or selection export the input signal of the second by-passing signal input terminal.
Further, the data delay deposit unit includes：
Concatenated first data delay register and the second data delay register, the first data delay register
Input terminal is as the first input end；The input terminal of the second data delay register is as first output end；Institute
The output end of the second data delay register is stated as the second output terminal；
Concatenated third data delay register and the 4th data delay register, the third data delay register
Output end is as the third output end；The output end of the 4th data delay register is as the 4th output end.
Further, the time division multiplexing logical operation cumulative unit includes：
Multiplier, including first data input pin, the second data input pin, third data input pin, the 4th data
Input terminal, the 5th data input pin, the first filtering parameter input terminal, the second filtering parameter input terminal, the input of third filtering parameter
End, the 4th filtering parameter input terminal, the 5th filtering parameter are according to input terminal and multiplying signal output end；
The multiplier is used to obtain the digital input signals and the first filtering in the predetermined tempo of the clock signal
First product of parameter, and first product is exported by the multiplying signal output end；In the clock signal
The latter beat of predetermined tempo obtains the second product of the first delay digital input signals and the second filtering parameter, and leads to
It crosses the multiplying signal output end and exports second product；In latter two beat of the predetermined tempo of the clock signal
The third product of the second delay digital input signals and third filtering parameter is obtained, and defeated by the multiplying signal
Outlet exports the third product；The first delay number is obtained in rear three beats of the predetermined tempo of the clock signal
4th product of output signal and the 4th filtering parameter, and multiplied by multiplying signal output end output the described 4th
Product；The second delay digital output signal and the 5th filtering are obtained in rear four beats of the predetermined tempo of the clock signal
5th product of parameter, and the 4th product is exported by the multiplying signal output end；
Plus/minus method accumulator, including：
First accumulating signal input terminal, for connecting the multiplying signal output end；
Second accumulating signal input terminal, the output end for connecting the 5th data delay register；And
Accumulating signal output end；
The plus/minus method accumulator passes through the accumulating signal output end for the predetermined tempo in the clock signal
Export first product；It is defeated by the accumulating signal output end in the latter beat of the predetermined tempo of the clock signal
Go out described first and value；It is exported by the accumulating signal output end in latter two beat of the predetermined tempo of the clock signal
Described second and value；Institute is exported by the accumulating signal output end in rear three beats of the predetermined tempo of the clock signal
State the first difference；Pass through described in accumulating signal output end output in rear four beats of the predetermined tempo of the clock signal
Second difference；
The input terminal of the 5th data delay register connects the accumulating signal output end, the 5th data delay
The output end of register is as the logical operation accumulating signal output end.
Further, general mode filter further includes：6th data delay register, the 6th data delay register
It is connected between the first data delay register and the second data delay register.
Further, the data delay deposit unit further includes reset signal input terminal.
Further, the clock signal is the clock signal of 384KHz.
Further, the digital input signals are the digital input signals of 48KHz.
Further, the digital input signals are the digital input signals of the 48KHz of 16bit quantizations.
Further, the general mode filter further includes counter, and the counter is the 384KHz clock domains of 3bit
Counter, the output of the counter connects the first clock signal count results input terminal and second clock signal-count
As a result input terminal.
The general mode filter of the present invention, by the way that data delay deposit unit is arranged comprising：Two input terminals；Four
Output end；Be time-multiplexed logical operation cumulative unit, including：Five data input pins, five filtering parameter input terminals；Time-division is multiple
It is used for the second difference in rear four beats output of the predetermined tempo of clock signal, the second difference with logical operation cumulative unit
By the first, second and third product and value subtract the 4th and the 5th product and obtain, wherein the first product be numeral input letter
Product number with the first filtering parameter；Second product is the product of the first delay digital input signals and the second filtering parameter；The
Three products are the product of the second delay digital input signals and third filtering parameter；4th product is the first delay numeral output letter
Product number with the 4th filtering parameter；5th product is the product of the second delay digital output signal and the 5th filtering parameter；It is full
And arithmetic element, for obtaining digital output signal according to the second difference；For digital input signals, using homologous generation when
Clock is filtered the time sharing clock of device, within the limited clock cycle, completes the function of filter, has greatly saved core
Piece area, has saved power consumption.In addition, by changing filter parameter, filter characteristic can arbitrary disposition.It is this can arbitrary disposition
Realization method is very simple, can be easily achieved various filtering performances.It can rapid configuration, occupancy design resource due to having
Characteristics, the universal filter of the invention such as small, low quiescent current (module can close) and good anti-technological fluctuation can answer extensively
For in the chips such as digital audio processing and digital power amplifier.
Description of the drawings
It is incorporated into specification and the attached drawing of a part for constitution instruction shows the embodiment of the present invention, and with
Principle for explaining the present invention together is described.In the drawings, similar reference numeral is for indicating similar element.Under
Attached drawing in the description of face is some embodiments of the present invention, rather than whole embodiments.Those of ordinary skill in the art are come
It says, it without creative efforts, can be obtain other attached drawings according to these attached drawings.
Fig. 1 is the structural schematic diagram of this prior art filter；
Fig. 2 is a kind of structural schematic diagram of general mode filter provided in an embodiment of the present invention；
Fig. 3 is a kind of sequence diagram of the time division multiplexing control of general mode filter provided in an embodiment of the present invention；
Fig. 4 is a kind of first actual emulation oscillogram of general mode filter provided in an embodiment of the present invention；
Fig. 5 is a kind of second actual emulation oscillogram of general mode filter provided in an embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.It needs
Illustrate, in the absence of conflict, the features in the embodiments and the embodiments of the present application mutually can be combined arbitrarily.
The present inventor is had found by studying：By the derivation to filter function, can obtain output signal is
One group of filter difference equation of input signal and output feedback, it is as follows：
Y (n)=b0*x (n)+b1*x (n-1)+b2*x (n-2)-a1*y (n-1)-a2*y (n-2)
B0 therein, b1, b2, a1, a2 are filter quantization parameters, can be configurable by register, in the present invention
With iRb0 [15:0],iRb1[15:0],iRb2[15:0],iRa1[15:0],iRa2[15:0] it substitutes.X (n) is exactly input letter
Number, 16bit quantized signals Din [15 is used in the present invention:0] it replaces, x (n-1) and x (n-2) be prolonging for input signal respectively
Signal after slow 1 claps, 2 clap.Din_d1 [15 has been used in the present invention:0] and din_d2 [15:0] it replaces.Y (n-1) and y
(n-2) be output signal delay 1 clap, 2 clap after signal.Dout_d1 [15 has been used in the present invention:0] and dout_d2
[15:0] it replaces.In this way, filter difference equation can be rewritten as：
Dout=iRb0*din+iRb1*din_q1+iRb2*din_q2-iRa1*dout_q1-iRa2* dout_q2
In Fig. 1 prior arts, five multiply-add (subtracting) operations of difference equation can be to go out within a bat as a result, cost is
Expensive chip area and large-sized encapsulation, this digital audio amplifier chip for minimizing and designing resource anxiety
Design, it is just very unsuitable.Consider the operation of this difference equation being divided into 5 beats to calculate, the value of operation is stored temporarily in tired
Add and (subtract) unit.As long as completing operation in Slow Clock (digital signal of 48KHz clock domains) one is clapped, so that it may with multiple with timesharing
For exchanging saving area for, reduce the target of chip size.
It is shown in Figure 2, general mode filter provided in an embodiment of the present invention, including：
Data delay deposit unit, including：Clock signal input terminal, for receiving clock signal；First clock signal meter
Number result input terminal, for receiving the count results to the clock signal；First input end is for receiving digital input signals；
Second input terminal is for receiving digital output signal；First output end is for exporting the digital input signals when postponing described
First after the one of clock signal claps postpones digital input signals；Second output terminal is postponing for exporting the digital input signals
Second after the two of the clock signal clap postpones digital input signals；Third output end is for exporting the digital output signal
The first delay digital output signal after postpone the clock signal one claps；4th output end is defeated for exporting the number
Enter second delay digital output signal of the signal after postpone the clock signal two clap；
Be time-multiplexed logical operation cumulative unit, including：
First data input pin, for receiving the digital input signals；
Second data input pin, for receiving the first delay digital input signals；
Third data input pin, for receiving the second delay digital input signals；
4th data input pin, for receiving the first delay digital output signal；
5th data input pin, for receiving the second delay digital output signal；
Second clock signal-count result input terminal, for receiving the count results to the clock signal
First filtering parameter input terminal, the second filtering parameter input terminal, third filtering parameter input terminal, the 4th filtering parameter
Input terminal, the 5th filtering parameter are according to input terminal and logical operation accumulating signal output end；
The time division multiplexing logical operation cumulative unit is used to obtain the number in the predetermined tempo of the clock signal
First product of input signal and the first filtering parameter；It is obtained in the latter beat of the predetermined tempo of the clock signal described
Second product of the first delay digital input signals and the second filtering parameter, and then obtain first product and multiply with described second
First and the value that product is added；The second delay numeral input is obtained in latter two beat of the predetermined tempo of the clock signal
The third product of signal and third filtering parameter, so obtain described first and value and the third product addition second and
Value；The first delay digital output signal and the 4th filtering are obtained in rear three beats of the predetermined tempo of the clock signal
4th product of parameter, and then obtain described first and the first difference for subtracting each other of value and the 4th product；Believe in the clock
Number predetermined tempo rear four beats obtain it is described second delay digital output signal and the 5th filtering parameter the 5th product,
And then the second difference that first difference is subtracted each other with the 4th product is obtained, and it is defeated by the logical operation accumulating signal
Outlet exports the second difference；
Saturation arithmetic unit, for carrying out saturation arithmetic to second difference, obtaining and exporting the numeral output letter
Number.
Further, the general mode filter further includes bypass selecting unit, including：
First by-passing signal input terminal, for receiving the digital input signals；
Second by-passing signal input terminal, for receiving the digital output signal or the first delay digital output signal；
Enable signal input terminal is bypassed, for receiving bypass enable signal；
Filtering signal output end, for according to the bypass enable signal, selection to export the first by-passing signal input
The input signal at end or selection export the input signal of the second by-passing signal input terminal.
By bypassing the setting of selecting unit, when bypass enable signal makes bypass be selected, general mode filter is not
Effect, digital input signals are not filtered completely, are directly exported.
Further, the data delay deposit unit includes：
Concatenated first data delay register and the second data delay register, the first data delay register
Input terminal is as the first input end；The input terminal of the second data delay register is as first output end；Institute
The output end of the second data delay register is stated as the second output terminal；
Concatenated third data delay register and the 4th data delay register, the third data delay register
Output end is as the third output end；The output end of the 4th data delay register is as the 4th output end.
Further, the time division multiplexing logical operation cumulative unit includes：
Multiplier, including first data input pin, the second data input pin, third data input pin, the 4th data
Input terminal, the 5th data input pin, the first filtering parameter input terminal, the second filtering parameter input terminal, the input of third filtering parameter
End, the 4th filtering parameter input terminal, the 5th filtering parameter are according to input terminal and multiplying signal output end；
The multiplier is used to obtain the digital input signals and the first filtering in the predetermined tempo of the clock signal
First product of parameter, and first product is exported by the multiplying signal output end；In the clock signal
The latter beat of predetermined tempo obtains the second product of the first delay digital input signals and the second filtering parameter, and leads to
It crosses the multiplying signal output end and exports second product；In latter two beat of the predetermined tempo of the clock signal
The third product of the second delay digital input signals and third filtering parameter is obtained, and defeated by the multiplying signal
Outlet exports the third product；The first delay number is obtained in rear three beats of the predetermined tempo of the clock signal
4th product of output signal and the 4th filtering parameter, and multiplied by multiplying signal output end output the described 4th
Product；The second delay digital output signal and the 5th filtering are obtained in rear four beats of the predetermined tempo of the clock signal
5th product of parameter, and the 4th product is exported by the multiplying signal output end；
Plus/minus method accumulator, including：
First accumulating signal input terminal, for connecting the multiplying signal output end；
Second accumulating signal input terminal, the output end for connecting the 5th data delay register；And
Accumulating signal output end；
The plus/minus method accumulator passes through the accumulating signal output end for the predetermined tempo in the clock signal
Export first product；It is defeated by the accumulating signal output end in the latter beat of the predetermined tempo of the clock signal
Go out described first and value；It is exported by the accumulating signal output end in latter two beat of the predetermined tempo of the clock signal
Described second and value；Institute is exported by the accumulating signal output end in rear three beats of the predetermined tempo of the clock signal
State the first difference；Pass through described in accumulating signal output end output in rear four beats of the predetermined tempo of the clock signal
Second difference；
The input terminal of the 5th data delay register connects the accumulating signal output end, the 5th data delay
The output end of register is as the logical operation accumulating signal output end.
Preferably, the clock signal is the clock signal of 384KHz；The number that the digital input signals are 48KHz is defeated
Enter signal；The digital input signals are the digital input signals of the 48KHz of 16bit quantizations, and general mode filter further includes：The
Six data delay registers, the 6th data delay register concatenation is in the first data delay register and the second data
Between delay time register.Because being the delay in 384k clock domains to 48K clock domains, it is such first delay have it is counter wear show
As needing that the 6th data delay register is added in this way, at this point, the 6th data delay register of the first data delay register is anti-
It is only counter to wear, ensure that subsequent 6th data delay register and the second data delay register be in 384K clock domains are delays
One claps and postpones two bats, that is to say, that the digital input signals of clock signal and 48KHz for 384KHz, that is, the first number
It is synchronous in fact according to delay time register (DFF), 384K clock domains is synchronized to from 48K clock domains.
Moreover it is preferred that the second by-passing signal input terminal is for receiving the first delay digital output signal；Because
384K clock domains are posted using come latch data, can saving one group when clock counter cnt=1 this when and synchronize
The setting of storage, that is, further saved design resource.For the quantized signal of 16bit, it can save 16 DFF's
Resource.It is achieved in and is optimized in a chip design using design resource, obtain optimum efficiency.
Further, the data delay deposit unit further includes reset signal input terminal.
Further, the general mode filter further includes counter, and the counter is the 384KHz clock domains of 3bit
Counter, the output of the counter connects the first clock signal count results input terminal and second clock signal-count
As a result input terminal.
Each signal in Fig. 2 is explained below by way of table 1：
Table 1
Fig. 3 is the sequence diagram of the time division multiplexing control of the present invention.For the digital sound of the 48KHz clock domains in audio frequency process
Frequency signal, we are filtered the time sharing clock of device using the clock (clk384) of the 384Khz of homologous generation, in 8 clocks
In period, the function in Fig. 1 is completed, chip area has greatly been saved, has saved power consumption.
Fig. 4 and Fig. 5 is the actual emulation waveform of the present invention, and the filtering output of data, is in clk_cnt [2:0]=1 when
It waits, the output of the 5th registers latch is carried out to signal, this completes the time-division processings of 384KHz clocks, when obtaining 48KHz
The filtered digital audio and video signals in clock domain.
The general mode filter of the present invention, which has, realizes that area is small, and filter characteristic can arbitrary disposition.It is this arbitrarily to match
It is very simple to set realization method, various filtering performances can be easily achieved.It can rapid configuration, occupancy design resource due to having
Small, low quiescent current (module can close) and the well characteristics such as anti-technological fluctuation, universal filter framework of the invention can be wide
It is general to be applied in the chips such as digital audio processing and digital power amplifier.
It will appreciated by the skilled person that realizing all or part of step/units/modules of above-described embodiment
It can be completed by the relevant hardware of program instruction, foregoing routine can be stored in computer read/write memory medium, should
When being executed, it includes the step corresponded in above-described embodiment each unit to execute to program；And storage medium above-mentioned includes：ROM、
The various media that can store program code such as RAM, magnetic disc or optical disc.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (10)
1. a kind of general mode filter, which is characterized in that including：
Data delay deposit unit, including：Clock signal input terminal, for receiving clock signal；First clock signal counts knot
Fruit input terminal, for receiving the count results to the clock signal；First input end is for receiving digital input signals；Second
Input terminal is for receiving digital output signal；First output end is postponing the clock letter for exporting the digital input signals
Number one clap after first delay digital input signals；Second output terminal is for exporting the digital input signals described in delay
Second after the two of clock signal clap postpones digital input signals；Third output end is prolonging for exporting the digital output signal
First after the one of the slow clock signal claps postpones digital output signal；4th output end is for exporting the numeral input letter
The second delay digital output signal number after postpone the clock signal two clap；
Be time-multiplexed logical operation cumulative unit, including：
First data input pin, for receiving the digital input signals；
Second data input pin, for receiving the first delay digital input signals；
Third data input pin, for receiving the second delay digital input signals；
4th data input pin, for receiving the first delay digital output signal；
5th data input pin, for receiving the second delay digital output signal；
Second clock signal-count result input terminal, for receiving the count results to the clock signal；
First filtering parameter input terminal, the second filtering parameter input terminal, third filtering parameter input terminal, the input of the 4th filtering parameter
End, the 5th filtering parameter are according to input terminal and logical operation accumulating signal output end；
The time division multiplexing logical operation cumulative unit is used to obtain the numeral input in the predetermined tempo of the clock signal
First product of signal and the first filtering parameter；Described first is obtained in the latter beat of the predetermined tempo of the clock signal
Postpone the second product of digital input signals and the second filtering parameter, and then obtains first product and the second product phase
First and the value added；The second delay digital input signals are obtained in latter two beat of the predetermined tempo of the clock signal
With the third product of third filtering parameter, and then second and the value of described first and value and the third product addition are obtained；
Rear three beats of the predetermined tempo of the clock signal obtain the first delay digital output signal and the 4th filtering parameter
The 4th product, and then obtain described first and the first difference for subtracting each other of value and the 4th product；In the clock signal
Rear four beats of predetermined tempo obtain the 5th product of the second delay digital output signal and the 5th filtering parameter, in turn
The second difference that first difference is subtracted each other with the 4th product is obtained, and passes through the logical operation accumulating signal output end
Export the second difference；
Saturation arithmetic unit obtains for carrying out saturation arithmetic to second difference and exports the digital output signal.
2. general mode filter as described in claim 1, which is characterized in that the general mode filter further includes bypass selection
Unit, including：
First by-passing signal input terminal, for receiving the digital input signals；
Second by-passing signal input terminal, for receiving the digital output signal or the first delay digital output signal；
Enable signal input terminal is bypassed, for receiving bypass enable signal；
Filtering signal output end, for according to the bypass enable signal, selection to export the first by-passing signal input terminal
Input signal or selection export the input signal of the second by-passing signal input terminal.
3. general mode filter as claimed in claim 1 or 2, which is characterized in that the data delay deposit unit includes：
Concatenated first data delay register and the second data delay register, the input of the first data delay register
End is used as the first input end；The input terminal of the second data delay register is as first output end；Described
The output end of two data delay registers is as the second output terminal；
Concatenated third data delay register and the 4th data delay register, the output of the third data delay register
End is used as the third output end；The output end of the 4th data delay register is as the 4th output end.
4. general mode filter as claimed in claim 3, which is characterized in that the time division multiplexing logical operation cumulative unit packet
It includes：
Multiplier, including the input of first data input pin, the second data input pin, third data input pin, the 4th data
End, the 5th data input pin, the first filtering parameter input terminal, the second filtering parameter input terminal, third filtering parameter input terminal,
Four filtering parameter input terminals, the 5th filtering parameter are according to input terminal and multiplying signal output end；
The multiplier is used to obtain the digital input signals and the first filtering parameter in the predetermined tempo of the clock signal
The first product, and pass through the multiplying signal output end and export first product；In the predetermined of the clock signal
The latter beat of beat obtains the second product of the first delay digital input signals and the second filtering parameter, and passes through institute
It states multiplying signal output end and exports second product；It is obtained in latter two beat of the predetermined tempo of the clock signal
The third product of second the delay digital input signals and third filtering parameter, and pass through the multiplying signal output end
Export the third product；The first delay numeral output is obtained in rear three beats of the predetermined tempo of the clock signal
4th product of signal and the 4th filtering parameter, and the 4th product is exported by the multiplying signal output end；
Rear four beats of the predetermined tempo of the clock signal obtain the second delay digital output signal and the 5th filtering parameter
The 5th product, and pass through the multiplying signal output end and export the 4th product；
Plus/minus method accumulator, including：
First accumulating signal input terminal, for connecting the multiplying signal output end；
Second accumulating signal input terminal, the output end for connecting the 5th data delay register；And
Accumulating signal output end；
The plus/minus method accumulator is exported for the predetermined tempo in the clock signal by the accumulating signal output end
First product；Institute is exported by the accumulating signal output end in the latter beat of the predetermined tempo of the clock signal
State first and value；Pass through described in accumulating signal output end output in latter two beat of the predetermined tempo of the clock signal
Second and value；In rear three beats of the predetermined tempo of the clock signal described the is exported by the accumulating signal output end
One difference；In rear four beats of the predetermined tempo of the clock signal described second is exported by the accumulating signal output end
Difference；
The input terminal of the 5th data delay register connects the accumulating signal output end, the 5th data delay deposit
The output end of device is as the logical operation accumulating signal output end.
5. general mode filter as claimed in claim 4, which is characterized in that further include：6th data delay register, it is described
6th data delay register concatenation is between the first data delay register and the second data delay register.
6. general mode filter as claimed in claim 5, which is characterized in that the data delay deposit unit further includes resetting
Signal input part.
7. general mode filter as claimed in claim 6, which is characterized in that the clock that the clock signal is 384KHz is believed
Number.
8. general mode filter as claimed in claim 7, which is characterized in that the digital input signals are the number of 48KHz
Input signal.
9. general mode filter as claimed in claim 8, which is characterized in that the digital input signals are 16bit quantizations
The digital input signals of 48KHz.
10. general mode filter as claimed in claim 9, which is characterized in that the general mode filter further includes counter,
The counter is the counter of the 384KHz clock domains of 3bit, and the output of the counter connects the first clock signal meter
Number result input terminal and second clock signal-count result input terminal.
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