CN102739195B - A kind of processing method of FIR filter, device and system - Google Patents
A kind of processing method of FIR filter, device and system Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of processing method of FIR filter, device and system.Embodiment of the present invention method comprises: obtain input signal, input signal is stored in the SRAM of FIR filter, each input signal is made to obtain N+1 signal data, then from SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data, then read to identify the filter coefficient obtained corresponding to current signal data according to this, current signal data and the filter coefficient got are carried out multiplying, obtain the multiplication result of current signal data, again the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtain add operation result and export, can be efficient, filtering in real time, economize on resources, reduce power consumption.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of processing method of FIR filter, device and system.
Background technology
Finite impulse response (FIR, FiniteImpulseResponse) filter, it is element the most basic in digital information processing system, at present, in digital communication systems, increasing employing FIR filter realizes digital signal filter, and FIR filter has stable and has the obvious advantages such as strict linear phase-frequency characteristic, and its transfer function can be expressed as:
Wherein, b
ifor filter coefficient, N is the exponent number of filter, z
-ifor the signal data of input.
At present, FIR filter is generally made up of multiple register, multiple multiplier and multiple adder, mainly according to FIR filter amplitude-frequency (FIR filter passband type, cut-off frequency, passband gain and stop band gain) or phase-frequency response requirement etc. by calculating filter coefficient b
iwith the exponent number N of filter.
As shown in Figure 1, Fig. 1 is the implementation structure of FIR filter of the prior art, and wherein, register is used for buffer memory input data, and multiplier is used for input data to be multiplied with filter coefficient, and adder is used for the Output rusults of multiplier to add up.During filtering, for a N rank filter, N+1 multiplier and N+1 adder is needed to carry out add operation and multiplying concurrently.Wherein, for N rank, input data are M-bit, filter coefficient b
iquantified precision be the FIR filter of X bit, need the memory cell of N × M-bit, N+1 2 input multiplication units, N number of 2 input adder units.
To in the research and practice process of prior art, the present inventor finds, FIR filter of the prior art needs to carry out buffer memory to input data, and multiplier and adder carry out filtering to input signal concurrently, when input signal bit wide is comparatively large, when exponent number is more, treatment effeciency is low, and need to take a large amount of logic, cost and power consumption are all very high.
Summary of the invention
Embodiments provide a kind of processing method of FIR filter, device and system, can filtering efficiently and in real time, economize on resources, reduce power consumption.
A processing method for FIR filter, comprising:
Obtain input signal;
Be stored in by input signal in the memory SRAM of FIR filter, make each input signal obtain N+1 signal data, N is the maximum order of FIR filter;
From SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data;
The filter coefficient obtained corresponding to current signal data is identified according to reading;
Current signal data and the filter coefficient got are carried out multiplying, obtains the multiplication result of current signal data;
The multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtains add operation result;
Export add operation result.
A kind of filter, comprising:
First acquiring unit, for obtaining input signal;
Storage element, the input signal for being got by the first acquiring unit is stored in the memory SRAM of FIR filter, and make each input signal obtain N+1 signal data, N is the maximum order of FIR filter;
Reading unit, for reading N+1 signal data corresponding to an input signal from SRAM successively, and mark is once read in renewal when often reading a signal data;
Second acquisition unit, for the filter coefficient read corresponding to mark acquisition current signal data upgraded according to reading unit;
Multiplying unit, the filter coefficient got for the current signal data that read by reading unit and second acquisition unit carries out multiplying, obtains the multiplication result of current signal data;
Add operation unit, is added up for the multiplication result obtained by multiplying unit by N+1 signal data corresponding to an input signal, obtains add operation result;
Output unit, for exporting the add operation result that add operation unit obtains.
A kind of filtering system, comprising: any one filter above-mentioned.
A kind of FIR filter, comprising:
SRAM, for obtaining input signal, and input signal is stored, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, and N+1 the signal data read successively corresponding to an input signal, upgrade when often reading a signal data and once read mark;
MUX, identifies the filter coefficient corresponding to the current signal data exporting and read with SRAM for reading of upgrading according to SRAM;
Multiplier, the filter coefficient exported for the current signal data that read by SRAM and MUX carries out multiplying, obtains the multiplication result of current signal data;
Adder, is added up for the multiplication result obtained by multiplier by N+1 signal data corresponding to an input signal, obtains add operation result, and export add operation result.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages:
The embodiment of the present invention adopts and first obtains input signal, the input signal got is stored in the SRAM of FIR filter, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, then from SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data, then read to identify the filter coefficient obtained corresponding to current signal data according to this, current signal data and the filter coefficient got are carried out multiplying, obtain the multiplication result of current signal data, again the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtain add operation result and export.The present embodiment is owing to being stored in the very high SRAM of density by the input signal of acquisition, and N+1 the signal data that can read successively from SRAM corresponding to an input signal, and renewal once reads to identify the filter coefficient obtained corresponding to current signal data when often reading a signal data, the filtration efficiency that buffer memory can be avoided to cause is low, can filtering efficiently and in real time; In the present embodiment, current signal data and the filter coefficient got are carried out multiplying, again the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, carry out filtering process by time-sharing multiplex adder and a multiplier, can economize on resources, reduce power consumption.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those skilled in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the implementation structure schematic diagram of FIR filter in prior art;
Fig. 2 is the flow chart of the processing method of FIR filter in the embodiment of the present invention;
Fig. 3 is a schematic diagram of filter in the embodiment of the present invention;
Fig. 4 is another schematic diagram of filter in the embodiment of the present invention;
Fig. 5 is a schematic diagram of FIR filter in the embodiment of the present invention;
Fig. 6 is another schematic diagram of FIR filter in the embodiment of the present invention;
Fig. 7 is the implementation structure schematic diagram of FIR filter in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those skilled in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of processing method of FIR filter, for filtering efficiently and in real time, can also economize on resources, reduce power consumption.The embodiment of the present invention also provides corresponding filter, and filtering system.Below describe in detail respectively.
Embodiment one
Angle from filter is described by the present embodiment, and wherein, this filter can be N rank, and input signal is M-bit, filter coefficient b
iquantified precision be the FIR filter (hereinafter referred to as FIR filter) of X bit.It should be noted that, the transfer function of the FIR filter in the present embodiment can be expressed as:
Wherein, b
ifor filter coefficient, N is the exponent number of FIR filter, z
-ifor the signal data of input.
A processing method for FIR filter, comprising:
First obtain input signal, the input signal got is stored in the holder (SRAM of FIR filter, StaticRandomAccessMemory) in, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, then from SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data, then read to identify the filter coefficient obtained corresponding to current signal data according to this, current signal data and the filter coefficient got are carried out multiplying, obtain the multiplication result of current signal data, again the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtain add operation result and export.
As shown in Figure 2, idiographic flow can be as follows:
101, input signal is obtained;
Wherein, the filter in the present embodiment generally has two ports, and a port is for obtaining input signal, and a port is used for output signal.
Wherein, for a N rank FIR filter, an input signal comprises N+1 signal data.Such as, for 3 rank FIR filter, an input signal comprises 4 signal datas.
102, the input signal got in step 101 is stored in the memory SRAM of FIR filter, makes each input signal obtain N+1 signal data; Such as, specifically can be as follows:
Optionally, input signal is stored in the memory SRAM of FIR filter, specifically can be realized by following steps: when the input signal got in step 101 is effective, obtain the write address of this input signal, then according to the write address of this input signal, input signal is write in SRAM.
Thus, each input signal can obtain N+1 signal data, and wherein, N is the maximum order of FIR filter.Such as, 3 rank FIR filter, each input signal includes 4 signal datas.
It should be noted that, the write address of next effectively input signal is that the write address of previous input signal adds 1, by that analogy, thus is write successively in SRAM by all input signals.In like manner, each input signal can obtain N+1 signal data.
Wherein, SRAM is static random access memory, and this SRAM is a kind of internal memory with static access facility, and do not need refresh circuit can preserve the data of its storage inside, density is high, and speed is fast, and performance is good.Compared to existing technology, signal data in the present embodiment stores in sram, avoids the problems such as filtration efficiency that buffer memory causes is low that use register to carry out.
Should be understood that, for N rank, input signal is M-bit, filter coefficient b
iquantified precision be the FIR filter of X bit, the SRAM of FIR filter is of a size of (N+1) × M.
103, from SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data; Such as, specifically can be as follows:
First, determine current need read input signal, and obtain current need read input signal read address.
Wherein, when supposing to get 10 input signals, need these 10 input signals carry out filtering successively and export.Such as, current need read input signal be second, first determine current need read input signal, first determine current need read input signal, and obtain current need read input signal read address.
Preferably, what obtain the input signal of current needs reading reads address, specifically can give the current input signal assignment needing to read according to the write address of input signal, and what obtain the input signal of current needs reading reads address.Wherein, from step 102, when an input signal is effective, can obtain N+1 signal data, this N+1 signal data is stored in certain address of SRAM, and wherein, namely the storage address of this input signal is the write address of this signal data.
Then, can according to input signal read address read successively from SRAM current need read input signal corresponding to N+1 signal data, and start be used to indicate read mark counter.
Wherein, obtain current need read input signal read address after, just can read address according to it N+1 corresponding for current input signal needing to read signal data is read out successively, and with this, each corresponding for all input signals needing to read signal data be read.
Meanwhile, can start one and be used to indicate the counter reading to identify, the signal data that this counter is used for reading counts, and when often reading a signal data, this counter adds 1, until N+1 signal data reads.
Preferably, the counter that can start 0 a to N counts the signal data read.After N+1 signal data reads, can be 0 by counter resets.
Wherein, read the exponent number identifying the FIR filter that can reflect corresponding to current signal data, therefore, according to reading the exponent number identifying the FIR filter can determined corresponding to current signal data.Should be understood that, the signal data that the exponent number of different FIR filter is corresponding different, the exponent number of FIR filter and the corresponding relation of signal data reflect by reading to identify.
Such as, for 3 rank FIR filter, comprising 4 signal datas when an input signal of this FIR filter is effective, can be Z respectively
-0, Z
-1, Z
-2and Z
-3.Wherein, first signal data of reading is Z
-0, it should be noted that, this Z
-0for current input signal data, this hour counter is 0; When input signal is through the 1st rank of FIR filter, reading second signal data is Z
-1, now upgrade and read to be designated 1; When input signal is through the 2nd rank of FIR filter, reading the 3rd signal data is Z
-2, this hour counter is 1, and renewal reads to be designated 2; When input signal is through the 3rd rank of FIR filter, reading the 4th signal data is Z
-3, this hour counter is 2, and renewal reads to be designated 3.For the FIR filter of other exponent numbers, by that analogy, repeat no more herein.
104, identify according to reading the filter coefficient obtained corresponding to current signal data;
Optionally, first filter coefficient can be stored in multiplexer (MUX, multiplexer).Should be understood that, input data wherein can export by MUX as required successively, convenient transmission.
Should be understood that, the exponent number respective filter coefficient of FIR filter, for a N rank FIR filter, its filter coefficient has N+1.Such as, for 3 rank FIR filter, filter coefficient has 4, can be b respectively
0, b
1, b
2and b
3.
Wherein, the exponent number identifying the FIR filter that can reflect corresponding to current signal data is read.Therefore, identifying according to reading the exponent number can determining FIR filter corresponding to current signal data, then can obtain filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined.And counter can indicate read mark.Such as, reading first signal data is Z
-0time, counter is 0, and corresponding mark of reading can be 0, and 0 rank of corresponding FIR filter, now filter coefficient is b
0, it should be noted that, this Z
-0for current input signal data; Reading second signal data is Z
-1time, when counter is 1, corresponding mark of reading can be 1, and 1 rank of corresponding FIR filter, now filter coefficient is b
1, by that analogy, repeat no more herein.Should be understood that, reading mark can also be the corresponding of other modes with the exponent number of FIR filter, and differ a citing herein.
Optionally, also corresponding filter coefficient can be obtained by mapping table according to reading mark from MUX.Wherein, this mapping table by reading mark by the exponent number of signal data, FIR filter and filter coefficient one_to_one corresponding, then often reads a signal data, according to mapping table, can obtain corresponding filter coefficient.
105, the filter coefficient got in the current signal data read in step 103 and step 104 is carried out multiplying, obtain the multiplication result of current signal data;
Wherein, from front, when an input signal is effective, N+1 signal data can be read, optionally, often read a signal data, can first by the multiplier of the signal data of this reading input FIR filter.And due to often read a signal data can upgrade once read mark, read to identify the filter coefficient corresponding to the signal data obtaining current reading by upgrading, then the filter coefficient corresponding with the signal data of current reading got is inputted in the multiplier of FIR filter, carry out multiplying with the signal data be input in multiplier.Such as, as read output signal data Z
-1time, first by Z
-1in input multiplier, and start a counter, now this counter is 1, and upgrades and read to be designated 1, and by reading mark 1, to obtain corresponding filter coefficient be b
1, and by b
1be input in multiplier and carry out multiplying, obtaining multiplication result is Z
-1× b
1, finally by this multiplication result Z
-1× b
1in input summer; As read output signal data Z
-2time, first by Z
-2be input in multiplier, this hour counter is 2, and upgrades and read to be designated 2, and by reading mark 21, to obtain corresponding filter coefficient be b
2, and by b
2be input in multiplier and carry out multiplying, obtaining multiplication result is Z
-2× b
2, finally by this multiplication result Z
-2× b
2in input summer, by that analogy, until N+1 signal data to be input in multiplier and to complete multiplying.
It should be noted that, an input signal in the present embodiment comprises N+1 signal data, to there being N+1 filter coefficient, needs to perform N+1 multiplying.
Wherein, due to filter coefficient b
ifor decimal, and have:
Optionally, generally filter coefficient is multiplied by gain 2
m, so that filter coefficient is turned to integer, to facilitate logical operation, then in final Output rusults divided by gain 2
m, to ensure that the center frequency point gain of FIR filter is for 0dB.
106, the multiplication result that N+1 signal data in step 105 corresponding to an input signal obtains is added up, obtain add operation result;
The present embodiment by serial carry out multiplying and filtering is carried out in add operation.Wherein, corresponding N+1 the signal data of input signal, can obtain multiplication result successively according to step 105, and is inputted successively by multiplication result in the adder of FIR filter and add up.Thisly first carry out multiplying by a multiplier, by an adder, the method that the result of multiplying carries out adding up is called the filtering method of time-sharing multiplex adder and multiplier again, filtering is realized by time-sharing multiplex adder and a multiplier, can power consumption be reduced, improve filtration efficiency.
Such as, first by the multiplication result input summer of first signal data that obtains, when obtaining the multiplication result of next signal data, add up in the multiplication result input summer of next signal data with previous multiplication result again, until the N+1 of an input signal signal data is exported.
Such as, the multiplication result of N+1 signal data corresponding to input signal can be obtained according to step 105, the multiplication result obtained successively: b
0× Z
-0, Z
-1× b
1, Z
-2× b
2z
-N× b
n, and add up in this multiplication result successively input summer, obtaining accumulation result is: b
0× Z
-0+ Z
-1× b
1+ Z
-2× b
2+ ... + Z
-N× b
n.
It should be noted that, an input signal in the present embodiment comprises N+1 signal data, to there being N+1 filter coefficient, needs to perform N+1 multiplying, and needs to perform the computing of N+1 sub-addition.
107, the add operation result in step 106 is exported.
Wherein, the output signal of the filter in the present embodiment is the add operation result in step 106, is: b
0× Z
-0+ Z
-1× b
1+ Z
-2× b
2+ ... + Z
-N× b
n.
Optionally, if filter coefficient is multiplied by gain 2 in step 104, basis after reading the step of the filter coefficient identified corresponding to acquisition current signal data
m, make filter coefficient turn to integer, then step 107 is specially:
Add operation result in step 106 is inputted in the divider of FIR filter divided by gain 2
m, make the gain of FIR filter center frequency point be 0dB, then export the business of division arithmetic.
Wherein, if this division arithmetic is not divided exactly, then by the remainder input summer of this division arithmetic, this remainder is added up with the multiplication result in input summer next time.
As from the foregoing, the present invention adopts and first obtains input signal, input signal is stored in the SRAM of FIR filter, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, then from SRAM, read N+1 signal data corresponding to an input signal successively, and mark is once read in renewal when often reading a signal data, then read to identify the filter coefficient obtained corresponding to current signal data according to this, current signal data and the filter coefficient got are carried out multiplying, obtain the multiplication result of current signal data, again the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtain add operation result and export.The present embodiment is owing to being stored in the very high SRAM of density the signal data that also can read successively corresponding to each input signal by input signal, the filtration efficiency that buffer memory can be avoided to cause is low, can filtering efficiently and in real time, and the present embodiment can identify according to reading the filter coefficient obtained corresponding to current signal data, filtering process can be carried out thus by time-sharing multiplex adder and a multiplier, can economize on resources, reduce power consumption.
Embodiment two
In order to better implement above method, the embodiment of the present invention additionally provides corresponding filter, as the device realizing the method in the embodiment of the present invention, this filter specifically can comprise the first acquiring unit 201, storage element 202, reading unit 203, second acquisition unit 204, multiplying unit 205, add operation unit 206 and output unit 207.Refer to Fig. 3:
First acquiring unit 201, for obtaining input signal.Wherein, the filter in the present embodiment generally has two ports, and a port is for obtaining input signal, and a port is used for output signal, therefore, can obtain input signal by of this filter port.
Storage element 202, is stored in the memory SRAM of FIR filter for the input signal got by the first acquiring unit 201, and make each input signal obtain N+1 signal data, N is the maximum order of FIR filter.
Wherein, storage element 202, specifically for when input signal is effective, the write address of the input signal that acquiring unit gets, and according to the write address of input signal, input signal is write in SRAM.
Reading unit 203, for reading N+1 signal data corresponding to an input signal from SRAM successively, and mark is once read in renewal when often reading a signal data;
Wherein, reading unit 203, specifically for determine current need read input signal, and obtain current need read input signal read address, and according to input signal read address read successively from SRAM current need read input signal corresponding to N+1 signal data.
Second acquisition unit 204, for the filter coefficient read corresponding to mark acquisition current signal data upgraded according to reading unit 203.
Wherein, second acquisition unit 204, specifically for according to the exponent number reading to identify the FIR filter determined corresponding to current signal data, obtains the filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined.
Multiplying unit 205, the filter coefficient got for the current signal data that read by reading unit 203 and second acquisition unit 204 carries out multiplying, obtains the multiplication result of current signal data.
Add operation unit 206, is added up for all multiplication results obtained by multiplying unit by N+1 signal data corresponding to an input signal, obtains add operation result.
Output unit 207, for exporting the add operation result that add operation unit 206 obtains.Wherein, add operation result can be exported by of this filter port.
First multiplying is carried out by multiplying unit 205 in the present embodiment, that the result of multiplying to be carried out adding up by add operation unit 206 again obtains Output rusults, namely by time-sharing multiplex multiplying unit 205 and add operation unit 206, can power consumption be reduced, improve filtration efficiency.
Preferably, in order to better realize the function of filter in the present embodiment, the filter in the present embodiment, also comprises: counting unit 208 and reset unit 209.Specifically can consult Fig. 4:
Wherein, counting unit 208, be used to indicate and read mark, when reading unit 203 often reads a signal data, counting unit 208 adds 1.
Reset unit 209, is reset to 0 by counting unit 208 after exporting add operation result when output unit 207.
In addition, multiplying unit 205, also for filter coefficient is multiplied by gain 2
m, make filter coefficient turn to integer; Then filter, also comprises: division arithmetic unit 210.Division arithmetic unit 210, for by add operation result divided by gain 2
m, obtain the quotient and the remainder of division arithmetic, and add up in the adder of the remainder of division arithmetic input FIR filter with the multiplication result of next input signal.
It should be noted that, concrete enforcement can See Examples one, repeats no more herein.
As from the foregoing, the present invention adopts the first acquiring unit 201 first to obtain input signal, and by storage element 202, the input signal that first acquiring unit 201 gets is stored in the memory SRAM of FIR filter, each input signal is made to obtain N+1 signal data, then from SRAM, N+1 signal data corresponding to an input signal is read successively by reading unit 203, and mark is once read in renewal when often reading a signal data, the filter coefficient read corresponding to mark acquisition current signal data upgraded according to reading unit 203 by second acquisition unit 204 again, then the filter coefficient that the current signal data read by reading unit 203 and second acquisition unit 204 get inputs respectively in multiplying unit 205 and carries out multiplying, and add up in the result of multiplying input add operation unit 206, finally input accumulation result by output unit 207.Because input signal can be stored in the very high SRAM of density by storage element 202 and can read signal data corresponding to each input signal successively by reading unit 203 in the present embodiment, the filtration efficiency that buffer memory can be avoided to cause is low, can filtering efficiently and in real time, and the present embodiment can obtain filter coefficient corresponding to current signal data according to reading to identify by second acquisition unit 204, filtering process can be carried out thus by time-sharing multiplex add operation unit and a multiplying unit, can economize on resources, reduce power consumption.
Embodiment three
Accordingly, the embodiment of the present invention additionally provides a kind of filtering system, and wherein, this filtering system comprises filter.
Wherein, this filter is for obtaining input signal, input signal is stored in the SRAM of FIR filter, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, N+1 signal data corresponding to an input signal is read successively from SRAM, and mark is once read in renewal when often reading a signal data, read to identify the filter coefficient obtained corresponding to current signal data according to this, current signal data and the filter coefficient got are carried out multiplying, obtain the multiplication result of current signal data, the multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtain add operation result and export.
It should be noted that, the filter of the present embodiment can be any one filter in embodiment two, and concrete enforcement can see previous embodiment two, and the present embodiment repeats no more.
Embodiment four
The present embodiment additionally provides a kind of FIR filter, and this FIR filter specifically can comprise SRAM401, MUX402, multiplier 403 and adder 404.Specifically can refer to Fig. 5:
SRAM401, for obtaining input signal, and input signal is stored, each input signal is made to obtain N+1 signal data, N is the maximum order of FIR filter, and N+1 the signal data read successively corresponding to an input signal, upgrade when often reading a signal data and once read mark.
Wherein, SRAM401, specifically for when input signal is effective, obtain the write address of input signal, and write input signal according to the write address of input signal, determine current need read input signal, and obtain current need read input signal read address, according to input signal read address read successively current need read input signal corresponding to N+1 signal data.
MUX402, identifies the filter coefficient corresponding to the current signal data exporting and read with SRAM for reading of upgrading according to SRAM.
Wherein, MUX402, specifically for the exponent number reading to identify the FIR filter determined corresponding to current signal data upgraded according to SRAM, exports the filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined.
Multiplier 403, the filter coefficient exported for the current signal data that read by SRAM and MUX carries out multiplying, obtains the multiplication result of current signal data.Wherein, this multiplier 403 is the multiplying unit in filter.
Adder 404, is added up for the multiplication result obtained by multiplier by N+1 signal data corresponding to an input signal, obtains add operation result, and export add operation result.Wherein, this adder 404 is the add operation unit in filter.
Wherein, first carry out multiplying by multiplier 403 in the present embodiment, then the result of multiplying carried out add up by adder 404 obtain Output rusults, namely by time-sharing multiplex multiplier 403 and adder 404, can power consumption be reduced, improve filtration efficiency.
In order to better realize the function of FIR filter in the present embodiment, the FIR filter in the present embodiment, also comprises: counter 405 and restorer 406, specifically can refer to Fig. 6:
Counter 405, be used to indicate and read mark, when SRAM often reads a signal data, counter adds 1; Wherein, counter 405 can count from 0 to N, and wherein, N is the exponent number of FIR filter.Wherein, this counter 405 is the counting unit in filter.
Restorer 406, for being 0 by counter resets after exporting add operation result when adder.Wherein, this restorer 406 is the reset unit in filter.
In addition, multiplier 403, also for filter coefficient is multiplied by gain 2
m, make filter coefficient turn to integer.Meanwhile, the FIR filter in the present embodiment also comprises: divider 407.Divider 407, for by add operation result divided by gain 2
m, obtain the quotient and the remainder of division arithmetic, add up in the remainder input summer of division arithmetic with the multiplication result of next input signal, and export the business of division arithmetic.Wherein, this divider 407 is the division arithmetic unit in filter.
As from the foregoing, the present invention can obtain input signal due to SRAM401, and the input signal got is stored, and N+1 the signal data that can read successively corresponding to each input signal, the filtration efficiency that buffer memory can be avoided to cause is low, can be efficient, filtering in real time, reduce power consumption, and the MUX402 in the present embodiment can identify filter coefficient corresponding to the current signal data that exports and read with SRAM according to reading of upgrading of SRAM401, filtering process can be carried out thus by time-sharing multiplex adder 403 and a multiplier 404, can economize on resources.
Embodiment five
Be described in detail the embodiment of the present invention with an embody rule example below, refer to Fig. 7, Fig. 7 is the implementation structure schematic diagram of FIR filter in the embodiment of the present invention:
Wherein, the FIR filter of the embodiment of the present invention can be N rank, and input signal is M-bit, filter coefficient b
iquantified precision be the FIR filter (hereinafter referred to as FIR filter) of X bit.
Wherein, the present embodiment completes multiplication operation or add operation needs Min (M, X) individual system clock cycle, by working as input signal effectively once, N+1 signal data can be read known, FIR filter input data break needs to be greater than (N+1) Min (M, X) individual system clock cycle.
Wherein, refer to Fig. 7, data_in is input signal, and din_vld is effective input signal, and wr_cnt is write operation counter, rd_cnt is read operation counter, wr_addr is write address, and rd_addr is for reading address, and divider is divider, data_out is output signal, and gain is the gain of FIR filter.
Be described for the effective input signal din_vld of one of them in input signal data_in below:
First, obtain input signal by SRAM, wherein, din_vld is an input signal when din_in is effective, and SRAM gets din_vld, and is stored by din_vld; Concrete, SRAM first can obtain the write address wr_addr of din_vld, is then write in SRAM by din_vld according to wr_addr.N+1 the signal data of din_vld can be obtained thus, and the wr_addr of this N+1 signal data, then can by by the wr_addr assignment of din_vld to rd_addr to obtain the rd_addr of din_vld, then read this N+1 signal data successively according to the rd_addr of din_vld.Wherein, this N+1 signal data is respectively: Z
-0, Z
-1, Z
-2, Z
-3z
-N.
Secondly, N+1 the signal data of din_vld is read successively according to the rd_addr of din_vld.Wherein, when read output signal data, what can start 0 a to N is used to indicate the counter rd_cnt reading to identify, the signal data read is counted, often reads a signal data, upgrade and once read mark, and rd_cnt is added 1, until N+1 signal data reads.
Then, the filter coefficient corresponding to N+1 the signal data obtaining din_vld can be identified according to reading.Wherein, read the exponent number identifying the FIR filter that can reflect corresponding to current signal data, therefore can obtain filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined, and the rd_cnt for counting the signal data read can indicate and reads mark.Therefore, the signal data read successively: 1, Z
-1, Z
-2, Z
-3z
-Nfilter coefficient corresponding is respectively: b
0, b
1, b
2, b
3b
n.Often read a signal data, carry out multiplying by the signal data of this reading input multiplier with corresponding filter coefficient, obtaining multiplication result is successively: b
0× Z
-0, Z
-1× b
1, Z
-2× b
2z
-N× b
n.
Then, often obtain a multiplication result, add up in this result input summer, therefore, obtaining accumulation result is: b
0× Z
-0+ Z
-1× b
1+ Z
-2× b
2+ ... + Z
-N× b
n.
Finally, this accumulation result is exported as output signal data_out.
It should be noted that, multiplier and adder can time-sharing multiplexs, namely often obtain a multiplication result, can carry out an add operation, and multiplying and add operation can be carried out, and can economize on resources simultaneously, lower power consumption, improve filtration efficiency.
It should be noted that, when gain, finally divided by gain gain, be that the signal of 0dB exports by gain.
It should be noted that, due to filter coefficient b
ifor decimal, generally by b
ibe multiplied by gain gain, with by b
iturn to integer, then after obtaining accumulation result, by this accumulation result divided by gain gain, to ensure that FIR filter gain is for 0dB, last export structure is the business of division arithmetic.It should be noted that, if when this division arithmetic is not divided exactly, then by the remainder input summer of this division arithmetic, the multiplication result in this remainder and next input signal is added up.
In like manner, when next input signal input, first obtain this input signal and stored in sram, then from SRAM, read N+1 corresponding to this input signal signal data successively, and mark is once read in renewal when often reading a signal data, filter coefficient corresponding to the current signal data needing to read is obtained by reading to identify, then the signal data of current reading and the filter coefficient corresponding with it are carried out multiplying, and multiplication result is added up, obtain accumulation result and export, until all input signals of filtering that needs are exported.
It should be noted that, concrete enforcement see above-described embodiment, can repeat no more herein.
One of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.
Above the processing method of a kind of FIR filter provided by the present invention, device and system are described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for those skilled in the art, according to the thought of the embodiment of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (17)
1. a processing method for FIR filter, is characterized in that, comprising:
Obtain input signal;
Be stored in the memory SRAM of described FIR filter by described input signal, make each input signal obtain N+1 signal data, N is the maximum order of described FIR filter;
From SRAM, read N+1 signal data corresponding to an input signal successively, and upgrade when often reading a signal data and once read mark, described in read to identify exponent number for determining the FIR filter corresponding to current signal data;
The filter coefficient obtained corresponding to current signal data is identified according to described reading;
Described current signal data and the filter coefficient got are carried out multiplying, obtains the multiplication result of current signal data;
The multiplication result that N+1 signal data corresponding to an input signal obtains is added up, obtains add operation result;
Export described add operation result.
2. method according to claim 1, is characterized in that, is describedly stored in the memory SRAM of described FIR filter by described input signal, comprising:
When described input signal is effective, obtain the write address of described input signal;
Described input signal writes in described SRAM by the write address according to described input signal.
3. method according to claim 2, is characterized in that, described N+1 the signal data read successively from SRAM corresponding to an input signal, and when often reading a signal data, mark is once read in renewal, comprising:
Determine current need read input signal, and obtain described current need read input signal read address;
According to described input signal read address read successively from described SRAM described current need read input signal corresponding to N+1 signal data, and start be used to indicate read mark counter;
When often reading a signal data, described counter is added 1.
4. method according to claim 3, is characterized in that, described acquisition described current need read input signal read address, comprising:
Give the described current input signal assignment needing to read according to the write address of described input signal, what obtain the input signal of described current needs reading reads address.
5. the method according to claim 3 or 4, is characterized in that, after the described add operation result of described output, also comprises:
Be 0 by described counter resets.
6. method according to any one of claim 1 to 4, is characterized in that,
The described exponent number reading the FIR filter of mark reflection corresponding to current signal data, then read described in described basis to identify the filter coefficient obtained corresponding to current signal data, comprising:
According to the described exponent number reading to identify the FIR filter determined corresponding to current signal data;
The filter coefficient corresponding to current signal data is obtained according to the exponent number of the FIR filter determined.
7. method according to any one of claim 1 to 4, is characterized in that, described described current signal data and the filter coefficient that gets are carried out the step of multiplying before, also comprise:
Described filter coefficient is multiplied by gain 2
m, make described filter coefficient turn to integer, described M is determined in the gain needed for described filter.
8. method according to claim 7, is characterized in that, the described add operation result of described output, comprising:
By described add operation result divided by gain 2
m, obtain the quotient and the remainder of division arithmetic, wherein, the remainder of described division arithmetic inputted in the adder of described FIR filter and add up with the multiplication result of the signal data of next input signal;
Export the business of described division arithmetic.
9. a filter, is characterized in that, comprising:
First acquiring unit, for obtaining input signal;
Storage element, is stored in the memory SRAM of FIR filter for the input signal got by described first acquiring unit, and make each input signal obtain N+1 signal data, N is the maximum order of described FIR filter;
Reading unit, for reading N+1 signal data corresponding to an input signal from SRAM successively, and upgrades when often reading a signal data and once reads mark, described in read to identify exponent number for determining the FIR filter corresponding to current signal data;
Second acquisition unit, for the filter coefficient read corresponding to mark acquisition current signal data upgraded according to described reading unit;
Multiplying unit, the filter coefficient got for the current signal data that read by described reading unit and described second acquisition unit carries out multiplying, obtains the multiplication result of current signal data;
Add operation unit, is added up for the multiplication result obtained by described multiplying unit by N+1 signal data corresponding to an input signal, obtains add operation result;
Output unit, for exporting the add operation result that described add operation unit obtains.
10. filter according to claim 9, is characterized in that,
Described storage element, for when input signal is effective, obtains the write address of the input signal that described acquiring unit gets, and writes in SRAM according to the write address of described input signal by described input signal;
Described reading unit, for determining the current input signal needing to read, and obtain described current need read input signal read address, and according to described input signal read address read successively from SRAM described current need read input signal corresponding to N+1 signal data;
Described second acquisition unit, for reading the exponent number identifying the FIR filter determined corresponding to current signal data described in basis, obtains the filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined.
11. filters according to claim 9 or 10, is characterized in that, also comprise:
Counting unit, be used to indicate and read mark, when reading unit often reads a signal data, described counting unit adds 1;
Reset unit, is reset to 0 by described counting unit after exporting add operation result when output unit.
12. filters according to claim 9 or 10, is characterized in that,
Described multiplying unit, also for described filter coefficient is multiplied by gain 2
m, make described filter coefficient turn to integer, described M is determined in the gain needed for described filter; Then described filter, also comprises:
Division arithmetic unit, for by described add operation result divided by gain 2
m, obtain the quotient and the remainder of division arithmetic, and the remainder of described division arithmetic is inputted in described add operation unit add up with the multiplication result of next input signal.
13. 1 kinds of filtering systems, is characterized in that, comprising:
Filter according to any one of claim 9 to 12.
14. 1 kinds of FIR filter, is characterized in that, comprising:
SRAM, for obtaining input signal, and described input signal is stored, each input signal is made to obtain N+1 signal data, described N is the maximum order of described FIR filter, and read N+1 signal data corresponding to an input signal successively, upgrade when often reading a signal data and once read mark, described in read the exponent number of mark for determining the FIR filter corresponding to current signal data;
MUX, identifies the filter coefficient corresponding to the current signal data exporting and read with described SRAM for reading of upgrading according to described SRAM;
Multiplier, the filter coefficient exported for the current signal data that read by described SRAM and described MUX carries out multiplying, obtains the multiplication result of current signal data;
Adder, is added up for the multiplication result obtained by described multiplier by N+1 signal data corresponding to an input signal, obtains add operation result, and export described add operation result.
15. FIR filter according to claim 14, is characterized in that,
Described SRAM, for when input signal is effective, obtain the write address of input signal, and write described input signal according to the write address of described input signal, determine the current input signal needing to read, and obtain described current need read input signal read address, according to described input signal read address read successively described current need read input signal corresponding to N+1 signal data;
Described MUX, for the exponent number reading to identify the FIR filter determined corresponding to current signal data upgraded according to described SRAM, exports the filter coefficient corresponding to current signal data according to the exponent number of the FIR filter determined.
16. FIR filter according to claims 14 or 15, is characterized in that, also comprise:
Counter, be used to indicate and read mark, when described SRAM often reads a signal data, described counter adds 1;
Restorer, for being 0 by described counter resets after exporting add operation result when described adder.
17. FIR filter according to claims 14 or 15, is characterized in that,
Described multiplier, also for described filter coefficient is multiplied by gain 2
m, make described filter coefficient turn to integer, described M is determined in the gain needed for described filter; Then described FIR filter, also comprises:
Divider, for by described add operation result divided by gain 2
m, obtain the quotient and the remainder of division arithmetic, the remainder of described division arithmetic inputted in described adder and add up with the multiplication result of next input signal, and export the business of division arithmetic.
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| CN106301285A (en) * | 2016-08-03 | 2017-01-04 | 深圳大学 | Based on fixed coefficient finite impulse response filter structure when resetting |
| JP6724828B2 (en) * | 2017-03-15 | 2020-07-15 | カシオ計算機株式会社 | Filter calculation processing device, filter calculation method, and effect imparting device |
| CN108627575B (en) * | 2017-03-23 | 2021-06-22 | 深圳开立生物医疗科技股份有限公司 | Fractional decimation filtering method and fractional decimation filtering apparatus |
| CN107592093A (en) * | 2017-08-18 | 2018-01-16 | 深圳大学 | A kind of Finite Impulse Response filter circuit |
| CN108900177B (en) * | 2018-06-14 | 2022-08-02 | 福建星海通信科技有限公司 | Method for filtering data by FIR filter |
| JP6970827B2 (en) * | 2018-06-25 | 2021-11-24 | オリンパス株式会社 | Arithmetic processing unit |
| CN109194307B (en) * | 2018-08-01 | 2022-05-27 | 南京中感微电子有限公司 | Data processing method and system |
| CN110808935B (en) * | 2019-10-31 | 2022-03-25 | 中国电子科技集团公司第二十九研究所 | Accurate and efficient implementation method and device for autocorrelation operation of linear frequency modulation signal |
| CN115102524B (en) * | 2022-07-07 | 2023-08-08 | 武汉市聚芯微电子有限责任公司 | Filter |
| CN117991243A (en) * | 2024-04-03 | 2024-05-07 | 海底鹰深海科技股份有限公司 | Sonar signal matched filtering processing method and system based on FPGA |
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