CN205647461U - Common mode rejection network filter with charge bleed -off - Google Patents

Common mode rejection network filter with charge bleed -off Download PDF

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Publication number
CN205647461U
CN205647461U CN201620521618.7U CN201620521618U CN205647461U CN 205647461 U CN205647461 U CN 205647461U CN 201620521618 U CN201620521618 U CN 201620521618U CN 205647461 U CN205647461 U CN 205647461U
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China
Prior art keywords
signal
current source
source array
frequency
low
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Expired - Fee Related
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CN201620521618.7U
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Chinese (zh)
Inventor
欧飞
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Mianyang Qin Qin Electronic Technology Co Ltd
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Mianyang Qin Qin Electronic Technology Co Ltd
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Priority to CN201620521618.7U priority Critical patent/CN205647461U/en
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Abstract

The utility model provides a common mode rejection network filter with charge bleed -off, the utility model relates to a signal processing technique field, it aims at solving prior art, and to have frequency of operation limited, and signal processing speed is low, and the strong and commonality of common mode low -frequency noise lowly waits technical problem. The utility model discloses it is main including a processing module for the duty cycle detects and charge bleed -off control, receives the preemphasized signal, including frequency matching programming module, sectional type programming current source and cass pond module, the network filtering module for high frequency signal keeps apart and low frequency signals filtering, receives the saturated delay signal of processing module output, including low frequency signals restrained circuit structure and charge bleed -off circuit structure, the 2nd processing module for the high frequency signal of network filtering module output is received, including 1 multiplexer to the high frequency signal modulation. The utility model is used for the peripheral interface chip of extensive high frequency information treatment facility.

Description

A kind of common mode inhibition network filter with charge discharging resisting
Technical field
This utility model relates to signal processing technology field, is specifically related to a kind of common mode inhibition with charge discharging resisting Network filter.
Background technology
At present, existing network filter circuit is only simple inductance component, when in different application scene, its There is a lot of problem.Essentially, simply use inductance component, can greatly limit to its maximum operating frequency;By In the polytype of communication receiving system, its input signal, not through any process, needs to take central authorities' process Equipment ample resources carries out signal processing;Input signal dutycycle is determined by input signal self completely, processes and lacks Weary efficiency;For preemphasized signal, its main information is all at HFS, and existing network filter apparatus exists Substantial amounts of common mode, low-frequency noise, can flood the useful information of input signal;Additionally, prior art lacks having The charge discharging resisting of storage lotus element, causes the useful information on spectrum line to flood, its system noise sound intensity after accumulation.
Summary of the invention
For above-mentioned prior art, this utility model purpose is to provide a kind of common mode inhibition with charge discharging resisting Network filter, it is limited that it aims to solve the problem that prior art exists operating frequency, and conversion speed is low, and common mode is low Frequently noise is strong and the low inferior technical problem of versatility.
For reaching above-mentioned purpose, the technical solution adopted in the utility model is as follows:
A kind of common mode inhibition network filter with charge discharging resisting, including preemphasized signal, also includes, first Processing module, controls for dutycycle detection and charge discharging resisting, receives preemphasized signal, including frequency Join programming module, stagewise program current source and detection programming module;Network filtering module, for high-frequency signal Isolation and low frequency signal filter, and receive the saturated time delayed signal of the first processing module output, believe including low frequency Number suppression circuit structure and charge discharging resisting circuit structure;Second processing module, modulates for high-frequency signal, receives The high-frequency signal of network filtering module output, including 1 multiplexer.
In such scheme, described frequency coupling programming module, post including the first buffer register and the second buffering Storage, all receives preemphasized signal;Programming chronotron, connects the first buffer register;Programming chronotron, the One buffer register and the second buffer register, common two frequencys multiplication driving saturated time delayed signal to be preemphasized signal Rate.
In such scheme, described stagewise program current source, including high five current source array, another setting depends on First depositor of secondary connection, the first decoder and the first latch are connected with high five current source array;In four Position current source array, separately arrange the second depositor, the second decoder and the second latch that are sequentially connected with and in four Position current source array connects;Low five current source array, separately arrange the 3rd depositor, the time delay electricity being sequentially connected with Road and the 3rd latch are connected with low five current source array;Reference voltage source, it respectively with high five current sources Array, in four current source array and low five current source array connect, reference voltage source is high five current sources Array, in four current source array and low five current source array reference voltage is provided.
In such scheme, described detection programming module, including the D being connected with low frequency signal suppression circuit structure Trigger, d type flip flop connects program counter.
In such scheme, described d type flip flop, can include clock module, principal and subordinate's level DICE latch module, Output module.Principal and subordinate's level DICE latch module includes main module and from level module, includes first from level module To the 4th from node, it is single-particle sensitive nodes from node, from node successively Logic adjacent.Wherein principal and subordinate's level DICE Latch module is according to the clock signal exported from described clock module and the external data signal of reception, to output Module exports corresponding data signal.Described d type flip flop, it is also possible to include that protection band, protection band include PMOS Protection of pipe band, NMOS tube protection band.PMOS protection band is constituted by P+ is active, and NMOS tube protection band is active by N+ Constitute, between single-particle sensitive nodes, be both provided with protection band.The width of protection band uses having in design rule Source minimum widith.
Compared with prior art, the beneficial effects of the utility model: improve operating frequency;Suppress significantly common mode, Low-frequency noise;Output feedback pulse count detection in real time is provided;Not only isolating device is carried out charge discharging resisting, also To for suppressing the electric capacity of low-frequency noise to release;During the signal with coding of final output can be directly connected to The analog-digital converter of centre processing equipment, economizes on resources for the next processing equipment, is conducive to extensive process high frequency letter Number, promote the work efficiency of system.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually Beyond the feature repelled and/or step, all can combine by any way.
Below in conjunction with the accompanying drawings this utility model is described further:
Embodiment 1
Preemphasized signal Signal1, inputs buffer register U1 and buffer register U2 to the first processing module, By programming chronotron U3, buffer register U1 output letter is set according to the dutycycle of preemphasized signal Signal1 Number time delay;Frequency coupling programming module outputs signal to the isolating coupler T1 of network filtering module FILTER Winding, its Secondary Winding low frequency signal suppression circuit structure, it is specially its Secondary Winding and is parallel with mutually string The electric capacity C1 and electric capacity C2 of connection, and its Secondary Winding is also connected and electric capacity C3, inductance L1 and electric capacity C4;Inductance The two ends of L1 are connected to electric capacity C7 and electric capacity C6, and the output signal of network filtering module FILTER passes through electric capacity C6 and electric capacity C7 is received by the multiplexer MUX1 of the second processing module, thus obtains the modulation high frequency after coding Signal;First processing module meets the framework of FPGA FPGA, and the second processing module can It is suitable for special integrated ASIC.Winding of isolating coupler T1 is also associated with field effect transistor Q1, and Secondary Winding is also Connecting has field effect transistor Q2, field effect transistor Q1 and field effect transistor Q2 to be controlled by stagewise program current source I1, point Segmentation program current source I1 connects field effect transistor Q1 and the grid of field effect transistor Q2 by load resistance R1;Electric capacity C6 To be connected to field effect transistor Q3 and field effect transistor Q4, field effect transistor Q3 and field effect transistor Q4 the most controlled with electric capacity C7 In processing module ASIC, stagewise program current source I1, voltage source Va1+ of processing module ASIC, field effect Pipe Q1, field effect transistor Q2, field effect transistor Q3 and field effect transistor Q4 constitute charge discharging resisting circuit structure.Detection programming Module connects electric capacity C1 and electric capacity C2 by electric capacity C5, it is thus achieved that feedback signal, and this signal inputs to d type flip flop U7, Connecting Schmidt trigger U9 by field effect transistor Q9, Schmidt trigger U9 outfan is connected to phase inverter U12, Phase inverter U12 output to or the input port of door U11, or the input port of door U11 be also connected with d type flip flop U7's~Q End and its outfan connect program counter, and this structure is according to the frequency utilization monostable principle timing controlled set Detection high and low frequency signal respectively;According to the signal detected after circuit logic so that circuit is operated in Signal frequency in certain reference clock frequency set less than low frequency or higher than high frequency setpoint frequency signal all incite somebody to action By this detection module, thus trigger stagewise program current source I1 and carry out reset operation and electric charge operation of releasing, The signal that the reference clock of d type flip flop U7 detects as required selects external clock CLOCK_B.
There is unknown mutation in hardware, and the progress of technology is the reference of selection standard.But it is in order at and changes bad practicality Novel, or cost viewpoint, only from the selection of technical scheme of practicality.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model is not It is confined to this, any belongs to those skilled in the art in the technical scope that this utility model discloses, can The change readily occurred in or replacement, all should contain within protection domain of the present utility model.

Claims (4)

1. there is a common mode inhibition network filter for charge discharging resisting, including preemphasized signal, it is characterised in that Also include,
First processing module, controls for dutycycle detection and charge discharging resisting, receives preemphasized signal, wherein wrap Include frequency coupling programming module, stagewise program current source and detection programming module;
Network filtering module, filters for high-frequency signal isolation and low frequency signal, receives the first processing module output Saturated time delayed signal, including low frequency signal suppression circuit structure and charge discharging resisting circuit structure;
Second processing module, modulates for high-frequency signal, receives the high-frequency signal of network filtering module output, its Include a multiplexer.
A kind of common mode inhibition network filter with charge discharging resisting the most according to claim 1, its feature It is, described frequency coupling programming module, including
First buffer register and the second buffer register, all receive preemphasized signal;
Programming chronotron, connects the first buffer register;Programming chronotron, the first buffer register and second are delayed Rush depositor, the common doubled frequency driving saturated time delayed signal frequency to be preemphasized signal frequency.
A kind of common mode inhibition network filter with charge discharging resisting the most according to claim 1, its feature It is, described stagewise program current source, including
High five current source array, separately arrange the first depositor, the first decoder and first being sequentially connected with and latch Device is connected with high five current source array;
In four current source array, separately arrange be sequentially connected with the second depositor, the second decoder and second latch Device with in four current source array be connected;
Low five current source array, separately arrange the 3rd depositor, delay circuit and the 3rd latch being sequentially connected with It is connected with low five current source array;
Reference voltage source, it respectively with high five current source array, in four current source array and low five electric currents Source array connects, reference voltage source be high five current source array, in four current source array and low five electric currents Source array provides reference voltage.
A kind of common mode inhibition network filter with charge discharging resisting the most according to claim 1, its feature It is, described detection programming module, including the d type flip flop being connected with low frequency signal suppression circuit structure, D Trigger connects program counter.
CN201620521618.7U 2016-05-31 2016-05-31 Common mode rejection network filter with charge bleed -off Expired - Fee Related CN205647461U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620521618.7U CN205647461U (en) 2016-05-31 2016-05-31 Common mode rejection network filter with charge bleed -off

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Application Number Priority Date Filing Date Title
CN201620521618.7U CN205647461U (en) 2016-05-31 2016-05-31 Common mode rejection network filter with charge bleed -off

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106786814A (en) * 2017-01-16 2017-05-31 威海新北洋正棋机器人股份有限公司 A kind of leadage circuit
CN109257028A (en) * 2018-09-27 2019-01-22 东南大学 A kind of low-power consumption plural number double-two-order unit circuit of current multiplexing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106786814A (en) * 2017-01-16 2017-05-31 威海新北洋正棋机器人股份有限公司 A kind of leadage circuit
CN106786814B (en) * 2017-01-16 2019-07-12 威海新北洋正棋机器人股份有限公司 A kind of leadage circuit
CN109257028A (en) * 2018-09-27 2019-01-22 东南大学 A kind of low-power consumption plural number double-two-order unit circuit of current multiplexing
CN109257028B (en) * 2018-09-27 2022-04-15 东南大学 Current multiplexing low-power consumption complex biquad unit circuit

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CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161012

Termination date: 20210531