CN108667432A - A High Efficiency and High Linearity Envelope Modulator - Google Patents

Abstract

The invention discloses an envelope modulator with high efficiency and high linearity, which comprises an envelope shaping unit, a bias tracking unit, a linear amplifier stage, a current sensing unit, a hysteresis comparator, a switch drive unit and a switch amplifier stage connected in sequence. The envelope shaping unit performs DC shift and peak clipping on the input envelope and then inputs it to the linear amplification stage and the bias tracking unit. The bias tracking unit feeds back the gate voltage of the class AB output NMOS transistor of the linear amplifier stage to the envelope shaping unit and then outputs a positive shift voltage. The resistance feedback network of the linear amplifier stage linearly amplifies and shapes the envelope signal, and compensates the ripple current of the switch amplifier stage. The current sensing unit senses the output current of the linear amplifier stage and generates a voltage drop across the sense resistor. The switch drive unit strengthens the output signal of the hysteresis comparator to drive the work of the subsequent switch amplifier stage. The envelope modulator of the invention has high linearity and low power consumption.

Description

A High Efficiency and High Linearity Envelope Modulator

technical field

The invention belongs to the technical field of wireless communication, and relates to an envelope modulator with high efficiency and high linearity applied in an envelope tracking power amplifier.

Background technique

Envelope tracking technology is a technology to improve the efficiency of power amplifiers under high peak-to-average power ratio signals. The envelope modulator generates dynamic voltage to supply power to the drain or collector of the power tube. The input of the power amplifier is a signal without separation of amplitude and phase, which reduces the system's requirement for delay; at the same time, the power supply voltage does not need to track the envelope signal very accurately. In an envelope tracking system, since the bandwidth of the envelope signal is often much larger than that of the baseband envelope phase-inseparable signal, it is difficult for the envelope modulator to guarantee its output efficiency when amplifying the envelope signal linearly. The design of the hybrid envelope modulator combining series and parallel requires that the power supply voltage and the envelope signal must change synchronously, so a trade-off must be made between noise bandwidth and efficiency during design. In addition, there are certain difficulties in the realization of large-bandwidth envelope modulators. There are also challenges in the design of low-loss and low-power current sensing units in hybrid envelope amplifiers; reducing the power consumption of hysteresis comparators in envelope amplifiers is also a challenge. Another difficulty of . Several commonly used envelope modulator structures often face the deterioration of linearity while achieving high efficiency.

Contents of the invention

Aiming at the problems existing in the prior art, the present invention provides an envelope modulator with high efficiency and high linearity. The envelope is processed by envelope shaping technology and then sent to the envelope modulator. At the same time, the linear The gate voltage of the class AB output NMOS transistor of the amplifier stage is fed back to the envelope shaping circuit and generates a positive shift voltage, thereby achieving high efficiency and high linearity.

In order to achieve the above object, the present invention adopts the following technical solutions.

A high-efficiency and high-linearity envelope modulator of the present invention is characterized in that it includes an envelope shaping unit, a bias tracking unit, a linear amplification stage, a current sensing unit, a hysteresis comparator, a switch drive unit and a switch Amplification level.

The envelope shaping unit performs DC shift and peak clipping on the input envelope and then inputs it to the linear amplification stage and the bias tracking unit.

The bias tracking unit feeds back the gate voltage of the class AB output NMOS transistor of the linear amplifier stage to the envelope shaping unit, so that the envelope shaping unit outputs a positive shift voltage.

The linear amplification stage includes a folded broadband operational amplifier OTA, an AB class output Buffer, and a resistor feedback network; the AB class output Buffer includes a first transistor M1 and a second transistor M2; the linear amplifier stage will pass through its resistance The envelope signal of the feedback network is linearly amplified and shaped, and the ripple current generated by the switching amplifier stage is compensated at the same time.

The current sensing unit detects the output current of the linear amplifier stage; the output current generates a voltage drop on the sensing resistor R _sen of the current sensing unit, and the voltage drop is compared with the window voltage of the hysteresis comparator. If the output voltage of the hysteresis comparator is When the level is low, the fifth transistor M5 in the switching amplifier stage is turned on, and the sixth transistor M6 is turned off. If the output voltage of the hysteresis comparator is high, the fifth transistor M5 is turned off, and the sixth transistor M6 is turned on.

The switch drive unit is used to strengthen the output signal of the hysteresis comparator to drive the switch amplifier stage to work.

The switching amplifier stage is used to provide most of the current to the load, and the rest of the current is provided by the linear amplifier stage.

Further, the input terminal of the envelope shaping unit is connected to the envelope signal, and its output terminal is connected to the input terminal of the bias tracking unit; the gate voltage of the second transistor M2 of the AB class output Buffer is connected to the bias tracking unit; The output terminal of the tracking unit is fed back to the envelope shaping unit; the gate of the first transistor M1 of the AB class output Buffer is connected to the gate of the third transistor M3 of the current sensing unit, and the gate of the second transistor M2 is connected to the current sensing unit The gate of the fourth transistor M4 of the unit; the drains of the third transistor M3 and the fourth transistor M4 of the current sensing unit and the positive terminal of the current sensing resistor R _sen are simultaneously connected to the positive input terminal of the hysteresis comparator; the hysteresis comparator The output terminal of the switch drive unit is connected to the input terminal of the switch drive unit; the output terminal of the switch drive unit is connected to the input terminal of the switch amplifier stage; the output terminal of the switch amplifier stage, the drains of the first transistor M1 and the second transistor M2, the current sense resistor The negative terminal of R _sen and the negative input terminal of the hysteresis comparator are connected to the positive terminal of the load resistor R _load at the same time, and the voltage of the positive terminal of the load resistor R _load is used as the output signal of the envelope modulator.

Further, the envelope shaping unit includes a transconductance stage, a V-I conversion unit, a bias feedback unit, a twentieth transistor M20, a twenty-first transistor M21, a twenty-fifth transistor M25, and a twenty-sixth transistor M26 ; The twentieth transistor M20 and the twenty-first transistor M21 are a pair of current mirrors, and the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are current bias transistors; the output of the transconductance stage is connected to the input of the V-I conversion unit , the output of the bias feedback unit is connected to the V-I conversion unit.

Further, the transconductance stage includes the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12, the thirteenth transistor M13, the tenth transistor The fourth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19. The VI conversion unit includes a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24. The bias feedback unit includes a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, and a thirtieth transistor M30. The gate of the seventh transistor M7 is connected to the input envelope signal V _env,i , the sources of the seventh transistor M7 and the eighth transistor M8 are connected to the drain of the eleventh transistor M11, and the drain of the seventh transistor M7 is connected to the sixteenth transistor M11. The drain of the transistor M16, the gate of the eighth transistor M8 is connected to the gate of the ninth transistor M9 and the drain of the eighth transistor M8, the drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9 and the nineteenth transistor The drain of M19, the sources of the ninth transistor M9 and the tenth transistor M10 are connected to the drain of the twelfth transistor M12, the drain of the tenth transistor M10 is connected to the drain and gate of the seventeenth transistor M17, and the tenth transistor The gate of M10 is connected to the source of the twenty-second transistor M22, the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 are connected to the bias voltage VB1, the source of the eleventh transistor M11 is connected to the twelfth transistor M12 The source of the transistor M12 is connected to the power supply voltage, the sources of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to the power supply voltage, the gate of the thirteenth transistor M13 is connected to the gate of the fourteenth transistor M14 and the thirteenth transistor M13 The drain of the thirteenth transistor M13 is connected to the drain of the fifteenth transistor M15, the drain of the fourteenth transistor M14 is connected to the drain of the eighteenth transistor M18, and the gate of the fifteenth transistor M15 is connected to the drain of the fifteenth transistor M15. The gate and drain of the sixteenth transistor M16, the sources of the fifteenth transistor M15 and the sixteenth transistor M16 are grounded, the gate of the eighteenth transistor M18 is connected to the gate and drain of the seventeenth transistor M17, the tenth The sources of the seventh transistor M17 and the eighteenth transistor M18 are grounded, the gate of the nineteenth transistor M19 is connected to the bias voltage VB2, the source of the nineteenth transistor M19 is grounded, the twentieth transistor M20 and the twenty-first transistor M21 The source of the twentieth transistor M21 is grounded, the gate of the twenty-first transistor M21 is connected to the gate and drain of the twentieth transistor M20, the drain of the twentieth transistor M20 is connected to the drain of the twenty-second transistor M22, the twenty-first The drain of the transistor M21 is connected to the drain of the twenty-fourth transistor M24, the gate of the twenty-second transistor M22 is connected to the drain of the eighteenth transistor M18, and the source of the twenty-second transistor M22 is connected to the twenty-third transistor The drain and gate of M23, the gate of the twenty-third transistor M23 is connected to the gate of the twenty-fourth transistor M24 and the drain of the twenty-seventh transistor M27, and the source of the twenty-third transistor M23 is connected to the second The drain of the fifteenth transistor M25, the source of the twenty-fourth transistor M24 is connected to the drain of the twenty-sixth transistor M26, the gates of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the bias voltage VB1, The sources of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the power supply voltage, the drains of the twenty-fourth transistor M24 and the twenty-first transistor M21 are connected to the output envelope signal V _env,o , the second The gate of the twenty-seventh transistor M27 is connected to the gate and drain of the twenty-eighth transistor M28, the sources of the twenty-seventh transistor M27 and the twenty-eighth transistor M28 are grounded, and the twenty-eighth transistor M28 is grounded. The drain of the transistor M28 is connected to the drain of the twenty-ninth transistor M29, the gate of the twenty-ninth transistor M29 is connected to the voltage VP1, the source of the twenty-ninth transistor M29 is connected to the drain of the thirtieth transistor M30, and the third The gate of the tenth transistor M30 is connected to the voltage VP2, and the source of the thirtieth transistor M30 is connected to the power supply voltage.

Further, the bias tracking unit includes the 31st transistor M31, the 32nd transistor M32, the 33rd transistor M33, the filter resistor _RL and the filter capacitor _CL ; the gate of the 31st transistor M31 connected to the bias voltage Vn, the source of the thirty-first transistor M31 is grounded, the drain of the thirty-first transistor M31 is connected to the drain of the thirty-second transistor M32 and the gate of the thirty-third transistor M33, and the third The source of the twelve transistor M32 is connected to the drain of the thirty-third transistor M33, the source of the thirty-third transistor M33 is connected to the power supply voltage, and the gate of the thirty-second transistor M32 is connected to the filter resistor R _L and the filter capacitor C _L , the other end of the filter resistor _RL is connected to the envelope signal V _env,o , and the other end of the filter capacitor C _L is grounded.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

1. In the present invention, the envelope signal is shaped and used as the input of the envelope amplifier, and the bias circuit feeds back the gate voltage of the AB class output NMOS transistor of the linear amplifier stage to the envelope shaping unit and generates a positive shift at the output Voltage, forming a self-biased envelope feedback loop, thereby improving the linearity of the envelope tracking system;

2. The envelope modulator circuit designed by the present invention greatly reduces the power consumption of the overall circuit by performing a certain degree of DC shift and envelope peak clipping on the envelope signal.

Description of drawings

FIG. 1 is a schematic circuit diagram of an embodiment of the high-efficiency and high-linearity envelope modulator of the present invention.

Fig. 2 is a schematic circuit diagram of an envelope shaping unit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit structure of a bias tracking unit according to an embodiment of the present invention.

Fig. 4 is a simulation result diagram of a circuit envelope signal passing through an envelope shaping unit according to an embodiment of the present invention.

FIG. 5 is a simulation result diagram of instantaneous current consumption of a linear amplifier stage and a switch amplifier stage according to an embodiment of the present invention.

Fig. 6 is a simulation result diagram of outputting the third-order intercept point OIP3 according to an embodiment of the present invention. The abscissa indicates the input power, and the ordinate indicates OIP3, both in dBm.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic circuit structure diagram of an embodiment of the high-efficiency and high-linearity envelope modulator of the present invention. Fig. 2 is a schematic circuit diagram of an envelope shaping unit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a circuit structure of a bias tracking unit according to an embodiment of the present invention. Wherein M1, M2, ... M33 shown in Fig. 1- Fig. 3 can respectively be represented as a first transistor M1, a second transistor M2, ... a thirty-third transistor M33 in sequence.

The high-efficiency and high-linearity envelope modulator of the embodiment shown in Figure 1 includes an envelope shaping unit 1, a bias tracking unit 2, a linear amplification stage 3, a current sensing unit 4, a hysteresis comparator 5, and a switch connected in sequence. A driving unit 6 and a switching amplifier stage 7. The envelope shaping unit 1 performs DC shift and peak clipping on the input envelope and then inputs it to the linear amplification stage 3 and the bias tracking unit. The bias tracking unit 2 feeds back the gate voltage of the class AB output NMOS transistor of the linear amplification stage 3 to the envelope shaping unit 1, and makes the envelope shaping unit 1 output a positive shift voltage. The linear amplification stage 3 includes a folded broadband operational amplifier OTA, a class AB output buffer, and a resistor feedback network. The class AB output buffer includes transistors M1 and M2. The linear amplification stage 3 performs linear amplification and shaping on the envelope signal through its resistance feedback network, and simultaneously compensates the ripple current generated by the switching amplifier stage 7 . The current sensing unit 4 detects the output current of the linear amplifier stage 3 ; this output current generates a voltage drop across the sensing resistor R _sen of the current sensing unit 4 , which is compared with the window voltage of the hysteresis comparator 5 . If the output voltage of the hysteresis comparator 5 is at a low level, M5 in the switching amplifier stage 7 is turned on and M6 is turned off. If the output voltage of the hysteresis comparator 5 is at a high level, M5 is turned off and M6 is turned on. The switch drive unit 6 is used to strengthen the output signal of the hysteresis comparator 5 to drive the switch amplifier stage 7 to work; the switch amplifier stage 7 is used to provide most of the current to the load, and the linear amplifier stage 3 provides the rest of the current.

Wherein, the input terminal of the envelope shaping unit 1 is connected to the envelope signal, and the output terminal thereof is connected to the input terminal of the offset tracking unit 2 . The gate voltage of the transistor M2 of the AB output Buffer is connected to the bias tracking unit 2 , and the output terminal of the bias tracking unit 2 is fed back to the envelope shaping unit 1 . The gate of the transistor M1 of the AB output Buffer is connected to the gate of the transistor M3 of the current sensing unit 4 , and the gate of the transistor M2 is connected to the gate of the transistor M4 of the current sensing unit 4 . The drains of the transistors M3 and M4 of the current sensing unit 4 and the positive terminal of the current sensing resistor R _sen are simultaneously connected to the positive input terminal of the hysteresis comparator 5 . The output terminal of the hysteresis comparator 5 is connected to the input terminal of the switch driving unit 6 . The output terminal of the switch drive unit 6 is connected to the input terminal of the switch amplifier stage 7 . The output terminal of the switching amplifier stage 7, the drains of the transistors M1 and M2, the negative terminal of the current sensing resistor R _sen and the negative input terminal of the hysteresis comparator 5 are simultaneously connected to the positive terminal of the load resistor R _load , and the load resistor R _load The positive terminal voltage of is used as the output signal of the envelope modulator.

The envelope shaping unit of the embodiment shown in Fig. 2 comprises transconductance stage, V-I conversion unit, bias feedback unit, current mirror M20, current mirror M21, current bias transistor M25 and current bias transistor M26; The output of the stage is connected to the input of the V-I conversion unit, and the output of the bias feedback unit is connected to the V-I conversion unit to change the magnitude of the current in the V-I conversion unit.

The transconductance stage shown in FIG. 2 includes input transistors M7, M8, M9 and M10, tail current source transistors M11 and M12, current mirror transistors M13, M14, M15, M16, M17, M18, and source negative feedback transistor M19. The VI conversion unit includes M22, M23, and M24. The bias feedback unit includes M23, M24, current mirror transistors M27, M28, and bias transistors M29, M30. The gate of M7 is connected to the input envelope signal V _env,i , the sources of M7 and M8 are connected to the drain of M11, the drain of M7 is connected to the drain of M16, the gate of M8 is connected to the gate of M9 and the drain of M8 The drain of M8 is connected to the drain of M9 and the drain of M19, the source of M9 and M10 is connected to the drain of M12, the drain of M10 is connected to the drain and gate of M17, and the gate of M10 is connected to the source of M22 , the gate of M11 and the gate of M12 are connected to the bias voltage VB1, the source of M11 and the source of M12 are connected to the power supply voltage, the sources of M13 and M14 are connected to the power supply voltage, and the gate of M13 is connected to the gate of M14 and M13 The drain of M13 is connected to the drain of M15, the drain of M14 is connected to the drain of M18, the gate of M15 is connected to the gate and drain of M16, the sources of M15 and M16 are grounded, and the gate of M18 is connected to The gate and drain of M17, the sources of M17 and M18 are grounded, the gate of M19 is connected to the bias voltage VB2, the source of M19 is grounded, the sources of M20 and M21 are grounded, the gate of M21 is connected to the gate of M20 and Drain, the drain of M20 is connected to the drain of M22, the drain of M21 is connected to the drain of M24, the gate of M22 is connected to the drain of M18, the source of M22 is connected to the drain and gate of M23, and the gate of M23 Connect to the gate of M24 and the drain of M27, the source of M23 to the drain of M25, the source of M24 to the drain of M26, the gates of M25 and M26 to the bias voltage VB1, the sources of M25 and M26 to Power supply voltage, the drain of M24 and M21 are connected to the output envelope signal V _env,o , the gate of M27 is connected to the gate and drain of M28, the sources of M27 and M28 are grounded, and the drain of M28 is connected to M29 The drain, the gate of M29 is connected to the voltage VP1, the source of M29 is connected to the drain of M30, the gate of M30 is connected to the voltage VP2, and the source of M30 is connected to the power supply voltage.

The transconductance stage amplifies the input envelope signal, where M1 and M4 improve the linearity of the circuit through source degeneration, and M16 acts as a source follower to drive the active load M17 at the same time, thereby realizing the conversion from voltage to current. M16 is a mirror image of the M15 current. The gate voltage bias of M19 and M20 is provided by the current source circuit, by using the bias information of VP1 and VP2, using M21, M22, M23 and M24 to generate a bias current between the currents of M17 and M18, and then get relative to An output envelope signal V _env,o with a positive bias voltage after shaping the input envelope signal V _env,i . The current on M21 is used to adjust the total current of the output branch, thereby changing the offset of V _env,o . Since VP1 and VP2 directly reflect the current and envelope voltage information output by the linear amplifier stage, it allows V _env,o to be relatively adjustable based on the conditions of the switching converter. After different DC voltage level shifts, the required voltage provided by the envelope modulator to the power amplifier can be satisfied.

The bias tracking unit of the embodiment shown in FIG. 3 includes transistors M31, M32, M33, filter resistor _RL and filter capacitor _CL . The gate of M31 is connected to the bias voltage Vn, the source of M31 is grounded, the drain of M31 is connected to the drain of M32 and the gate of M33, the source of M32 is connected to the drain of M33, the source of M33 is connected to the power supply voltage, and M32 The gate of RL is connected to _RL and _CL , the other end of _RL is connected to the envelope signal V _env,o , and the other end of _CL is grounded. The gate of M32 and the gate of M33 serve as VP1 and VP2 signals respectively, and VP1 and VP2 respectively correspond to the gate voltages of M29 and M30 in the envelope shaping circuit. Since the envelope peak voltage changes too sharply, a certain degree of low-pass filter is used as an auxiliary process to obtain an envelope signal with a slightly reduced bandwidth.

As shown in Figure 4, when the input signal is an LTE 16-QAM 10MHz signal, the simulated original envelope is the output envelope signal after passing through the envelope shaping unit. It can be seen that the bandwidth of the envelope signal is somewhat different from the original down, thereby saving power.

As shown in Figure 5, under the signal that the input signal is LTE 16-QAM 10MHz, the instantaneous current on the linear amplifier stage and the switch amplifier stage of the high-efficiency high-linearity envelope modulator based on an embodiment of the present invention obtained by simulation Consumption curve, through calculation, the average current consumed by the linear amplifier stage is 56mA, and the average current consumed by the switch amplifier stage is 78mA. When applied to different envelope tracking power amplifier systems, the efficiency of the entire system can be further calculated.

As shown in FIG. 6 , the output third-order intermodulation point OIP3 of the high-efficiency and high-linearity envelope modulator based on an embodiment of the present invention obtained by simulation under the LTE 16-QAM 10MHz signal with a center frequency of 1.8GHz is 53.06dBm.

In summary, the present invention uses the envelope signal as the input of the linear amplification stage after shaping, and the circuit of the bias tracking unit feeds back the gate voltage of the AB class output NMOS transistor of the linear amplification stage to the circuit of the envelope shaping unit and A positive shift voltage is generated at the output, thereby improving the linearity of the envelope tracking power amplifier system; at the same time, by performing a certain degree of DC shift and envelope peak clipping on the envelope signal, the power consumption of the overall circuit is saved. An envelope modulator with high efficiency and high linearity is realized.

Claims (5)

1. A high-efficiency high-linearity envelope modulator, characterized in that: It includes an envelope shaping unit (1), a bias tracking unit (2), a linear amplifier stage (3), a current sensing unit (4), a hysteresis comparator (5), a switch drive unit (6) and a switch amplifier connected in sequence level(7); An envelope shaping unit (1), which performs DC shift and peak clipping on the input envelope and then inputs it to the linear amplification stage and the bias tracking unit; The bias tracking unit (2) feeds back the gate voltage of the AB class output NMOS transistor of the linear amplifier stage to the envelope shaping unit (1), so that the envelope shaping unit (1) outputs a positive shift voltage; A linear amplification stage (3), comprising a folded broadband operational amplifier OTA, an AB class output Buffer, a resistor feedback network; the AB class output Buffer includes a first transistor M1 and a second transistor M2; the linear amplification stage (3 ), the envelope signal through its resistance feedback network is linearly amplified and shaped, and the ripple current generated by the switching amplifier stage (7) is compensated at the same time; The current sensing unit (4) detects the output current of the linear amplifier stage (3); the output current generates a voltage drop on the sense resistor R _sen of the current sensing unit (4), and the voltage drop is the same as that of the hysteresis comparator (5) The window voltages are compared, if the output voltage of the hysteresis comparator is a low level, the fifth transistor M5 in the switching amplifier stage (7) is turned on, and the sixth transistor M6 is turned off, and if the output voltage of the hysteresis comparator is a high level, the fifth transistor M5 is turned off. The transistor M5 is turned off, and the sixth transistor M6 is turned on; A switch drive unit (6), used to strengthen the output signal of the hysteresis comparator (5) to drive the switch amplifier stage (7) to work; The switch amplifier stage (7) is used to provide most of the current to the load, and the rest of the current is provided by the linear amplifier stage (3). 2. A kind of high-efficiency high-linearity envelope modulator according to claim 1, is characterized in that, the input terminal of described envelope shaping unit (1) is connected with envelope signal, and its output terminal is connected with bias tracking The input terminal of the unit (2); the gate voltage of the second transistor M2 of the AB class output Buffer is connected to the bias tracking unit (2); the output terminal of the bias tracking unit (2) is fed back to the envelope shaping unit (1); The gate of the first transistor M1 of the AB class output Buffer is connected to the gate of the third transistor M3 of the current sensing unit (4), and the gate of the second transistor M2 is connected to the gate of the fourth transistor M4 of the current sensing unit (4). Gate; The drain of the third transistor M3 and the fourth transistor M4 of the current sensing unit (4) and the positive terminal of the current sensing resistor R _sen are simultaneously connected to the positive input of the hysteresis comparator (5); the hysteresis comparator ( 5) the output terminal is connected to the input terminal of the switch drive unit (6); the output terminal of the switch drive unit (6) is connected to the input terminal of the switch amplifier stage (7); the output terminal of the switch amplifier stage (7), the first The drains of the transistor M1 and the second transistor M2, the negative terminal of the current sensing resistor R _sen and the negative input terminal of the hysteresis comparator (5) are simultaneously connected to the positive terminal of the load resistor R _load , the voltage of the positive terminal of the load resistor R _load as the output signal of the envelope modulator. 3. a kind of high efficiency high linearity envelope modulator according to claim 1, is characterized in that, described envelope shaping unit (1) comprises transconductance stage (8), V-I conversion unit (9), bias Set the feedback unit (10), the twentieth transistor M20, the twenty-first transistor M21, the twenty-fifth transistor M25 and the twenty-sixth transistor M26; the twentieth transistor M20 and the twenty-first transistor M21 are a pair of current mirror, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are current bias transistors; the output of the transconductance stage (8) is connected to the input of the V-I conversion unit (9), and the output of the bias feedback unit (10) is connected V-I conversion unit (9). 4. A high-efficiency high-linearity envelope modulator according to claim 3, characterized in that: said transconductance stage (8) comprises a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and The tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth Transistor M18, nineteenth transistor M19; The V-I conversion unit (9) includes a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24; The bias feedback unit (10) includes a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, and a thirtieth transistor M30; The gate of the seventh transistor M7 is connected to the input envelope signal V _env,i , the sources of the seventh transistor M7 and the eighth transistor M8 are connected to the drain of the eleventh transistor M11, and the drain of the seventh transistor M7 is connected to the sixteenth transistor M11. The drain of the transistor M16, the gate of the eighth transistor M8 is connected to the gate of the ninth transistor M9 and the drain of the eighth transistor M8, the drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9 and the nineteenth transistor The drain of M19, the sources of the ninth transistor M9 and the tenth transistor M10 are connected to the drain of the twelfth transistor M12, the drain of the tenth transistor M10 is connected to the drain and gate of the seventeenth transistor M17, and the tenth transistor The gate of M10 is connected to the source of the twenty-second transistor M22, the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 are connected to the bias voltage VB1, the source of the eleventh transistor M11 is connected to the twelfth transistor M12 The source of the transistor M12 is connected to the power supply voltage, the sources of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to the power supply voltage, the gate of the thirteenth transistor M13 is connected to the gate of the fourteenth transistor M14 and the thirteenth transistor M13 The drain of the thirteenth transistor M13 is connected to the drain of the fifteenth transistor M15, the drain of the fourteenth transistor M14 is connected to the drain of the eighteenth transistor M18, and the gate of the fifteenth transistor M15 is connected to the drain of the fifteenth transistor M15. The gate and drain of the sixteenth transistor M16, the sources of the fifteenth transistor M15 and the sixteenth transistor M16 are grounded, the gate of the eighteenth transistor M18 is connected to the gate and drain of the seventeenth transistor M17, the tenth The sources of the seventh transistor M17 and the eighteenth transistor M18 are grounded, the gate of the nineteenth transistor M19 is connected to the bias voltage VB2, the source of the nineteenth transistor M19 is grounded, the twentieth transistor M20 and the twenty-first transistor M21 The source of the twentieth transistor M21 is grounded, the gate of the twenty-first transistor M21 is connected to the gate and drain of the twentieth transistor M20, the drain of the twentieth transistor M20 is connected to the drain of the twenty-second transistor M22, the twenty-first The drain of the transistor M21 is connected to the drain of the twenty-fourth transistor M24, the gate of the twenty-second transistor M22 is connected to the drain of the eighteenth transistor M18, and the source of the twenty-second transistor M22 is connected to the twenty-third transistor The drain and gate of M23, the gate of the twenty-third transistor M23 is connected to the gate of the twenty-fourth transistor M24 and the drain of the twenty-seventh transistor M27, and the source of the twenty-third transistor M23 is connected to the second The drain of the fifteenth transistor M25, the source of the twenty-fourth transistor M24 is connected to the drain of the twenty-sixth transistor M26, the gates of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the bias voltage VB1, The sources of the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are connected to the power supply voltage, the drains of the twenty-fourth transistor M24 and the twenty-first transistor M21 are connected to the output envelope signal V _env,o , the second The gate of the twenty-seventh transistor M27 is connected to the gate and drain of the twenty-eighth transistor M28, the sources of the twenty-seventh transistor M27 and the twenty-eighth transistor M28 are grounded, and the twenty-eighth transistor M28 is grounded. The drain of the transistor M28 is connected to the drain of the twenty-ninth transistor M29, the gate of the twenty-ninth transistor M29 is connected to the voltage VP1, the source of the twenty-ninth transistor M29 is connected to the drain of the thirtieth transistor M30, and the third The gate of the tenth transistor M30 is connected to the voltage VP2, and the source of the thirtieth transistor M30 is connected to the power supply voltage. 5. A high-efficiency and high-linearity envelope modulator according to claim 1, characterized in that: the bias tracking unit (2) comprises a thirty-first transistor M31, a thirty-second transistor M32, a Thirty-three transistor M33, filter resistor R _L and filter capacitor C _L ; the gate of the thirty-first transistor M31 is connected to the bias voltage Vn, the source of the thirty-first transistor M31 is grounded, and the drain of the thirty-first transistor M31 connected to the drain of the thirty-second transistor M32 and the gate of the thirty-third transistor M33, the source of the thirty-second transistor M32 is connected to the drain of the thirty-third transistor M33, and the source of the thirty-third transistor M33 The pole is connected to the power supply voltage, the gate of the thirty-second transistor M32 is connected to the filter resistor _RL and the filter capacitor C _L , the other end of the filter resistor _RL is connected to the envelope signal V _env,o , and the other end of the filter capacitor C _L is grounded.