CN108666417B - Memory device including variable resistance material layer - Google Patents

Memory device including variable resistance material layer Download PDF

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CN108666417B
CN108666417B CN201810257802.9A CN201810257802A CN108666417B CN 108666417 B CN108666417 B CN 108666417B CN 201810257802 A CN201810257802 A CN 201810257802A CN 108666417 B CN108666417 B CN 108666417B
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ltoreq
layer
ranges
memory device
electrode lines
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CN108666417A (en
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安东浩
吴哲
朴淳五
堀井秀树
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Samsung Electronics Co Ltd
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    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
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    • G—PHYSICS
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    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
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    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
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    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
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    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method

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Abstract

A memory device is provided. The memory device includes a variable resistance layer. The selection device layer is electrically connected to the variable resistance layer. The select device layer includes a chalcogenide switching material, [ Ge ] having a composition according to the following chemical formula 1ASeBTeC](1‑U)[X]U0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C.ltoreq.1, 0.0. ltoreq. U.ltoreq.0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).

Description

Memory device including variable resistance material layer
Technical Field
Exemplary embodiments of the inventive concepts relate to a memory device, and more particularly, to a memory device including a variable resistance material layer.
Background
As electronic equipment becomes lighter, thinner, shorter, and smaller, the demand for more highly integrated semiconductor devices has increased. A three-dimensional (3D) memory device may include a variable resistance material layer and a selection device layer. The 3D memory device may have a cross-point structure. A select device layer for a 3D memory device may include a memory device comprising a chalcogenide material exhibiting Ovonic Threshold Switching (OTS) characteristics.
Disclosure of Invention
According to example embodiments of the inventive concepts, a memory device may have a low off-current and may be relatively reliable.
According to an exemplary embodiment of the inventive concept, a memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The select device layer includes a chalcogenide switching material having a composition according to the following chemical formula 1,
[GeASeBTeC](1-U)[X]U·····················(1)
wherein 0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C1, 0.0. ltoreq. U.ltoreq.0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
According to an exemplary embodiment of the inventive concept, a memory device includes a plurality of first electrode lines located above a substrate and extending in a first direction parallel to an upper surface of the substrate. A plurality of second electrode lines are positioned above the plurality of first electrode lines and extend in a second direction parallel to the upper surface of the substrate and crossing the first direction. A plurality of third electrode lines are positioned above the plurality of second electrode lines and extend in the first direction. A plurality of memory cells are formed at points where the plurality of first electrode lines and the plurality of second electrode lines cross each other and at points where the plurality of second electrode lines and the plurality of third electrode lines cross each other, respectively. Each of the plurality of memory cells includes a selection device layer and a variable resistance layer. The select device layer includes a chalcogenide switching material having a composition according to chemical formula 1.
Each of the plurality of memory cells includes a selection device layer and a variable resistance layer. The select device layer includes a chalcogenide switching material having a composition according to the following chemical formula 1,
[GeASeBTeC](1-U)[X]U·····················(1)
wherein 0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C1, 0.0. ltoreq. U.ltoreq.0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
According to an exemplary embodiment of the inventive concept, a memory device includes a variable resistance layer including a chalcogenide memory material. The selection device layer is electrically connected to the variable resistance layer and includes a chalcogenide switching material having a composition according to chemical formula 1 or the following chemical formula 2,
[GeASeBTeCAsD](1-U)[X]U··················(2)
wherein 0.20. ltoreq. A.ltoreq.0.35, 0.45. ltoreq. B.ltoreq.0.65, 0.04. ltoreq. C.ltoreq.0.18, 0.0. ltoreq. D.ltoreq.0.18, A + B + C + D1, 0.0. ltoreq. U.ltoreq.0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
Drawings
The above and further features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is an equivalent circuit diagram of a memory device according to an exemplary embodiment of the inventive concept;
FIG. 2 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;
FIG. 3 is a cross-sectional view taken along lines 1X-1X 'and 1Y-1Y' of FIG. 2;
FIG. 4 is a graph schematically illustrating a voltage-current curve for a select device layer having a bi-directional threshold switching characteristic;
fig. 5 is a ternary phase diagram illustrating a composition range of a chalcogenide switching material according to an exemplary embodiment of the inventive concept;
fig. 6A to 6C are graphs illustrating characteristics of a memory device including a chalcogenide switching material according to an exemplary embodiment of the inventive concept;
fig. 7 to 10 are each a cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept;
fig. 11 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;
FIG. 12 is a cross-sectional view taken along lines 2X-2X 'and 2Y-2Y' of FIG. 11;
fig. 13 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;
FIG. 14 is a cross-sectional view taken along lines 3X-3X 'and 3Y-3Y' of FIG. 13;
fig. 15 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;
FIG. 16 is a cross-sectional view taken along line 4X-4X' of FIG. 15; and
fig. 17 to 19 are cross-sectional views illustrating a process of manufacturing the memory device of fig. 2 according to an exemplary embodiment of the inventive concept.
Detailed Description
Fig. 1 is an equivalent circuit diagram of a memory device according to an exemplary embodiment of the inventive concept.
Referring to fig. 1, a memory device 100 may include word lines WL1 and WL2 extending along a first direction (e.g., an X direction) and spaced apart from each other in a second direction (e.g., a Y direction) perpendicular to the first direction. The memory device 100 may include bit lines BL1, BL2, BL3, and BL4 spaced apart from word lines WL1 and WL2 in a third direction (e.g., Z direction) orthogonal to the first and second directions. The bit lines BL1, BL2, BL3, and BL4 may extend along the second direction.
The memory cells MC may be arranged between bit lines BL1, BL2, BL3, and BL4 and word lines WL1 and WL2, respectively. As an example, the memory cells MC may be arranged at intersections between the bit lines BL1, BL2, BL3, and BL4 and the word lines WL1 and WL2, and may each include a variable resistance layer ME for storing information and a selection device layer SW for selecting a memory cell. The select device layer SW may be referred to as a switching device layer or an access device layer.
The memory cells MC may be arranged in the third direction and may be identical to each other in structure. For example, in the memory cell MC arranged between the word line WL1 and the bit line BL1, the selection device layer SW may be electrically connected to the word line WL1, the variable resistance layer ME may be electrically connected to the bit line BL1, and the variable resistance layer ME and the selection device layer SW may be connected in series to each other.
However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the positions of the selection device layer SW and the variable resistance layer ME may be exchanged in the memory cell MC. For example, in the memory cell MC, the variable resistance layer ME may be connected to the word line WL1, and the selection device layer SW may be connected to the bit line BL 1.
A method of driving the memory device 100 will be described in more detail below. A voltage may be applied to the variable-resistance layer ME in the memory cell MC via the word line WL1 or WL2 and the bit line BL1, BL2, BL3, or BL4 so that a current may flow through the variable-resistance layer ME. For example, the variable resistance layer ME may include a phase change material layer that is reversibly convertible between a first phase and a second phase. However, the variable resistance layer ME is not limited thereto. For example, the variable resistance layer ME may include any type of variable resistor having a resistance value that varies depending on an applied voltage. For example, in the selected memory cell MC, the resistance of the variable-resistance layer ME may be reversibly switched between the first phase and the second phase according to the voltage applied to the variable-resistance layer ME.
The memory cell MC may store digital information represented as "0" or "1" or may erase the digital information from the memory cell MC according to a resistance change of the variable resistance layer ME. For example, data may be written in the memory cell MC in a high resistance state "0" and a low resistance state "1". Writing of data from the high resistance state "0" to the low resistance state "1" may be referred to as a "set operation", and writing of data from the low resistance state "1" to the high resistance state "0" may be referred to as a "reset operation". However, the memory cell MC according to the exemplary embodiment of the inventive concept is not limited to the digital information of the high resistance state "0" and the low resistance state "1" as described above, but may store various resistance states.
The memory cell MC may be addressed by selecting word lines WL1 and WL2 and bit lines BL1, BL2, BL3, and BL4, and the memory cell MC may be programmed by applying a predetermined signal between the word lines WL1 and WL2 and the bit lines BL1, BL2, BL3, and BL 4. The current value may be measured via the bit lines BL1, BL2, BL3, and BL4 to read information such as program information according to the resistance value of the variable resistance layer in the corresponding memory cell MC.
Fig. 2 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 3 is a cross-sectional view taken along lines 1X-1X 'and 1Y-1Y' of FIG. 2.
Referring to fig. 2 and 3, the memory device 100 may include a first electrode line layer 110L, a second electrode line layer 120L, and a memory cell layer MCL on a substrate 101.
An insulating interlayer 105 may be disposed on the substrate 101. The insulating interlayer 105 may include a silicon oxide material or a silicon nitride material, and may electrically separate the first electrode line layer 110L from the substrate 101. In the memory device 100 according to an exemplary embodiment of the inventive concept, the insulating interlayer 105 is disposed on the substrate 101; however, the exemplary embodiments of the inventive concept are not limited thereto. For example, in the memory device 100 according to an exemplary embodiment of the inventive concept, an integrated circuit layer may be disposed on the substrate 101, and a memory cell may be disposed on the integrated circuit layer. The integrated circuit layer may include, for example, peripheral circuitry for driving the memory cells and/or core circuitry for performing operations. A structure in which an integrated circuit layer including a peripheral circuit and/or a core circuit is disposed on a substrate and a memory cell is located above the integrated circuit layer may be referred to as a Cell On Periphery (COP) structure.
The first electrode line layer 110L may include a plurality of first electrode lines 110 extending parallel to each other along a first direction (e.g., an X direction). The second electrode lines 120L may include a plurality of second electrode lines 120 extending parallel to each other in a second direction (e.g., Y direction) crossing the first direction. The first direction and the second direction may be perpendicular to each other.
Referring to the driving of the memory device 100, the first electrode lines 110 may be in positions corresponding to word lines WL (see, e.g., fig. 1), and the second electrode lines 120 may be in positions corresponding to bit lines BL (see, e.g., fig. 1). According to an exemplary embodiment of the inventive concept, the first electrode lines 110 may be in positions corresponding to bit lines, and the second electrode lines 120 may be in positions corresponding to word lines.
The first electrode lines 110 and the second electrode lines 120 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode lines 110 and the second electrode lines 120 may each include W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, Indium Tin Oxide (ITO), alloys thereof, or combinations thereof. Further, the first electrode lines 110 and the second electrode lines 120 may each include a metal layer and a conductive barrier layer at least partially covering the metal layer. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.
The memory cell layer MCL may include a plurality of memory cells 140 (see, e.g., MC of fig. 1) spaced apart from each other in a first direction and a second direction. Referring to fig. 2 and 3, the first electrode lines 110 and the second electrode lines 120 may cross each other (e.g., may be perpendicular to each other). The memory cells 140 may be located between the first electrode line layer 110L and the second electrode line layer 120L where the first electrode lines 110 and the second electrode lines 120 cross each other.
Storage units 140 may each have a cubic pillar structure; however, the exemplary embodiments of the inventive concept are not limited thereto. For example, the storage units 140 may each have various types of column shapes, such as a cylindrical column, an elliptic column, and a polygonal column. The memory cells 140 may each have a structure in which a lower portion is wider than an upper portion, or a structure in which an upper portion is wider than a lower portion. As an example, when the memory cells 140 may be formed by performing an etching process, a lower portion of each memory cell 140 may be wider than an upper portion thereof. As an example, the memory cells 140 may be formed by performing a damascene process, and thus an upper portion of each memory cell 140 may be wider than a lower portion thereof. During the etching process or the damascene process, the etching may be precisely controlled so that the material layer may be etched to have almost vertical side surfaces, and the upper and lower portions are almost the same as each other in width. Referring to, for example, fig. 2 and 3, the memory cell 140 may have vertical side surfaces; however, the exemplary embodiments of the inventive concept are not limited thereto. For example, the memory cells 140 may each have a structure in which a lower portion is wider than an upper portion or an upper portion is wider than a lower portion.
Each of the memory cells 140 may include a lower electrode layer 141, a selection device layer 143, an intermediate electrode layer 145, a heating electrode layer 147, a variable resistance layer 149, and an upper electrode layer 148. Regardless of the positions of the above layers, the lower electrode layer 141 may be referred to as a first electrode layer, the middle electrode layer 145 and the heating electrode layer 147 may be referred to as a second electrode layer, and the upper electrode layer 148 may be referred to as a third electrode layer.
In an exemplary embodiment of the inventive concept, the variable resistance layer 149 (see, e.g., ME of fig. 1) may include a phase change material reversibly changeable between an amorphous state and a crystalline state. For example, the variable resistance layer 149 may include a material whose phase can be reversibly changed due to joule heat generated by a voltage applied to opposite ends of the variable resistance layer 149 and whose resistance changes depending on the phase change. As an example, a phase change material may be in a high resistance state when it is in an amorphous phase and a low resistance state when it is in a crystalline phase. By defining the high resistance state as "0" and the low resistance state as "1", data can be stored in the variable resistance layer 149.
In an exemplary embodiment of the inventive concept, the variable resistance layer 149 may include a chalcogenide material as a phase change material. For example, the variable resistance layer 149 may include Ge-Sb-Te (GST). Here, the chemical composition expression having a hyphen (-) may represent an element included in a certain mixture or compound, and may represent any kind of chemical formula structure including the expressed element. For example, Ge-Sb-Te may include Ge2Sb2Te5、Ge2Sb2Te7、Ge1Sb2Te4Or Ge1Sb4Te7。
In addition to the above-described Ge-Sb-te (gst), the variable resistance layer 149 may include various chalcogenide materials. For example, the variable resistance layer 149 may include at least two selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), or selenium (Se), or a combination thereof, as a chalcogenide material.
Each element included in the variable resistance layer 149 may have various stoichiometric ratios. The crystallization temperature, melting point, phase shift speed according to crystallization energy, and data retention of the variable resistance layer 149 may be adjusted according to the stoichiometry of each element. In an exemplary embodiment of the inventive concept, the melting point of the chalcogenide material included in the variable resistance layer 149 may be from about 500 ℃ to about 800 ℃.
The variable resistance layer 149 may further include at least one impurity selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S). The driving current of the memory device 100 may vary depending on impurities. The variable resistance layer 149 may also include a metal. For example, the variable resistance layer 149 may include at least one selected from aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), or polonium (Po). Such a metal material can increase the electrical conductivity and thermal conductivity of the variable-resistance layer 149, thereby increasing the crystallization speed and the set speed. In addition, the metal material may improve data retention characteristics of the variable resistance layer 149.
The variable resistance layer 149 may have a multi-layer structure in which two or more layers having different physical properties from each other are stacked. The number of layers or thickness of each layer may be selected as desired. A barrier layer may further be formed between the layers. The barrier layer may prevent diffusion of materials between the layers. For example, the barrier layer may reduce diffusion of a previous layer between the plurality of layers when a next layer is formed.
The variable resistance layer 149 may have a superlattice structure in which a plurality of layers including different materials from each other are alternately stacked. For example, the variable resistance layer 149 may have a structure in which first layers including Ge — Te and second layers including Sb — Te are alternately stacked. However, the first layer and the second layer are not limited thereto, and the first layer and the second layer may include various kinds of the above-described materials.
In the above description, the phase change material is exemplarily provided as the variable resistance layer 149, but exemplary embodiments of the inventive concept are not limited thereto. The variable resistance layer 149 of the memory device 100 may include various materials having variable resistance characteristics.
In an exemplary embodiment of the inventive concept, if the variable resistance layer 149 includes a transition metal oxide, the memory device 100 may be a resistive random access memory (ReRAM). In the variable resistance layer 149 including the transition metal oxide, at least one electrical path may be generated or extinguished through a programming operation. The variable resistance layer 149 may have a low resistance value when the electrical path is generated, and the variable resistance layer 149 may have a high resistance value when the electrical path is extinguished. The memory device 100 may store data by using such a difference between the resistance values of the variable resistance layer 149.
When the variable resistance layer 149 includes a transition metal oxide, the transition metal oxide may include at least one metal selected from Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, or Cr. For example, the transition metal oxide may have a composition comprising Ta2O5-x、ZrO2-x、TiO2-x、HfO2-x、MnO2-x、Y2O3-x、NiO1-y、Nb2O5-x、CuO1-yOr Fe2O3-xA single-layer structure or a multi-layer structure of at least one selected from (a). In the above example, x and y may be selected within a range of 0. ltoreq. x.ltoreq.1.5 or 0. ltoreq. y.ltoreq.0.5, respectively; however, the exemplary embodiments of the inventive concept are not limited thereto.
In an exemplary embodiment of the inventive concept, when the variable resistance layer 149 has a magnetic tunnel junction (MRJ) structure including two electrodes formed of a magnetic material and a dielectric material between the two electrodes of the magnetic material, the memory device 100 may be a magnetic ram (mram).
The two electrodes may be a pinned magnetization layer and a free magnetization layer, respectively, and the dielectric material between the two electrodes may be a tunnel barrier layer. The pinned magnetization layer has a magnetization direction fixed in a certain direction, and the free magnetization layer has a magnetization direction parallel or antiparallel to the magnetization direction of the pinned magnetization layer. The magnetization directions of the pinned magnetization layer and the free magnetization layer may be parallel to the surface of the tunnel barrier layer. Alternatively, the magnetization directions of the pinned magnetization layer and the free magnetization layer may be perpendicular to the surface of the tunnel barrier layer.
In the case where the magnetization direction of the free magnetization layer is parallel to the magnetization direction of the pinned magnetization layer, the variable resistance layer 149 may have a first resistance value. In the case where the magnetization direction of the free magnetization layer is antiparallel to the magnetization direction of the pinned magnetization layer, the variable resistance layer 149 may have a second resistance value. The memory device 100 may store data by using a change in resistance value. The magnetization direction of the free magnetization layer can be changed by the spin torque of electrons in the programming current.
The pinned magnetization layer and the free magnetization layer may have a magnetic material. The pinned magnetization layer may further include an antiferromagnetic material for fixing a magnetization direction of the ferromagnetic material in the pinned magnetization layer. The tunnel barrier layer may include an oxide material of any one selected from Mg, Ti, Al, MgZn, and MgB, but is not limited thereto.
Select device layer 143 (e.g., SW of fig. 1) may be a current regulation layer that may control the flow of current. Select device layer 143 may include a layer of material whose resistance may vary depending on the magnitude of a voltage applied to opposite ends of select device layer 143. For example, select device layer 143 may include an Ovonic Threshold Switch (OTS) material. The function of the select device layer 143 based on the OTS material will be described in more detail below. As an example, when less than the threshold voltage VTWhen a voltage of (2) is applied to the selection device layer 143, the selection device layer 143 is maintained in a high resistance state, and thus a current flows through the selection device layer 143 very little. When a voltage greater than the threshold voltage VT is applied to the selection device layer 143, the selection device layer 143 enters a low resistance state and current starts to flow. When the current flowing through the selection device layer 143 is less than the holding current, the selection device layer 143 may transition to a high resistance state. The ovonic threshold switching characteristics of select device layer 143 will be described in greater detail below with reference to fig. 4.
Select device layer 143 may include a chalcogenide switching material as the OTS material. In an exemplary embodiment of the inventive concept, the selection device layer 143 may include a ternary chalcogenide switching material including Ge, Se, and Te, and optionally, the ternary chalcogenide switching material may further include an additive element (X). For example, the selection device layer 143 may include a chalcogenide switching material having a composition according to the following chemical formula 1.
[GeASeBTeC](1-U)[X]U·····················(1)
(wherein 0.20. ltoreq. A. ltoreq.0.40, 0.40. ltoreq. B. ltoreq.0.70, 0.05. ltoreq. C. ltoreq.0.25, A + B + C. ltoreq.1, 0.0. ltoreq. U. ltoreq.0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S)).
In an exemplary embodiment of the inventive concept, the ternary chalcogenide switching material may include Ge in an amount of about 20 atomic percent (at%) to about 40 at% (e.g., a may be about 0.20 to about 0.40 in chemical formula 1 above). With GeASeBTeCThe constituent chalcogenide switching materials may be referred to as ternary chalcogenide switching materials. For example, the chalcogenide switching material having a composition according to chemical formula 1 may further include an additive element (X) in addition to the ternary chalcogenide switching material. In some examples, the ternary chalcogenide switching material may include Ge in an amount from about 25 at% to about 35 at% (e.g., a may be from about 0.25 to about 0.35 in chemical formula 1 above).
When Ge is included in the chalcogenide switching material, thermal stability of the chalcogenide switching material may be improved and stable switching characteristics may be exhibited. When the ternary chalcogenide switching material includes an amount of Ge that is less than about 20 at%, the thermal stability of the chalcogenide switching material may be relatively low. For example, when the ternary chalcogenide switching material includes an amount of Ge of less than about 20 at%, the ternary chalcogenide switching material may have a low volatilization temperature equal to or less than about 150 ℃, and thus the thermal stability may not be sufficiently high for use in a memory device having a cross-point structure. When the ternary chalcogenide switching material includes Ge in an amount greater than about 40 at%, the chalcogenide switching material may not exhibit stable switching characteristics. For example, when the ternary chalcogenide switching material includes Ge in an amount greater than about 40 at%, the crystallization temperature of the chalcogenide switching material is lowered, and thus the leakage current of the chalcogenide switching material may increase or the switching may not be turned off, and thus the chalcogenide switching material may not exhibit stable switching characteristics.
In an exemplary embodiment of the inventive concept, the ternary chalcogenide switching material may include Se in an amount of about 40 at% to about 70 at% (e.g., B may be about 0.40 to about 0.70 in chemical formula 1 above). In an exemplary embodiment of the inventive concept, the ternary chalcogenide switching material may include Se in an amount of about 45 at% to about 65 at% (e.g., B may be about 0.45 to about 0.65 in chemical formula 1 above). When a predetermined amount of Se is included in the chalcogenide switching material, the leakage current (or off-current) of the chalcogenide switching material may be reduced. For example, when the ternary chalcogenide switching material includes Se in an amount greater than about 40 at%, the off-current of the chalcogenide switching material may be reduced. When the ternary chalcogenide switching material includes Se in an amount exceeding about 70 at%, the content of Ge that may be included in the ternary chalcogenide switching material to achieve stable switching characteristics may be reduced, and thus the thermal stability of the chalcogenide switching material may be lowered.
In an exemplary embodiment of the inventive concept, the ternary chalcogenide switching material may include Te in an amount of about 5 at% to about 25 at% (e.g., C may be about 0.05 to about 0.25 in chemical formula 1 above). In an exemplary embodiment of the inventive concept, the ternary chalcogenide switching material may include Te in an amount of about 10 at% to about 20 at% (e.g., C may be about 0.10 to about 0.20 in chemical formula 1 above). When a predetermined amount of Te is included in the chalcogenide switching material, the durability of the chalcogenide switching material may be increased and stable switching characteristics may be exhibited. For example, when the ternary chalcogenide switching material includes Te in an amount greater than about 5 at%, the durability of the chalcogenide switching material may be increased. When the ternary chalcogenide switching material includes Te in an amount exceeding about 25 at%, the leakage current of the chalcogenide switching material may increase or the switch may not be turned off, and thus the chalcogenide switching material may not exhibit stable switching characteristics.
The ternary chalcogenide switching material according to an exemplary embodiment of the inventive concept may not include Si. When the chalcogenide switching material includes Si, it may be difficult to form the select device layer 143 with a relatively high film quality. For example, to form select device layer 143, the chalcogenide switching material may be sintered to form a target, and a film comprising the chalcogenide switching material may be formed from the target on the substrate by impingement of argon gas using a Physical Vapor Deposition (PVD) process, for example. However, when the chalcogenide switching material includes Si, silicon particles may be coalesced and separated in the target during a target forming process, or pores may be formed in the target, and thus silicon particles in the selection device layer 143 may be coalesced and separated. Therefore, the selection device layer 143 may have an uneven composition distribution and/or an uneven thickness, and the film quality of the selection device layer 143 may be deteriorated. However, the ternary chalcogenide switching material according to an exemplary embodiment of the inventive concept may not include Si, and thus a relatively high-quality target may be formed, and the selection device layer 143 formed using the target may have a relatively high film quality.
The ternary chalcogenide switching material according to an exemplary embodiment of the inventive concept may not include Sb. When the chalcogenide switching material includes Sb, the crystallization temperature of the chalcogenide switching material may be lowered. Accordingly, the chalcogenide switching material may be deteriorated in thermal stability, and the chalcogenide switching material may be damaged or deteriorated in a process for manufacturing a memory device having a cross-point structure by using the chalcogenide switching material. However, the ternary chalcogenide switching material according to an exemplary embodiment of the inventive concept may not include Sb, and the ternary chalcogenide switching material may have relatively high thermal stability.
In an exemplary embodiment of the inventive concept, the chalcogenide switching material may further include an additive element (X) in an amount of about 0 at% to about 20 at% as shown in chemical formula 1 above (e.g., U may be about 0.0 to about 0.2 in chemical formula 1 above). In an exemplary embodiment of the inventive concept, the chalcogenide switching material may further include B as the additive element (X) in an amount of about 0.1 at% to about 20 at%, may further include C as the additive element (X) in an amount of about 0.1 at% to about 10 at%, may further include N as the additive element (X) in an amount of about 8 at% to about 20 at%, may further include P as the additive element (X) in an amount of about 0.1 at% to about 8 at%, or may further include S as the additive element (X) in an amount of about 0.1 at% to about 8 at%. When the chalcogenide switching material includes the additive element (X), the content of each of Ge, Se, or Te in the chalcogenide switching material may be reduced according to the amount of the additive element (X).
In an exemplary embodiment of the inventive concept, the selection device layer 143 may include a chalcogenide switching material including Ge, Se, or Te and further including arsenic (As). For example, the selection device layer 143 may include a chalcogenide switching material having a composition according to the following chemical formula 2.
[GeASeBTeCAsD](1-U)[X]U·················(2)
(wherein 0.20. ltoreq. A.ltoreq.0.35, 0.45. ltoreq. B.ltoreq.0.65, 0.04. ltoreq. C.ltoreq.0.18, 0.0. ltoreq. D.ltoreq.0.18, A + B + C + D. 1, 0.0. ltoreq. U.ltoreq.0.20, and X is at least one selected from B, C, N, O, P or S.)
In an exemplary embodiment of the inventive concept, for example, As shown in chemical formula 2, the chalcogenide switching material may include As in an amount of about 0 at% to about 18 at% (e.g., D may be about 0.0 to about 0.18 in chemical formula 2). In an exemplary embodiment of the inventive concept, the chalcogenide switching material may include Ge in an amount of about 20 at% to about 30 at%, Se in an amount of about 45 at% to about 60 at%, Te in an amount of about 4 at% to about 18 at%, and As in an amount of about 4 at% to about 18 at% (e.g., in chemical formula 2, a may be about 0.20 to about 0.30, B may be about 0.45 to about 0.60, C may be about 0.04 to about 0.18, and D may be about 0.04 to about 0.18).
The inclusion of As in the chalcogenide switching material may improve the thermal stability of the chalcogenide switching material. For example, As may increase the volatilization temperature and/or crystallization temperature of the chalcogenide switching material and thus may increase the thermal stability of select device layer 143 comprising the chalcogenide switching material. For example, the chalcogenide switching material may have a relatively high volatilization temperature and a relatively high crystallization temperature, and thus damage to the chalcogenide switching material or degradation of the chalcogenide switching material may be prevented during a process of manufacturing a memory device having a cross-point structure by using the chalcogenide switching material. Further, the leakage current characteristics and thermal stability of the chalcogenide switching material according to an exemplary embodiment of the inventive concept will be described in more detail below with reference to fig. 6A to 6C.
Select device layer 143 may include a chalcogenide switching material having a composition according to chemical formula 1 or 2 above. Because the chalcogenide switching material does not include Si, the chalcogenide switching material may have a relatively high film quality. In addition, the chalcogenide switching material may have stable switching characteristics, low off-current, relatively high thermal stability, and relatively high durability.
The heating electrode layer 147 may be disposed between the intermediate electrode layer 145 and the variable resistance layer 149, and may be in direct contact with the variable resistance layer 149. The heating electrode layer 147 may heat the variable resistance layer 149 during a set or reset operation. The heating electrode layer 147 may include a conductive material that may generate heat sufficient to cause a phase change of the variable resistance layer 149 without reacting with the variable resistance layer 149. The heating electrode layer 149 may include a carbon-based conductive material. In an exemplary embodiment of the inventive concept, the heating electrode layer 147 may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, tiaon, TiAlON, WON, TaON, C, silicon carbide (SiC), silicon carbonitride (SiCN), Carbonitride (CN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), a refractory metal combination, or a nitride thereof. However, the heating electrode layer 147 is not limited to the above example.
The lower electrode layer 141, the middle electrode layer 145, and the upper electrode layer 148 may serve as a current path, and may include a conductive material. For example, the lower electrode layer 141, the middle electrode layer 145, and the upper electrode layer 148 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the lower electrode layer 141, the middle electrode layer 145, and the upper electrode layer 148 may each include at least one selected from C, TiN, TiSiN, TiCN, TiCSiN, TiAlN, Ta, TaN, W, or WN; however, the exemplary embodiments of the inventive concept are not limited thereto.
The lower electrode layer 141 and the upper electrode layer 148 may be optionally formed. As an example, the lower electrode layer 141 and the upper electrode layer 148 may be omitted. However, in order to prevent contamination or poor contact that may be caused when the selection device layer 143 and the variable resistance layer 149 directly contact the first electrode lines 110 and the second electrode lines 120, the lower electrode layer 141 and the upper electrode layer 148 may be located between the first electrode lines 110 and the second electrode lines 120 and the selection device layer 143 and the variable resistance layer 149.
The intermediate electrode layer 145 may prevent heat transfer from the heating electrode layer 147 to the selection device layer 143. As an example, select device layer 143 may include a chalcogenide switching material in an amorphous state. However, according to the scaling-down trend of the memory device 100, the thickness and width of each of the variable resistance layer 149, the selection device layer 143, the heating electrode layer 147 and the intermediate electrode layer 145 and the distance therebetween may be reduced. Therefore, when the heating electrode layer 147 generates heat to cause a phase change of the variable resistance layer 149 while the memory device 100 is driven, the selection device layer 143 disposed adjacent to the heating electrode layer 147 may be thermally affected. For example, the selection device layer 143 may be partially crystallized by heat from the adjacent heating electrode layer 147, and thus the selection device layer 143 may be deteriorated or damaged. In an exemplary embodiment of the inventive concept, the intermediate electrode layer 145 may be relatively thick so as not to transfer heat from the heating electrode layer 147 to the selection device layer 143. Referring to fig. 2 and 3, the middle electrode layer 145 may have a thickness similar to that of the lower electrode layer 141 or the upper electrode layer 148, but the thickness of the middle electrode layer 145 may be greater than that of the lower electrode layer 141 or the upper electrode layer 148 for facilitating a thermal blocking operation. For example, the intermediate electrode layer 145 may have a thickness of about 10nm to about 100 nm; however, the exemplary embodiments of the inventive concept are not limited thereto.
In an exemplary embodiment of the inventive concept, the intermediate electrode layer 145 may include at least one thermal barrier layer for a thermal barrier function. When the intermediate electrode layer 145 includes two or more thermal barrier layers, the intermediate electrode layer 145 may have a structure in which the thermal barrier layers and the electrode material layers are alternately stacked.
The first insulating layer 160a may be positioned between the adjacent first electrode lines 110, and the second insulating layer 160b may be positioned between the adjacent memory cells 140 of the memory cell layer MCL. In addition, the third insulating layer 160c may be positioned between the adjacent second electrode lines 120. The first to third insulating layers 160a to 160c may be insulating layers including the same material as each other, or at least one of the first to third insulating layers 160a to 160c may include a material different from that of the other first to third insulating layers 160a to 160 c. The first to third insulating layers 160a to 160c may each include a dielectric material such as an oxide material or a nitride material, and may electrically isolate devices from each other in each layer. An air gap may be formed instead of the second insulating layer 160 b. When the air gap is formed, an insulating spacer having a predetermined thickness may be formed between the air gap and the memory cell 140.
As an example, in a memory device using a chalcogenide material as a select device, the chalcogenide material may have a relatively low crystallization temperature, and thus a general process for manufacturing the memory device may not be performed, and it may be difficult to manufacture the memory device having a three-dimensional (3D) cross-point stack structure. Because chalcogenide materials have a relatively large off current, the number of memory cells that operate at one time is reduced and endurance may be relatively low. However, the memory device 100 according to an exemplary embodiment of the inventive concept may include the selection device layer 143 including the chalcogenide switching material having the composition according to chemical formula 1 or 2, and the chalcogenide switching material may exhibit stable switching characteristics, a low off-current, a relatively high thermal stability, and a relatively high endurance. Accordingly, the memory device 100 may have a 3D cross-point stack structure having relatively high reliability.
Fig. 4 is a graph schematically illustrating a voltage-current curve of a select device layer having an ovonic threshold switch characteristic.
Referring to fig. 4, a first curve 61 represents a voltage-current relationship in a state where current does not flow through the selection device layer 143 (see, e.g., fig. 3). Here, select device layer 143 may function as threshold voltage V having first voltage level 63TThe switching device of (1). When the voltage is gradually increased from the state where the voltage and current are 0, the current may flow on the selection device layer 143 very little until the voltage reaches the threshold voltage VTI.e. the first voltage level 63. However, once the voltage exceeds the threshold voltage VTThe current flowing on the selection device layer 143 may be greatly increased, and the voltage applied to the selection device layer 143 may be reduced to the saturation voltage VS(i.e., second voltage level 64).
A second curve 62 represents the voltage-current relationship in a state where current flows in the selection device layer 143. When the current flowing in select device layer 143 is greater than first current level 66, the voltage applied to select device layer 143 may be slightly increased to be greater than second voltage level 64. For example, when the current flowing in select device layer 143 increases from first current level 66 to second current level 67, the voltage applied to select device layer 143 may slightly increase from second voltage level 64. That is, once a current flows through the selection device layer 143, a voltage applied to the selection device layer 143 may be mainly maintained at a saturation voltage VSTo (3). If the current decreases to the holding current level (e.g., first current level 66) or lower, select device layer 143 switches to a resistor state to effectively block current until the voltage increases to threshold voltage VT。
Referring to fig. 4, when the memory device is in an off state (e.g., less than a threshold voltage V)TA predetermined voltage is applied), a small amount of current can flow. Since the leakage current in the off state becomes larger, the number of memory cells that can be operated at one time decreases, and stable switching characteristics may not be obtained, so that it may be difficult to realize a memory device having a 3D cross-point structure. However, the selection device according to an exemplary embodiment of the inventive conceptLayer 143 may include a chalcogenide switching material having a composition according to formula 1 or 2. Accordingly, the selection device layer 143 may have stable switching characteristics, low off-current, and the memory device 100 may have a 3D cross-point stack structure having relatively high reliability.
A memory device including a chalcogenide switching material according to an exemplary embodiment of the inventive concept will be described in more detail with reference to fig. 5 and 6A to 6C.
Fig. 5 is a ternary phase diagram illustrating a composition range of a chalcogenide switching material according to an exemplary embodiment of the inventive concept.
Referring to fig. 5, a chalcogenide switching material according to an exemplary embodiment of the inventive concept may have a first composition range R1 and a second composition range R2 according to chemical formula 1. For example, the first composition range R1 may correspond to a composition of a ternary chalcogenide switching material comprising Ge in an amount from about 20 at% to about 40 at%, Se in an amount from about 40 at% to about 70 at%, and Te in an amount from about 5 at% to about 25 at%, and the second composition range R2 may correspond to a composition of a ternary chalcogenide switching material comprising Ge in an amount from about 25 at% to about 35 at%, Se in an amount from about 45 at% to about 65 at%, and Te in an amount from about 10 at% to about 20 at%.
Fig. 6A to 6C are graphs illustrating characteristics of a memory device including a chalcogenide switching material according to an exemplary embodiment of the inventive concept.
The off current 6A _ R2, volatilization temperature 6B _ R2, and endurance 6C _ R2 of the ternary chalcogenide switching material having the second composition range R2 are shown in fig. 6A to 6C, respectively. In fig. 6A to 6C, respective values of the off-current 6A _ R2, the volatilization temperature 6B _ R2, and the endurance 6C _ R2 are described as arbitrary units.
Referring to fig. 6A, a ternary chalcogenide switching material having a second compositional range R2 may exhibit a relatively low off-current over substantially the entire region of the compositional range of the ternary chalcogenide switching material. For example, a ternary chalcogenide switching material having a second compositional range of R2 may have an off current of several tens of pA, which may be significantly lower than the off current obtainable with chalcogenide materials having conventional Ovonic Threshold Switching (OTS) characteristics. Furthermore, an off current of several tens of pA may correspond to a relatively low level of current that may be obtained in conventional diode-type switching devices.
Referring to fig. 6B and 6C, ternary chalcogenide switching materials having a second composition range R2 may exhibit relatively high thermal stability and durability. For example, referring to fig. 6B, the volatilization temperature of the ternary chalcogenide switching material can increase as the Ge content increases from about 20 at% to about 40 at%.
Referring also to fig. 6C, the endurance of the ternary chalcogenide switching material may increase as the content of Te increases from about 5 at% to about 25 at% and/or the content of Ge increases from about 20 at% to about 40 at%.
A chalcogenide switching material according to an exemplary embodiment of the inventive concept may include Ge in an amount of about 20 at% to 40 at%, Se in an amount of about 40 at% to about 70 at%, and Te in an amount of about 5 at% to about 25 at%. The chalcogenide switching material may have relatively high thermal stability and low off-current because the chalcogenide switching material includes Ge in an amount of about 20 at% to 40 at%, and may have reduced off-current because the chalcogenide switching material includes Se in an amount of about 40 at% to about 70 at%, and may have increased durability because the chalcogenide switching material includes Te in an amount of about 5 at% to about 25 at%. In addition, the chalcogenide switching material does not include Si, and thus the select device layer 143 having relatively high film quality may be formed. Accordingly, the memory device may exhibit a relatively low off current, a relatively high thermal stability, and a relatively high excellent reliability.
Fig. 7 to 10 are each a cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept. The same description as that described above with reference to fig. 2 and 3 may be omitted below.
Referring to fig. 7, a memory device 100a according to an exemplary embodiment of the inventive concept may be different from the memory device 100 described above with reference to fig. 3 in that the lower electrode layer 141 and the selection device layer 143 are formed in a damascene structure. As an example, in the memory device 100a according to an exemplary embodiment of the inventive concept, the lower electrode layer 141 and the selection device layer 143 may be formed through a damascene process, and the middle electrode layer 145, the heating electrode layer 147, the variable resistance layer 149, and the upper electrode layer 148 may be formed through an etching process. Accordingly, the lower electrode layer 141 and the selection device layer 143 may have a structure in which the width thereof decreases in the downward direction. The downward direction may be orthogonal to the upper surface of the substrate 101.
In the memory device 100a according to an exemplary embodiment of the inventive concept, the lower spacer 152 may be formed on side surfaces of the lower electrode layer 141 and the selection device layer 143. In the memory device 100a according to an exemplary embodiment of the inventive concept, when the lower electrode layer 141 and the selection device layer 143 are formed through a damascene process, the lower spacer 152 may be previously formed on the side surface of the trench, and thereafter, the lower electrode layer 141 and the selection device layer 143 may be formed. Accordingly, the memory device 100a according to an exemplary embodiment of the inventive concept may include a lower spacer 152 on side surfaces of the lower electrode layer 141 and the selection device layer 143. According to an exemplary embodiment of the inventive concept, the lower spacer 152 may be omitted.
Referring to fig. 8, a memory device 100b according to an exemplary embodiment of the inventive concept may be different from the memory device 100 described above with reference to fig. 3 in that the variable resistance layer 149 may be formed in a damascene structure. As an example, in the memory device 100b according to an exemplary embodiment of the inventive concept, the lower electrode layer 141, the selection device layer 143, the middle electrode layer 145, the heating electrode layer 147, and the upper electrode layer 148 may be formed by an etching method, and the variable resistance layer 149 may be formed by a damascene process. In the memory device 100b according to an exemplary embodiment of the inventive concept, the upper spacer 155 may be formed on a side surface of the variable resistance layer 149. The upper spacers 155 may be formed in the same manner as the lower spacers 152 in the memory device 100a described with reference to fig. 7. For example, a trench may be formed in the insulating layer, an upper spacer 155 may be formed on a side surface of the trench, and the material of the variable resistance layer 149 may fill the remaining space in the trench. However, according to an exemplary embodiment of the inventive concept, the upper spacer 155 may be omitted.
Referring to fig. 9, a memory device 100c according to an exemplary embodiment of the inventive concept is different from the memory device 100b described with reference to fig. 8 in that a variable resistance layer 149 may be formed in a damascene structure to have an "L" shaped structure. As an example, in the memory device 100c according to an exemplary embodiment of the inventive concept, the lower electrode layer 141, the selection device layer 143, the middle electrode layer 145, the heating electrode layer 147, and the upper electrode layer 148 may be formed by an etching method, and the variable resistance layer 149 may be formed by a damascene process.
In the memory device 100c according to an exemplary embodiment of the inventive concept, the upper spacer 155 may be formed on a side surface of the variable resistance layer 149. However, since the variable resistance layer 149 is formed to have an "L" shaped structure, the upper spacer 155 may be formed to have an asymmetric structure. The variable resistance layer 149 having the "L" shaped structure may be formed by a damascene process. The damascene process will be described in more detail below. An insulating layer for the formation of the upper spacer 155 may be formed on the heating electrode layer 147, and a trench may be formed in the insulating layer. The trench may be formed wide to overlap adjacent memory cells 140 (e.g., in a direction orthogonal to the upper surface of the substrate 101). Next, a first material layer that will construct the variable resistance layer may be conformally formed in the trench and on the insulating layer, after which a second material layer that will form the upper spacer may be formed on the first material layer. A Chemical Mechanical Polishing (CMP) process may then be performed to planarize and expose the upper surface of the insulating layer. After planarization, a mask pattern aligned with the memory cell 140 may be formed, and the first material layer and the second material layer may be etched by using the mask pattern to form the variable resistance layer 149 of the "L" shape and the upper spacer 155.
Referring to fig. 10, a memory device 100d according to an exemplary embodiment of the inventive concept is different from the memory device 100c described above with reference to fig. 9 in that the variable resistance layer 149 may be formed in a dash structure. The variable-resistance layer 149 of the dash structure may be formed in a manner similar to that of the variable-resistance layer 149 of the "L" shaped structure. For example, a first material layer for forming the variable resistance layer 149 may be conformally formed in the trench and on the insulating layer, and thereafter, the first material layer may be left only on the sidewalls of the trench by anisotropic etching. Thereafter, a second material layer may be formed to cover the first material layer. Planarization may be performed by a CMP process to expose the upper surface of the insulating layer. After the planarization process, a mask pattern aligned with the memory cell 140 may be formed, and the second material layer may be etched by using the mask pattern to form the variable resistance layer 149 and the upper spacer 155 of the dash structure.
Fig. 11 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 12 is a cross-sectional view taken along lines 2X-2X 'and 2Y-2Y' of fig. 11. The same description as that described above with reference to fig. 2 and 3 may be omitted below.
Referring to fig. 11 and 12, the memory device 200 may include a first electrode line layer 110L, a second electrode line layer 120L, a third electrode line layer 130L, a first memory cell layer MCL1, and a second memory cell layer MCL2 over a substrate 101.
An insulating interlayer 105 may be disposed on the substrate 101. The first electrode line layer 110L may include a plurality of first electrode lines 110 extending parallel to each other in a first direction (e.g., X direction). The second electrode line layer 120L may include a plurality of second electrode lines 120 extending parallel to each other in a second direction (e.g., Y direction) perpendicular to the first direction. The third electrode line layer 130L may include a plurality of third electrode lines 130 extending parallel to each other in the first direction (e.g., the X direction). The third electrode lines 130 may be identical to the first electrode lines 110 in an extending direction or arrangement structure except for their positions in a third direction (e.g., Z direction). Accordingly, the third line 130 may be referred to as a first electrode line in the third electrode line layer 130L.
In view of driving the memory device 200, the first electrode lines 110 and the third electrode lines 130 may each be in a position corresponding to a word line, and the second electrode lines 120 may each be in a position corresponding to a bit line. Alternatively, the first electrode lines 110 and the third electrode lines 130 may each be in a position corresponding to a bit line, and the second electrode lines 120 may each be in a position corresponding to a word line. When the first electrode lines 110 and the third electrode lines 130 are in positions corresponding to word lines, the first electrode lines 110 may each be in a position corresponding to a lower word line, the third electrode lines 130 may each be in a position corresponding to an upper word line, and the second electrode lines 120 may each be in a position corresponding to a common bit line shared by the lower word line and the upper word line.
The first electrode lines 110, the second electrode lines 120, and the third electrode lines 130 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. Further, the first electrode lines 110, the second electrode lines 120, and the third electrode lines 130 may each include a metal layer and a conductive barrier layer at least partially covering the metal layer.
The first memory cell layer MCL1 may include a plurality of first memory cells 140-1 spaced apart from each other in a first direction and a second direction. The second memory cell layer MCL2 may include a plurality of second memory cells 140-2 spaced apart from each other in the first direction and the second direction. The first electrode lines 110 and the second electrode lines 120 cross each other, and the second electrode lines 120 and the third electrode lines 130 may cross each other. The first memory cell 140-1 may be located on a portion where the first and second electrode lines 110 and 120 cross each other between the first and second electrode line layers 110L and 120L. The second memory cells 140-2 may be located on a portion where the second electrode lines 120 and the third electrode lines 130 cross each other between the second electrode line layer 120L and the third electrode line layer 130L.
The first memory cell 140-1 may include a lower electrode layer 141-1, a selection device layer 143-1, an intermediate electrode layer 145-1, a heating electrode layer 147-1, a variable resistance layer 149-1, and an upper electrode layer 148-1.
The second memory cell 140-2 may include a lower electrode layer 141-2, a selection device layer 143-2, an intermediate electrode layer 145-2, a heating electrode layer 147-2, a variable resistance layer 149-2, and an upper electrode layer 148-2.
Accordingly, the first memory cell 140-1 and the second memory cell 140-2 may have substantially the same structure.
The first insulating layer 160a may be positioned between the adjacent first electrode lines 110, and the second insulating layer 160b may be positioned between the adjacent first memory cells 140-1 of the first memory cells MCL 1. The third insulating layer 160c may be positioned between the adjacent second electrode lines 120, the fourth insulating layer 160d may be positioned between the adjacent second memory cells 140-2 of the second memory cell layer MCL2, and the fifth insulating layer 160e may be positioned between the adjacent third electrode lines 130. The first to fifth insulating layers 160a to 160e may include the same material as each other, or at least one of the first to fifth insulating layers 160a to 160e may include a material different from the other of the first to fifth insulating layers 160a to 160 e. The first to fifth insulating layers 160a to 160e may include a dielectric material of oxide or nitride, and may electrically isolate devices from each other in each layer. Further, an air gap may be formed instead of at least one of the second and fourth insulating layers 160b and 160 d. When the air gap is formed, an insulating spacer having a predetermined thickness may be formed between the air gap and the first memory cell 140-1 and/or between the air gap and the second memory cell 140-2.
The memory device 200 according to an exemplary embodiment of the inventive concept may have a structure in which the memory devices 100 having the structures described with reference to fig. 2 and 3 are repeatedly stacked. However, the memory device 200 is not limited thereto. For example, the memory device 200 according to an exemplary embodiment of the inventive concept may have a structure in which the memory devices 100a, 100b, 100c, and/or 100d of the various structures described with reference to fig. 7 to 10 are stacked.
Fig. 13 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 14 is a cross-sectional view taken along lines 3X-3X 'and 3Y-3Y' of fig. 13. The same description as that described above with reference to fig. 2, 3, 11, and 12 may be omitted below.
Referring to fig. 13 and 14, a memory device 300 according to an exemplary embodiment of the inventive concept may have a four-layer structure including four memory cell layers MCL1, MCL2, MCL3, and MCL 4. As an example, the first memory cell layer MCL1 may be positioned between the first electrode line layer 110L and the second electrode line layer 120L, and the second memory cell layer MCL2 may be positioned between the second electrode line layer 120L and the third electrode line layer 130L. The second insulating interlayer 170 may be disposed on the third electrode line layer 130L, and the first upper electrode line layer 210L, the second upper electrode line layer 220L, and the third upper electrode line layer 230L may be positioned above the second insulating interlayer 170. The first upper electrode line layer 210L includes first upper electrode lines 210 having the same structure as the first electrode lines 110, the second upper electrode line layer 220L includes second upper electrode lines 220 having the same structure as the second electrode lines 120, and the third upper electrode line layer 230L includes third upper electrode lines 230 having the same structure as the third electrode lines 130 or the first electrode lines 110. The first upper memory cell layer MCL3 may be positioned between the first upper electrode line layer 210L and the second upper electrode line layer 220L, and the second upper memory cell layer MCL4 may be positioned between the second upper electrode line layer 220L and the third upper electrode line layer 230L.
According to an exemplary embodiment of the inventive concept, the first upper memory cell layer MCL3 may include a plurality of first upper memory cells 240-1 spaced apart from each other in the first and second directions. The second upper memory cell layer MCL4 may include a plurality of second upper memory cells 240-2 spaced apart from each other in the first direction and the second direction.
The first upper memory cell 240-1 may include a lower electrode layer 241-1, a selection device layer 243-1, an intermediate electrode layer 245-1, a heater electrode layer 247-1, a variable resistance layer 249-1, and an upper electrode layer 248-1.
The second upper memory cell 240-2 may include a lower electrode layer 241-2, a selection device layer 243-2, an intermediate electrode layer 245-2, a heater electrode layer 247-2, a variable resistance layer 249-2, and an upper electrode layer 248-2.
Accordingly, the first upper memory cell 240-1 and the second upper memory cell 240-2 may have substantially the same structure.
The first to third electrode line layers 110L to 130L and the first and second memory cells MCL1 and MCL2 are substantially the same as those described above with reference to fig. 2, 3, 11, and 12. Also, the first to third upper electrode line layers 210L to 230L and the first and second upper memory cell layers MCL3 and MCL4 may be substantially the same as the first to third electrode line layers 110L to 130L and the first and second memory cell layers MCL1 and MCL2, except that they are located on the second insulating interlayer 170 instead of the first insulating interlayer 105.
The memory device 300 according to an exemplary embodiment of the inventive concept may have a structure in which the memory devices 100 having the structures described with reference to fig. 2 and 3 are repeatedly stacked, but the exemplary embodiment of the inventive concept is not limited thereto. For example, the memory device 300 according to an exemplary embodiment of the inventive concept may have a structure in which the memory devices 100a, 100b, 100c, and/or 100d having various structures described with reference to fig. 7 to 10 are stacked.
Fig. 15 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 16 is a cross-sectional view taken along line 4X-4X' of fig. 15. The same description as that described above with reference to fig. 2, 3, 11, and 12 may be omitted below.
Referring to fig. 15 and 16, the memory device 400 may include a driving circuit region 410 located at a first level above the substrate 101 in a direction orthogonal to the upper surface of the substrate 101, and the first and second memory cell layers MCL1 and MCL2 may be located at a second level above the substrate 101 in a direction orthogonal to the upper surface of the substrate 101.
Here, "horizontal" may refer to a height along a direction orthogonal to the upper surface of the substrate 101 (e.g., the Z direction shown in fig. 15 and 16). Above the substrate 101, the first level is closer to the substrate 101 than the second level.
The driving circuit region 410 may be a region where peripheral circuits or driving circuits for driving memory cells in the first and second memory cell layers MCL1 and MCL2 are located. For example, the peripheral circuit located in the driving circuit region 410 may be a circuit capable of processing data input to/output from the first and second memory cell layers MCL1 and MCL2 at a high speed. For example, the peripheral circuits may include a page buffer, a latch circuit, a buffer circuit, a column decoder, a sense amplifier, a data input/output circuit, or a row decoder.
An active area AC for a driving circuit may be defined on the substrate 101 through the isolation layer 104. The plurality of transistors TR forming the driving circuit region 410 may be located in the active region AC of the substrate 101. Each of the plurality of transistors TR may include a gate G, a gate insulating layer GD, and source/drain regions SD. Opposite sidewalls of the gate G may be covered by the insulating spacers 106, and an etch stop layer 108 may be formed on the gate G and the insulating spacers 106. An etch stop layer 108 may be formed on the upper surface 101T of the isolation layer 104. The etch stop layer 108 may be in direct contact with the upper surface 101T of the isolation layer 104 above the substrate 101. The etch stop layer 108 may comprise an insulating material such as silicon nitride or silicon oxynitride.
A plurality of insulating interlayers 412A, 412B, and 412C may be sequentially stacked on the etch stop layer 108. The plurality of insulating interlayers 412A, 412B, and 412C may each include silicon oxide, silicon nitride, or silicon oxynitride.
The driving circuit region 410 may include a multi-layer wiring structure 414 electrically connected to the plurality of transistors TR. The multilayer wiring structure may be insulated from each other by the plurality of insulating interlayers 412A, 412B, and 412C.
The multilayer wiring structures 414 may each include a first contact 416A, a first wiring layer 418A, a second contact 416B, and a second wiring layer 418B that are sequentially stacked on the substrate 101 and electrically connected to each other. In an exemplary embodiment of the inventive concept, the first and second wiring layers 418A and 418B may include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the first wiring layer 418A and the second wiring layer 418B may include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, cobalt silicide, tantalum silicide, or nickel silicide.
Referring to fig. 16, the multilayer wiring structure 414 may have a dual-layer wiring structure including a first wiring layer 418A and a second wiring layer 418B, but exemplary embodiments of the inventive concept are not limited to the exemplary embodiment of the inventive concept described with reference to fig. 16. For example, the multilayer wiring structure 414 may include three or more wiring layer structures according to the layout of the driving circuit region 410 and the arrangement of the gate electrodes G.
The insulating interlayer 105 may be formed on the plurality of insulating interlayers 412A, 412B, and 412C. The first and second memory cell layers MCL1 and MCL2 may be disposed over the insulating interlayer 105.
The wiring structure connected between the first and second memory cell layers MCL1 and MCL2 and the driving circuit region 410 may penetrate the insulating interlayer 105.
As an example, in the memory device 400, since the first and second memory cell layers MCL1 and MCL2 are located in the driving circuit region 410, the integration degree of the memory device 400 may be further increased.
Fig. 17 to 19 are cross-sectional views illustrating a process of manufacturing the memory device of fig. 2 according to an exemplary embodiment of the inventive concept.
Referring to fig. 17, an insulating interlayer 105 may be disposed on the substrate 101. The insulating interlayer 105 may include, for example, silicon oxide or silicon nitride; however, the exemplary embodiments of the inventive concept are not limited thereto. A first electrode line layer 110L including a plurality of first electrode lines 110 extending in a first direction (e.g., X direction) and spaced apart from each other may be located above the insulating interlayer 105. The first electrode lines 110 may be formed through an etching process or a damascene process described herein. The materials included in the first electrode lines 110 are described above, for example, with reference to fig. 2 and 3. The first insulating layer 160a extending in the first direction may be located between the adjacent first electrode lines 110.
The lower electrode material layer 141k, the selection device material layer 143k, the middle electrode material layer 145k, the heating electrode material layer 147k, the variable resistance material layer 149k, and the upper electrode material layer 148k may be sequentially stacked on the first electrode line layer 110L and the first insulating layer 160a to form a stacked structure 140 k. The materials and functions of the material layers included in the stacked structure 140k have been described above, for example, with reference to fig. 2 and 3.
The selection device material layer 143k may be formed by a Physical Vapor Deposition (PVD) process using a target including a chalcogenide switching material (e.g., a chalcogenide switching material according to chemical formula 1 described in more detail above, for example, with reference to fig. 2) including Ge, Se, and Te and selectively including at least one selected from B, C, N, O, P or S as an additional element (X). Alternatively, the selection device material layer 143k may be formed by a PVD process using a target including a chalcogenide switching material (e.g., a chalcogenide switching material according to chemical formula 2 described in more detail above, for example, with reference to fig. 2) including Ge, Se, Te, and As and selectively including at least one selected from B, C, N, O, P or S As an additive element (X). In an exemplary embodiment of the inventive concept, the selection device material layer 143k may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process using a source including a chalcogenide switching material according to chemical formula 1 or chemical formula 2.
The chalcogenide switching material according to chemical formula 1 and chemical formula 2 may not include Si. If the chalcogenide switching material includes Si, silicon particles may coalesce and separate in the target during the target formation process or pores may occur in the target, and thus in select device material layer 143k, silicon particles may coalesce and separate or pores may be formed, and thus the film quality of select device material layer 143k may be relatively low. However, the chalcogenide switching material according to chemical formula 1 or chemical formula 2 does not include Si, and thus the select device material layer 143k formed through the PVD process may have a relatively high film quality.
Referring to fig. 18, after forming the stacked structure 140k (see, e.g., fig. 17), mask patterns spaced apart from each other in a first direction (e.g., an X direction) and a second direction (e.g., a Y direction) may be formed on the stacked structure 140 k. Thereafter, the stacked structure 140k may be etched by using the mask pattern such that the upper surfaces of the first insulating layer 160a and the first electrode lines 110 are partially exposed to form a plurality of memory cells 140.
The memory cells 140 may be spaced apart from each other in the first and second directions according to the shape of the mask pattern, and may be electrically connected to the first electrode lines 110 therebelow. In addition, the memory cells 140 may each include a lower electrode layer 141, a selection device layer 143, an intermediate electrode layer 145, a heating electrode layer 147, a variable resistance layer 149, and an upper electrode layer 148. After the memory cell 140 is formed, the remaining mask pattern may be removed through an ashing process and a stripping process.
The memory cell 140 may be formed by an etching process; however, the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment of the inventive concept, the memory cell 140 may be formed through a damascene process described herein. For example, when the variable resistance layer 149 in the memory cell 140 is formed by a damascene process, the insulating material layer may be first formed and then may be etched to form a trench exposing the upper surface of the heating electrode layer 147. Thereafter, a phase change material may be filled in the trench, and then planarization may be performed by using a CMP process to form the variable resistance layer 149.
Referring to fig. 19, a second insulating layer 160b filling between adjacent ones of the memory cells 140 may be formed. The second insulating layer 160b may include the same oxide or nitride material as that of the first insulating layer 160a and/or a different oxide or nitride material. The insulating material layer may be formed to have a sufficient thickness to completely fill the space between the memory cells 140 and then planarized by a CMP process to expose the upper surface of the upper electrode layer 148 and form the second insulating layer 160 b.
A conductive layer for forming the second electrode line layer may be formed and patterned through an etching process to form the second electrode lines 120. The second electrode lines 120 may extend in a second direction (e.g., Y direction) and may be spaced apart from each other. A third insulating layer 160c extending in the second direction may be located between the adjacent second electrode lines 120. The second electrode lines 120 may be formed by an etching process; however, the exemplary embodiments of the inventive concept are not limited thereto. For example, the second electrode lines 120 may be formed by a damascene process. When the second electrode lines 120 are formed by a damascene process, an insulating material layer may be formed on the memory cells 140 and the second insulating layer 160b, and the insulating material layer may be etched to form a trench extending in the second direction and exposing the upper surface of the variable resistance layer 149. Thereafter, the trench may be filled with a conductive material and planarized to form the second electrode line 120. An insulating material layer filled between the adjacent memory cells 140 may be formed to be relatively thick and planarized, and then, trenches may be formed in the insulating material layer to form the second electrode lines 120. Therefore, the second insulating layer and the third insulating layer can be integrally formed (for example, formed in an integral type) by using the same material.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept.
This application claims priority to korean patent application No. 10-2017-0038666, filed by the korean intellectual property office on 3/27 of 2017, the disclosure of which is incorporated herein by reference in its entirety.

Claims (25)

1. A memory device, comprising:
a variable resistance layer; and
a selection device layer electrically connected to the variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to the following chemical formula 1,
[GeASeBTeC](1-U)[X]U·················(1)
wherein 0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
2. The memory device of claim 1, wherein in the chemical formula 1, a ranges from 0.25 to 0.35, B ranges from 0.45 to 0.65, and C ranges from 0.10 to 0.20.
3. The memory device according to claim 1, wherein in the chemical formula 1, U ranges from 0.001 to 0.20 when X is boron (B), ranges from 0.001 to 0.10 when X is carbon (C), ranges from 0.08 to 0.20 when X is nitrogen (N), ranges from 0.001 to 0.08 when X is phosphorus (P), and ranges from 0.001 to 0.08 when X is sulfur (S).
4. The memory device of claim 1, wherein the chalcogenide switching material has a composition according to the following chemical formula 2, wherein arsenic (As) is further added to the chemical formula 1,
[GeASeBTeCAsD](1-U)[X]U···················(2)
wherein 0.20. ltoreq. A.ltoreq.0.35, 0.45. ltoreq. B.ltoreq.0.65, 0.04. ltoreq. C.ltoreq.0.18, 0.0. ltoreq. D.ltoreq.0.18, A + B + C + D.ltoreq.1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
5. The memory device of claim 4, wherein in the chemical formula 2, A ranges from 0.20 to 0.30, B ranges from 0.45 to 0.60, C ranges from 0.04 to 0.18, and D ranges from 0.04 to 0.18.
6. The memory device of claim 1, wherein the chalcogenide switching material does not include silicon (Si).
7. The memory device of claim 1, wherein the chalcogenide switching material does not include antimony (Sb).
8. The memory device of claim 1, wherein the chalcogenide switching material is configured to have an Ovonic Threshold Switch (OTS) characteristic.
9. The memory device of claim 1, wherein the variable resistance layer comprises a chalcogenide memory material having a composition different from a composition of the chalcogenide switching material, the chalcogenide memory material including at least two selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), or selenium (Se).
10. The memory device of claim 9, wherein the chalcogenide memory material further comprises at least one selected from boron (B), carbon (C), nitrogen (N), or oxygen (O), and the chalcogenide memory material has a melting point of less than 800 ℃.
11. A memory device, comprising:
a plurality of first electrode lines located above a substrate and extending in a first direction parallel to an upper surface of the substrate;
a plurality of second electrode lines positioned above the plurality of first electrode lines and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction;
a plurality of third electrode lines positioned above the plurality of second electrode lines and extending in the first direction; and
a plurality of memory cells formed between the plurality of first electrode lines and the plurality of second electrode lines at points where the plurality of first electrode lines and the plurality of second electrode lines cross each other and formed between the plurality of second electrode lines and the plurality of third electrode lines at points where the plurality of second electrode lines and the plurality of third electrode lines cross each other, respectively,
wherein each of the plurality of memory cells includes a selection device layer and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to the following chemical formula 1,
[GeASeBTeC](1-U)[X]U··················(1)
wherein 0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
12. The memory device of claim 11, wherein in the chemical formula 1, a ranges from 0.25 to 0.35, B ranges from 0.45 to 0.65, and C ranges from 0.10 to 0.20.
13. The memory device of claim 11, wherein in the chemical formula 1, U ranges from 0.001 to 0.20 when X is boron (B), ranges from 0.001 to 0.10 when X is carbon (C), ranges from 0.08 to 0.20 when X is nitrogen (N), ranges from 0.001 to 0.08 when X is phosphorus (P), and ranges from 0.001 to 0.08 when X is sulfur (S).
14. The memory device of claim 11, wherein the chalcogenide switching material has a composition according to the following chemical formula 2, wherein arsenic (As) is further added to the chemical formula 1,
[GeASeBTeCAsD](1-U)[X]U·····················(2)
wherein 0.20. ltoreq. A.ltoreq.0.35, 0.45. ltoreq. B.ltoreq.0.65, 0.04. ltoreq. C.ltoreq.0.18, 0.0. ltoreq. D.ltoreq.0.18, A + B + C + D.ltoreq.1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
15. The memory device of claim 14, wherein in the chemical formula 2, a ranges from 0.20 to 0.30, B ranges from 0.45 to 0.60, C ranges from 0.04 to 0.18, and D ranges from 0.04 to 0.18.
16. The memory device of claim 11, wherein the chalcogenide switching material does not include silicon (Si).
17. The memory device of claim 11, wherein the chalcogenide switching material does not include antimony (Sb).
18. The memory device of claim 11, wherein the variable resistance layer has any one selected from a pillar structure, a cone structure, or an L-shaped structure.
19. The memory device of claim 11, wherein each of the plurality of memory cells further comprises a first electrode layer, a second electrode layer, and a third electrode layer, wherein the selection device layer is located between the first electrode layer and the second electrode layer, and wherein the variable resistance layer is located between the second electrode layer and the third electrode layer.
20. The memory device according to claim 19, wherein the first electrode layer, the second electrode layer, and the third electrode layer each comprise at least one selected from carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN).
21. A memory device, comprising:
a plurality of first electrode lines located above a substrate and extending in a first direction parallel to an upper surface of the substrate;
a plurality of second electrode lines positioned above the plurality of first electrode lines and extending in a second direction parallel to the upper surface of the substrate, wherein the second direction is perpendicular to the first direction;
a plurality of memory cells formed at points where the plurality of first electrode lines and the plurality of second electrode lines cross each other between the plurality of first electrode lines and the plurality of second electrode lines, respectively,
wherein each of the plurality of memory cells includes a selection device layer and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to the following chemical formula 1,
[GeASeBTeC](1-U)[X]U···················(1)
wherein 0.20. ltoreq. A.ltoreq.0.40, 0.40. ltoreq. B.ltoreq.0.70, 0.05. ltoreq. C.ltoreq.0.25, A + B + C1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
22. The memory device of claim 21, wherein in the chemical formula 1, a ranges from 0.25 to 0.35, B ranges from 0.45 to 0.65, and C ranges from 0.10 to 0.20.
23. The memory device of claim 21, wherein in the chemical formula 1, U ranges from 0.001 to 0.20 when X is boron (B), ranges from 0.001 to 0.10 when X is carbon (C), ranges from 0.08 to 0.20 when X is nitrogen (N), ranges from 0.001 to 0.08 when X is phosphorus (P), and ranges from 0.001 to 0.08 when X is sulfur (S).
24. The memory device of claim 21, wherein the chalcogenide switching material has a composition according to the following chemical formula 2, wherein arsenic (As) is further added to the chemical formula 1,
[GeASeBTeCAsD](1-U)[X]U·····················(2)
wherein 0.20. ltoreq. A.ltoreq.0.35, 0.45. ltoreq. B.ltoreq.0.65, 0.04. ltoreq. C.ltoreq.0.18, 0.0. ltoreq. D.ltoreq.0.18, A + B + C + D1, 0.0. ltoreq. U.ltoreq.0.20, and wherein X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S).
25. The memory device of claim 24, wherein in the chemical formula 2, a ranges from 0.20 to 0.30, B ranges from 0.45 to 0.60, C ranges from 0.04 to 0.18, and D ranges from 0.04 to 0.18.
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